Flip Flop

Triggering Methods
The output of a flip flop can be changed by bring a small change in the input signal. This small change
can be brought with the help of a clock pulse or commonly known as a trigger pulse.

When such a trigger pulse is applied to the input, the output changes and thus the flip flop is said to be
triggered. Flip flops are applicable in designing counters or registers which stores data in the form of
multi-bit numbers. But such registers need a group of flip flops connected to each other as sequential
circuits. And these sequential circuits require trigger pulses.

The number of trigger pulses that is applied to the input of the circuit determines the number in a
counter. A single pulse makes the bit move one position, when it is applied onto a register that stores
multi-bit data.

In the case of SR Flip Flops, the change in signal level decides the type of trigger that is to be given to the
input. But the original level must be regained before giving a second pulse to the circuit.

If a clock pulse is given to the input of the flip flop at the same time when the output of the flip flop is
changing, it may cause instability to the circuit. The reason for this instability is the feedback that is given
from the output combinational circuit to the memory elements. This problem can be solved to a certain
level by making the flip flop more sensitive to the pulse transition rather than the pulse duration.

There are mainly four types of pulse-triggering methods. They differ in the manner in which the
electronic circuits respond to the pulse. They are

1. High Level Triggering

When a flip flop is required to respond at its HIGH state, a HIGH level triggering method is used. It is
mainly identified from the straight lead from the clock input. Take a look at the symbolic representation
shown below.

2. Low Level Triggering

When a flip flop is required to respond at its LOW state, a LOW level triggering method is used. It is
mainly identified from the clock input lead along with a low state indicator bubble.
3. Positive Edge Triggering

When a flip flop is required to respond at a LOW to HIGH transition state, POSITIVE edge triggering
method is used. It is mainly identified from the clock input lead along with a triangle. Take a look at the
symbolic representation shown below.

4. Negative Edge Triggering

When a flip flop is required to respond during the HIGH to LOW transition state, a NEGATIVE edge
triggering method is used. It is mainly identified from the clock input lead along with a low-state
indicator and a triangle. Take a look at the symbolic representation shown below.
Clock Pulse Transition

The movement of a trigger pulse is always from a 0 to 1 and then 1 to 0 of a signal. Thus it takes two
transitions in a single signal. When it moves from 0 to 1 it is called a positive transition and when it
moves from 1 to 0 it is called a negative transition. To understand more take a look at the images below.

The clocked flip-flops already introduced are triggered during the 0 to 1 transition of the pulse, and the
state transition starts as soon as the pulse reaches the HIGH level. If the other inputs change while the
clock is still 1, a new output state may occur. If the flip-flop is made to then the multiple-transition
problem can be eliminated.

The multi-transition problem can be stopped is the flip flop is made to respond to the positive or negative
edge transition only, other than responding to the entire pulse duration.

Introduction of Sequential Circuits

Sequential circuits are digital circuits that store and use the previous state information to determine their
next state. Unlike combinational circuits, which only depend on the current input values to produce
outputs, sequential circuits depend on both the current inputs and the previous state stored in memory
elements.

1. Sequential circuits are commonly used in digital systems to implement state machines, timers,
counters, and memory elements. The memory elements in sequential circuits can be implemented
using flip-flops, which are circuits that store binary values and maintain their state even when
the inputs change.

2. There are two types of sequential circuits: finite state machines (FSMs) and synchronous
sequential circuits. FSMs are designed to have a limited number of states and are typically used
to implement state machines and control systems. Synchronous sequential circuits, on the other
hand, are designed to have an infinite number of states and are typically used to implement
timers, counters, and memory elements.

In summary, sequential circuits are digital circuits that store and use previous state information to
determine their next state. They are commonly used in digital systems to implement state machines,
timers, counters, and memory elements and are essential components in digital systems design.
Sequential circuit is a combinational logic circuit that consists of inputs variable (X), logic gates
(Computational circuit), and output variable (Z).

A combinational circuit produces an output based on input variables only, but a sequential
circuit produces an output based on current input and previous output variables. That means
sequential circuits include memory elements that are capable of storing binary information. That binary
information defines the state of the sequential circuit at that time. A latch is capable of storing one bit
of information.

As shown in the figure, there are two types of input to the combinational logic :

1. External inputs which are not controlled by the circuit.

2. Internal inputs, which are a function of a previous output state.
Secondary inputs are state variables produced by the storage elements, whereas secondary outputs are
excitations for the storage elements.

Types of Sequential Circuits:

There are two types of sequential circuits:

Type 1: Asynchronous sequential circuit: These circuits do not use a clock signal but uses the pulses of
the inputs. These circuits are faster than synchronous sequential circuits because there is clock pulse
and change their state immediately when there is a change in the input signal. We use asynchronous
sequential circuits when speed of operation is important and independent of internal clock pulse.
But these circuits are more difficult to design and their output is uncertain.

Type2: Synchronous sequential circuit: These circuits uses clock signal and level inputs (or pulsed) (with
restrictions on pulse width and circuit propagation). The output pulse is the same duration as the clock
pulse for the clocked sequential circuits. Since they wait for the next clock pulse to arrive to perform the
next operation, so these circuits are bit slower compared to asynchronous. Level output changes state at
the start of an input pulse and remains in that until the next input or clock pulse.

We use synchronous sequential circuit in synchronous counters, flip flops, and in the design of MOORE-
MEALY state management machines. We use sequential circuits to design Counters, Registers, RAM,
MOORE/MEALY Machine and other state retaining machines.

Advantages of Sequential Circuits:

1. Memory: Sequential circuits have the ability to store binary values, which makes them ideal for
applications that require memory elements, such as timers and counters.

2. Timing: Sequential circuits are commonly used to implement timing and synchronization in
digital systems, making them essential for real-time control applications.

3. State machine implementation: Sequential circuits can be used to implement state machines,
which are useful for controlling complex digital systems and ensuring that they operate as
intended.

4. Error detection: Sequential circuits can be designed to detect errors in digital systems and
respond accordingly, improving the reliability of digital systems.
Disadvantages of Sequential Circuits:

1. Complexity: Sequential circuits are typically more complex than combinational circuits and
require more components to implement.

2. Timing constraints: The design of sequential circuits can be challenging due to the need to ensure
that the timing of the inputs and outputs is correct.

3. Testing and debugging: Testing and debugging sequential circuits can be more difficult
compared to combinational circuits due to their complex structure and state-dependent outputs.

In conclusion, sequential circuits have their advantages and disadvantages, but they play an important
role in digital systems design due to their ability to store and use binary values, implement timing and
synchronization, and implement state machines.

Difference between combinational and sequential circuit

Combinational circuits are defined as the time independent circuits which do not depends upon
previous inputs to generate any output are termed as combinational circuits. Sequential circuits are
those which are dependent on clock cycles and depends on present as well as past inputs to generate any
output. Combinational Circuit –

1. In this output depends only upon present input.

2. Speed is fast.
3. It is designed easy.
4. There is no feedback between input and output.
5. This is time independent.
6. Elementary building blocks: Logic gates
7. Used for arithmetic as well as Boolean operations.
8. Combinational circuits don’t have capability to store any state.
9. As combinational circuits don’t have clock, they don’t require triggering.
10. These circuits do not have any memory element.
11. It is easy to use and handle.
Examples – Encoder, Decoder, Multiplexer, Demultiplexer

Block Diagram–
Sequential Circuit –

1. In this output depends upon present as well as past input.

2. Speed is slow.
3. It is designed tough as compared to combinational circuits.
4. There exists a feedback path between input and output.
5. This is time dependent.
6. Elementary building blocks: Flip-flops
7. Mainly used for storing data.
8. Sequential circuits have capability to store any state or to retain earlier state.
9. As sequential circuits are clock dependent they need triggering.
10. These circuits have memory element.
11. It is not easy to use and handle.

The combinational circuit does not use any memory. Hence the previous state of input does not have any
effect on the present state of the circuit. But sequential circuit has memory so output can vary based on
input. This type of circuits uses previous input, output, clock and a memory element.

Block diagram
Latches in Digital Logic

Latches are digital circuits that store a single bit of information and hold its value until it is updated by
new input signals. They are used in digital systems as temporary storage elements to store binary
information. Latches can be implemented using various digital logic gates, such as AND, OR, NOT,
NAND, and NOR gates.

There are two types of latches:

1. S-R (Set-Reset) Latches: S-R latches are the simplest form of latches and are implemented using
two inputs: S (Set) and R (Reset). The S input sets the output to 1, while the R input resets the
output to 0. When both S and R are at 1, the latch is said to be in an ‚undefined‛ state.

2. D (Data) Latches: D latches are also known as transparent latches and are implemented using two
inputs: D (Data) and a clock signal. The output of the latch follows the input at the D terminal as
long as the clock signal is high. When the clock signal goes low, the output of the latch is stored
and held until the next rising edge of the clock.

3. Latches are widely used in digital systems for various applications, including data storage,
control circuits, and flip-flop circuits. They are often used in combination with other digital
circuits to implement sequential circuits, such as state machines and memory elements.

4. In summary, latches are digital circuits that store a single bit of information and hold its value
until it is updated by new input signals. There are two types of latches: S-R (Set-Reset) Latches
and D (Data) Latches, and they are widely used in digital systems for various applications.

Latches are basic storage elements that operate with signal levels (rather than signal transitions). Latches
controlled by a clock transition are flip-flops. Latches are level-sensitive devices. Latches are useful for the
design of the asynchronous sequential circuit. Latches are sequential circuit with two stable states. These
are sensitive to the input voltage applied and does not depend on the clock pulse. Flip flops that do not
use clock pulse are referred to as latch.

SR (Set-Reset) Latch – They are also known as preset and clear states. The SR latch forms the basic
building blocks of all other types of flip-flops.

SR Latch is a circuit with:

i) 2 cross-coupled NOR gate or 2 cross-coupled NAND gate.

ii) 2 input S for SET and R for RESET.
iii) 2 output Q, Q’.
 Q Q’ STATE

1 0 Set

0 1 Reset

Under normal conditions, both the input remains 0. The following is the RS Latch with NAND gates:

Case-1: S’=R’=1 (S=R=0) –

If Q = 1, Q and R’ inputs for 2nd NAND gate are both 1.
If Q = 0, Q and R’ inputs for 2nd NAND gate are 0 and 1 respectively.

Case-2: S’=0, R’=1 (S=1, R=0) –

As S’=0, the output of 1st NAND gate, Q = 1(SET state). In 2nd NAND gate, as Q and R’ inputs are 1,
Q’=0.
Case-3: S’= 1, R’= 0 (S=0, R=1) –
As R’=0, the output of 2nd NAND gate, Q’ = 1. In 1st NAND gate, as Q and S’ inputs are 1, Q=0 (RESET
state).

Case-4: S’= R’= 0 (S=R=1) –

When S=R=1, both Q and Q’ becomes 1 which is not allowed. So, the input condition is prohibited.
The SR Latch using NOR gate is shown below:

Advantages of Latches:

1. Easy to Implement: Latches are simple digital circuits that can be easily implemented using
basic digital logic gates.

2. Low Power Consumption: Latches consume less power compared to other sequential circuits
such as flip-flops.
 3. High Speed: Latches can operate at high speeds, making them suitable for use in high -speed
digital systems.

4. Low Cost: Latches are inexpensive to manufacture and can be used in low-cost digital systems.

5. Versatility: Latches can be used for various applications, such as data storage, control circuits,
and flip-flop circuits.

Disadvantages of Latches:

1. No Clock: Latches do not have a clock signal to synchronize their operations, making their
behavior unpredictable.

2. Unstable State: Latches can sometimes enter into an unstable state when both inputs are at 1.
This can result in unexpected behavior in the digital system.

3. Complex Timing: The timing of latches can be complex and difficult to specify, making them
less suitable for real-time control applications.

Flip Flop

Flip flop is a sequential circuit which generally samples its inputs and changes its outputs only at
particular instants of time and not continuously. Flip flop is said to be edge sensitive or edge triggered
rather than being level triggered like latches.

Flip-flop is a circuit that maintains a state until directed by input to change the state. A basic flip-flop can
be constructed using four-NAND or four-NOR gates. Flip flop is popularly known as the basic digital
memory circuit. It has its two states as logic 1(High) and logic 0(low) states. A flip flop is a sequential
circuit which consist of single binary state of information or data. The digital circuit is a flip flop which
has two outputs and are of opposite states. It is also known as a Bistable Multivibrator.

Types of flip-flops:

1. SR Flip Flop

2. JK Flip Flop

3. D Flip Flop

4. T Flip Flop

Logic diagrams and truth tables of the different types of flip-flops are as follows:

S-R Flip Flop:

In the flip flop, with the help of preset and clear when the power is switched ON, the states of the circuit
keeps on changing, that is it is uncertain. It may come to set (Q=1) or reset (Q’=0) state. In many
applications, it is desired to initially set or reset the flip flop that is the initial state of the flip flop that
needs to be assigned. This thing is accomplished by the preset (PR) and the clear (CLR).
We can construct SR flip with two ways, one is with 2 NOR Gates + 2 AND Gates and other is with 4
NAND Gates.

S-R Flip Flop

Operations:
Case 1:
PR=CLR=1 The asynchronous inputs are inactive and the flip flop responds freely to the S,R and the
CLK inputs in the normal way.
Case 2:
PR=0 and CLR=1 This is used when the Q is set to 1.
Case 3:
PR=1 and CLR=0 This is used when the Q’ is set to 1.
Case 4:
PR=CLR=0 This is an invalid state.
Characteristics Equation for SR Flip Flop: QN+1 = QNR’ + SR’
Here clock pulse is supplied to operate this flip flop, hence it is clocked flip flop.

SR Flip Flop Construction using 2 AND + 2 NOR Gates:

 SR Flip Fop using two NOR and two AND Gates

Basic Block Diagram of SR Flip Flop

The basic block diagram contains S and R inputs, and between them is clock pulse, Q and Q’ is the
complemented outputs.

SR Flip Flop basic Block diagram

Working of SR Flip Flop

 Case 1: Let’s say, S=0 and R=0, then output of both AND gates will be 0 and the value of Q and
Q’ will be same as their previous value, i.e, Hold state.

 Case 2: Let’s say, S=0 and R=1, then output of both AND gates will be 1 and 0, correspondingly
the value of Q will be 0 as one of input is 1 and it is a NOR gate so it will ultimately give 0, hence
Q gets 0 value, similarly Q’ will be 1.

 Case 3: Let’s say, S=1 and R=0, then output of both AND gates will be 0 and 1, correspondingly
the value of Q’ will be 0 as one of input to NOR gate is 1, so output will be 0 ultimately and this 0
value will go as input to upper NOR gate, and hence Q will become 1.

 Case 4: Let’s say, S=1 and R=1, then output of both AND gates will be 1 and 1 which is invalid, as
the outputs should be complement of each other.

Truth Table of SR Flip Flop

Here, S is the Set input, R is the reset input,Qn+1 is the next state and State tells in which state it enters.

Characteristic Table of SR Flip Flop

Here, S is the Set input, R is the reset input, Qn is the current state input and Qn+1 is the next state
outputs.

Characteristic Equation

 The characteristic equation tells us about what will be the next state of flip flop in terms of
present state.

 In order to get the characteristic equation, K-Map is constructed which will be shown as below:
  If we solve the above K-Map then the characteristic equation will be Qn+1 = S + QnR’

Excitation Table

 Excitation Table basically tells about the excitation which is required by flip flop to go from
current state to next state.

 Here, Qn is the current state, Qn+1 is the next state outputs and S, R are the set and reset inputs
respectively.

Applications of SR Flip Flop

There are numerous applications of SR Flip Flop in Digital System, which are listed below:

 Register: SR Flip Flop used to create register. Designer can create any size of register by
combining SR Flip Flops.

 Counters: SR Flip Flops used in counters. Counters count the number of events that occurs in a
digital system.

 Memory: SR Flip Flops used to create memory which is used to store data, when the power is
turned off.
  Synchronous System: SR Flip Flop are used in synchronous system which are used to
synchronise the operation of different component.

Conclusion

We start from the basics of flip flops, that what actually are flip flops and then we discussed about the SR
Flip Flops, the two ways in which we can construct SR Flip Flops, it’s Basic Block Diagram, Working of
SR Flip Flop, it’s Truth table, Characteristic table, Characteristic equation as well as Excitation table and
in the end we discussed the Applications of SR Flip Flops.

J-K Flip Flop:

In Digital Electronics and communication science, flip-flops are widely used for handling binary
information. These fundamental building blocks are used to store and manipulate information as per our
needs. From the Flipflop family, Jack Kilby flip-flop(JK Flipflop) is very prominent as it is very versatile
and can be used as a basic memory element. It can store binary information, and toggle functionality with
a diversity of making applications with it. This article will cover all about JK flipflop.

JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock transitions or
negative clock transitions. The circuit diagram of JK flip-flop is shown in the following figure.
This circuit has two inputs J & K and two outputs Qt & Qt’. The operation of JK flip-flop is similar to SR
flip-flop. Here, we considered the inputs of SR flip-flop as S = J Qt’ and R = KQt in order to utilize the
modified SR flip-flop for 4 combinations of inputs.

The following table shows the state table of JK flip-flop.

J K Qt+1

0 0 Qt

0 1 0

1 0 1

1 1 Qt'

Here, Qt & Qt+1 are present state & next state respectively. So, JK flip-flop can be used for one of these
four functions such as Hold, Reset, Set & Complement of present state based on the input conditions,
when positive transition of clock signal is applied. The following table shows the characteristic table of
JK flip-flop.

Present Inputs Present State Next State

J K Qt Qt+1

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1
 1 0 1 1

1 1 0 1

1 1 1 0

By using three variables K-Map, we can get the simplified expression for next state, Qt+1. Three variables
K-Map for next state, Qt+1 is shown in the following figure.

The maximum possible groupings of adjacent ones are already shown in the figure. Therefore,
the simplified expression for next state Qt+1 is

Q(t+1)=JQ(t)′+K′Q(t)

JK Flip Flop using NAND Gates

In JK flip flops, the diagram over here represents the basic structure of the flip flop which consists of
Clock (CLK), Clear (CLR), Preset (PR).
Operations:

Case 1:

PR=CLR=0 This condition is in its invalid state.

Case 2:

PR=0 and CLR=1 The PR is activated which means the output in the Q is set to 1. Therefore, the flip flop is
in the set state.

Case 3:
PR=1 and CLR=0 The CLR is activated which means the output in the Q’ is set to 1. Therefore, the flip flop
is in the reset state.

Case 4:

PR=CLR=1 In this condition the flip flop works in its normal way whereas the PR and CLR gets
deactivated.

Race around condition:

When the J and K both are set to 1, the input remains high for a longer duration of time, then the output
keeps on toggling. Toggle means that switching in the output instantly i.e. Q=0, Q’=1 will immediately
change to Q=1 and Q’=0 and this continuation keeps on changing. This change in output leads to race
around condition.

Characteristics Equation for JK Flip Flop: QN+1 = JQ’N + K’QN

Memory Units: JK-flip flop itself act as a memory unit to store binary information. By making a sequential
chain of JK-flip flops we can use it even as RAM.

Applications of JK Flip-Flop

We can simply implement a JK-flipflop using NAND gates. In that case two NAND gates need to be
connected together and the output of that will be feed to the input which will create a stable state-holding
circuit. The resulting circuit will be the NAND gate. So, by following this mechanism we can develop and
use JK-flipflop for various application which are listed below.

Counters: These are very essential components for the application of frequency dividers and event
sequencers where there is a need of storing and propagating the count value. We can design binary
synchronous and asynchronous counters using JK-flip flop.

Shift registers: For data storage and manipulation, serial-to-parallel or parallel-to-serial data conversion
the shift registers are widely used. Registers can store and shift the binary data in a sequential manner.
We can design it by JK-flip flops.

Advantages of JK Flip-Flop

Versatility: As discussed above, JK-flipflops can be used as a basic memory element or a primary building
block of further complex memory design. It is very much adaptive as it can be operated in both
synchronous and asynchronous modes.

Toggle Functionality: The application which are required to get output as its complement of input that
also can be developed by JK-flipflops as when J=K=1 it triggers toggle state which gives output which is
complement with it’s each clock pulse.
Error Detection and Correction: We can use a complex circuit built by JK-flipflops which can detect and
correct information during data-transmission.

Disadvantages of JK Flip-Flop

Complexity: Compared to other types of flipflops (D,T, SR), JK flipflop requires additional logic gates to
implement which consumes extra memory resources and increases complexity to operate.

Propagation Delay: This is the major problem present in JK-FF. Propagation delay results a timing delay
in certain application which are time-flow sensitive.

Race Problem: This issue arises when the clock input’s timing pulse isn’t given enough time to turn ‚Off‛
before the output Q’s state is altered.

T Flip Flop:
T flip-flop is the simplified version of JK flip-flop. It is obtained by connecting the same input ‘T’ to both
inputs of JK flip-flop. It operates with only positive clock transitions or negative clock transitions.
The circuit diagram of T flip-flop is shown in the following figure:

This circuit has single input T and two outputs Qt & Qt’. The operation of T flip-flop is same as that of JK
flip-flop. Here, we considered the inputs of JK flip-flop as J = T and K = T in order to utilize the modified
JK flip-flop for 2 combinations of inputs. So, we eliminated the other two combinations of J & K, for
which those two values are complement to each other in T flip-flop. The following table shows the state
table of T flip-flop:

T Qt+1

0 Qt

1 Qt’
Here, Qt & Qt+1 are present state & next state respectively. So, T flip-flop can be used for one of these two
functions such as Hold, & Complement of present state based on the input conditions, when positive
transition of clock signal is applied. The following table shows the characteristic table of T flip-flop.

Present Next
Inputs
State State

T Qt Qt+1

0 0 0

0 1 1

1 0 1

1 1 0

From the above characteristic table, we can directly write the next state equation as

Q(t+1)=T′Q(t)+TQ(t)′

⇒Q(t+1)=T⊕Q(t)

The output of T flip-flop always toggles for every positive transition of the clock signal, when input T
remains at logic High 1. Hence, T flip-flop can be used in counters.

Similarly, we can implement these flip-flops by using NAND gates.

Characteristics Equation for T Flip Flop: QN+1 = Q’NT + QNT’ = QN XOR T

D Flip-Flop :

D Flip-Flop is a modified SR flip-flop which has an additional inverter. It prevents the inputs from
becoming the same value.

D flip-flop operates with only positive clock transitions or negative clock transitions. Whereas, D latch
operates with enable signal. That means, the output of D flip-flop is insensitive to the changes in the
input, D except for active transition of the clock signal. The circuit diagram of D flip-flop is shown in the
following figure.

The following table shows the state table of D flip-flop.

D Qt + 1

0 0

1 1

Therefore, D flip-flop always hold the information, which is available on data input, D of earlier positive
transition of clock signal.
Characteristics Equation for D Flip Flop: QN+1 = D

This circuit has single input D and two outputs Qt & Qt’. The operation of D flip-flop is similar to D
Latch. But, this flip-flop affects the outputs only when positive transition of the clock signal is applied
instead of active enable.

Next state of D flip-flop is always equal to data input, D for every positive transition of the clock signal.
Hence, D flip-flops can be used in registers, shift registers and some of the counters.

Master-Slave JK Flip

For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q output will toggle as long as CLK
is high, which makes the output of the flip-flop unstable or uncertain. This problem is called race around
condition in J-K flip-flop. In edge triggered race around not occurred. Race around condition occurs in
level triggered only. This problem (Race Around Condition) can be avoided by ensuring that the clock
input is at logic ‚1‛ only for a very short time. This introduced the concept of Master Slave JK flip
flop. Master Slave JK flip flop – The Master-Slave Flip-Flop is basically a combination of two JK flip-flops
connected together in a series configuration. Out of these, one acts as the ‚master‛ and the other as
a ‚slave‛. The output from the master flip flop is connected to the two inputs of the slave flip flop whose
output is fed back to inputs of the master flip flop. In addition, to these two flip-flops, the circuit also
includes an inverter. The inverter is connected to clock pulse in such a way that the inverted clock pulse
(CP) is given to the slave flip-flop. In other words, if CP=0 for a master flip-flop, then CP=1 for a slave
flip-flop and if CP=1 for master flip flop then it becomes 0 for slave flip flop.
Working of a master slave flip flop –

1. When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the
system. The slave flip-flop is isolated until the CP goes to 0. When the CP goes back to 0,
information is passed from the master flip-flop to the slave and output is obtained.

2. Firstly, the master flip flop is positive level triggered and the slave flip flop is negative level
triggered, so the master responds before the slave.

3. If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the clock
forces the slave to reset, thus the slave copies the master.

4. If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the Negative
transition of the clock sets the slave, copying the master.

5. If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on the
negative transition of the clock.

6. If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

Timing Diagram of a Master Slave flip flop –

 1. When the Clock pulse is high the output of master is high and remains high till the clock is low
because the state is stored.

2. Now the output of master becomes low when the clock pulse becomes high again and remains
low until the clock becomes high again.

3. Thus toggling takes place for a clock cycle.

4. When the clock pulse is high, the master is operational but not the slave thus the output of the
slave remains low till the clock remains high.

5. When the clock is low, the slave becomes operational and remains high until the clock again
becomes low.

6. Toggling takes place during the whole process since the output is changing once in a cycle.

This makes the Master-Slave J-K flip flop a Synchronous device as it only passes data with the timing of
the clock signal.

Conversion for Flip Flops:

EXCITATION TABLE:

Steps To Convert from One Flip Flop to Other:

Let there be required flip flop to be constructed using sub-flip flop:

1. Draw the truth table of the required flip-flop.

2. Write the corresponding outputs of sub-flip flop to be used from the excitation table.

3. Draw K-Maps using required flip flop inputs and obtain excitation functions for sub-flip flop
inputs.

4. Construct a logic diagram according to the functions obtained.

i) Convert SR To JK Flip Flop
Excitation Functions:

ii) Convert SR To D Flip Flop:

Excitation Functions: S = D, R = D‘

Applications of Flip-Flops:

These are the various types of flip-flops being used in digital electronic circuits and the applications of
Flip-flops are as specified below.

 Counters
 Frequency Dividers
 Shift Registers
 Storage Registers
 Bounce elimination switch
 Data storage
 Data transfer
 Latch
 Registers
 Memory