UART COMMUNICATION:

In UART communication, two UARTs communicate directly with each other. The transmitting
UART converts parallel data from a controlling device like a CPU into serial form, transmits it in serial to
the receiving UART, which then converts the serial data back into parallel data for the receiving device.
Only two wires are needed to transmit data between two UARTs. Data flows from the Tx pin of the
transmitting UART to the Rx pin of the receiving UART:

UARTs transmit data asynchronously, which means there is no clock signal to synchronize the
output of bits from the transmitting UART to the sampling of bits by the receiving UART. Instead of a
clock signal, the transmitting UART adds start and stop bits to the data packet being transferred. These
bits define the beginning and end of the data packet so the receiving UART knows when to start reading
the bits.

When the receiving UART detects a start bit, it starts to read the incoming bits at a
specific frequency known as the baud rate. Baud rate is a measure of the speed of data
transfer, expressed in bits per second (bps). Both UARTs must operate at about the same baud rate.

UART WORKING:

The UART that is going to transmit data receives the data from a data bus. The data bus is used
to send data to the UART by another device like a CPU, memory, or microcontroller. Data is transferred
from the data bus to the transmitting UART in parallel form. After the transmitting UART gets
the parallel data from the data bus, it adds a start bit, a parity bit, and a stop bit, creating the data
packet. Next, the data packet is output serially, bit by bit at the Tx pin. The receiving UART reads the
data packet bit by bit at its Rx pin. The receiving UART then converts the data back into parallel form and
removes the start bit, parity bit, and stop bits. Finally, the receiving UART transfers the data packet in
parallel to the data bus on the receiving end:
UART transmitted data is organized into packets. Each packet contains 1 start bit, 5 to 9 data bits
(depending on the UART), an optional parity bit, and 1 or 2 stop bits:

ADVANTAGES AND DISADVANTAGES OF UART:

ADVANTAGES

 Only uses two wires

 No clock signal is necessary

 Has a parity bit to allow for error checking

 The structure of the data packet can be changed as long as both sides are set up for it

 Well documented and widely used method

DISADVANTAGES

 The size of the data frame is limited to a maximum of 9 bits

 Doesn’t support multiple slave or multiple master systems

 The baud rates of each UART must be within 10% of each other.

Serial Peripheral Interface (SPI) Bus:

Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between
microcontrollers and small peripherals such as shift registers, sensors, and SD cards. It uses separate
clock and data lines, along with a select line to choose the device you wish to talk to.

SPI works in a slightly different manner. It's a "synchronous" data bus, which means that it uses
separate lines for data and a "clock" that keeps both sides in perfect sync. The clock is an oscillating
signal that tells the receiver exactly when to sample the bits on the data line.

SPI Transfer Modes: SPI interface allows transmitting and receiving data simultaneously on two
lines (MOSI and MISO). Clock polarity (CPOL) and clock phase (CPHA) are the main parameters that
define a clock format to be used by the SPI bus.
SPI Interface:

The SPI bus specifies four logic signals:

 SCLK: Serial Clock (output from master)

 MOSI: Master Output Slave Input, or Master Out Slave In (data output from master)
 MISO: Master Input Slave Output, or Master In Slave Out (data output from slave)
 SS: Slave Select (often active low, output from master)

RS232 (Recommended Standard):

The RS-232(X) is a serial communication protocol, commonly used for transferring and receiving
the serial data between two devices. It supports both synchronous and asynchronous data
transmissions.

Many devices in the industrial environment are still using RS-232 communication cable. Rs-232
cable is used to identify the difference of two signal levels between logic 1 and logic 0. The logic 1 is
represented by the -12V and logic 0 is represented the +12V. The RS-232 cable works at different baud
rates like 9600 bits/s, 2400bits/s, 4800bits/s etc. The RS-232 cable has two terminal devices namely Data
Terminal Equipment and Data communication Equipment. Both devices will send and receives the
signals. The data terminal equipment is a computer terminal and data communication Equipment is
modems, or controllers etc.
 Now a day’s most of the personal computers have two serial ports and one parallel port (RS232).
These two types of ports are used for communicating with external devices and they work in different
ways. The parallel port sends and receives the 8-bit data at a time over eight separate wires and this
transfers the data very quickly, the parallel ports are typically used to connect a printer to a PC.

A serial port sends and receives one-bit data at a time over one wire and it transfers data very
slowly. The RS-232 stands for recommended slandered and 232 is a number X indicates the latest
version like RS-232c, RS232s.

RS-232 Hand Shaking Signals:

The most commonly used type of serial cable connectors are 9-pin connectors DB9 and 25-pin
connector DB-25. Each of them may be a male or female type. Nowadays most of the computers use the
DB9 connector for asynchronous data exchange. The maximum length of RS-232 cable is 50ft.

RS232 Pin Description:

It is a 25-pin connector, each pin has its own function is as follows.

PIN 1: (Protective Ground); It is a ground Pin.

PIN 2: Transmit Data.

PIN 3: Receive Data.

PIN 2 & PIN 3: These pins are most important pins for data transmitting and receiving. The 1 & 2-pins
are used to data transmission and pin-3 used to data receiving purpose.

PIN 4: Request to send.

Pin 5: Clear to send.

PIN 6: Data Set Ready.

PIN 20: Data terminal Ready.

PIN 4, PIN 5, PIN 6, PIN 20: These pins are the handshaking pins(flow of control). Normally terminals
cannot transmit the data until clear to send transmission is received from the DCE.

PIN 7: This pin is the common reference for all signals, including data, timing, and control signals. The
DCE and DTE work properly across the serial interface and the pin-7 must be connected both ends
without interface would not work.

PIN 8: This pin is also known as received line signal detect or carrier detect. This signal is activated when
a suitable carrier is established between the local and remote DCE devices.

PIN9: This pin is a DTE serial connector; this signal follows the incoming ring to an extent. Normally this
signal is used by DCE auto answer mode.

PIN 10: Test Pin.

PIN 11: standby select.

PIN 12: Data Carrier Detect.

PIN 13: Clear to send.

PIN 14: Transmit data.

PIN 15: Transmit clock.

PIN 17: Receive clock.

PIN 24: External Clock.

PIN 15, 17, 24; Synchronous modems use the signals on these pins. These pins are controlled bit timing.

PIN 16: Receive data.

PIN 18: Test Pin.

PIN 19: Request to send.

PIN 21: (Signal Quality Detector); This pin Indicates the quality of the received carrier signal because the
transmitting modem must be sent 0 or either 1 at each bit time, the modem controls the timing of the
bits from the DTE.

PIN 22: (Ring Indicator): The ringing indicator means the DCE informs the DTE that the phone is ringing.
All the modems designed for directly connected to the phone network equipped with auto answer.
PIN 23: Data Signal Rate Detector

PIN 25: Test Mode

I2C BUS (Inter-integrated Circuit):

I²C (Inter-Integrated Circuit), pronounced I-squared-C, is a synchronous, multi-master, multi-
slave, packet switched, single-ended, serial computer bus invented in 1982 by Philips
Semiconductor (now NXP Semiconductors). It is widely used for attaching lower-speed peripheral ICs to
processors and microcontrollers in short-distance, intra-board communication.

The aforementioned reference design is a bus with a clock (SCL) and data (SDA) lines with 7-bit
addressing. The bus has two roles for nodes: master and slave:

 Master node – node that generates the clock and initiates communication with slaves.

 Slave node – node that receives the clock and responds when addressed by the master.

The bus is a multi-master bus, which means that any number of master nodes can be present.
Additionally, master and slave roles may be changed between messages (after a STOP is sent).

There may be four potential modes of operation for a given bus device, although most devices only use
a single role and its two modes:

 master – master node is sending data to a slave,

 master receive – master node is receiving data from a slave,

 slave transmit – slave node is sending data to the master,

 slave receive – slave node is receiving data from the master.

Applications:

Common applications of the I²C bus are:

 Accessing real-time clocks and NVRAM chips that keep user settings.

 Accessing low-speed DACs and ADCs.

  Changing contrast, hue, and color balance settings in monitors (via Display Data Channel).

 Changing sound volume in intelligent speakers.

 Controlling small (e.g. feature phone) OLED or LCD displays.

 Reading hardware monitors and diagnostic sensors, e.g. a fan's speed.

 Turning on and turning off the power supply of system components.

USB (Universal Serial Bus):

Universal Serial Bus (USB) is an industry standard that establishes specifications for cables and
connectors and protocols for connection, communication and power supply between computers,
peripheral devices and other computers. There have been four generations of USB specifications: USB
1.x, USB 2.0, USB 3.x and USB4. It is available in different types, which are shown below.

SUMMARY OF USB VERSIONS AND PERFORMANCE:

USB VERSION DETAILS

USB 1 Lowspeed:1.5Mbps
Full speed: 12 Mbps

USB 2 'High Speed' rate of 480 Mbps

USB 3 Raw data transfer rates of 4.8 Gbit/s

USB advantages & disadvantages:

Advantages Disadvantages

 Ease of use  Data transfer not as fast as some other

systems
 Acceptable data rate for many applications
 Limited capability & overall performance
 Robust connector system

 Variety of connector types / sizes available

 Low cost
ADC and DAC Specifications:
Slew Rate: Rate of change of output w.r.t input change. Generally, in specifications of IC, it is quoted as
minimum and maximum slew rate.

Resolution: The resolution refers to the finest minimum change in the signal which is accepted for
conversion, and it is decided with respect to number of bits. It is given as 1/2n, where ‘n’ is the number
of bits in the digital output word.

Quantization error: If the binary output bit combination is such that for all the values of input voltage
Vi between any two voltage levels, there is a unavoidable uncertainty about the exact value of Vi when
the output is a particular binary combination. This uncertainty is termed as quantization error.

Linearity Error: It is defined as the measure of variation in voltage step size. It indicates the difference
between the transitions for a minimum step of input voltage change.
Analog error: An error occurring due to the variations in DC switching point of the comparator, resistors,
reference voltage source, ripples and noises introduced by the circuit components is termed as Analog
error.

Logical Separation Of Program And Data Memory:

PROGRAM MEMORY (ROM) is used for permanent saving program being executed, while DATA
MEMORY (RAM) is used for temporarily storing and keeping intermediate results and variables.

Masking Operation Using Logical Instructions:

Logic instructions are commonly used to set (turn on) or clear (reset, turn off) individual bits within a
word without affecting other bits.

By ANDing a value with a deliberately designed constant, called a bit mask we can clear specific
bits. Any bits that are 0 in the mask will be cleared in the result, and bits that are 1 in the mask with be
preserved in the result.

value 10010100
mask 00001111
----------------
00000100
Likewise, we can use an OR operation to set bits. A 1 in the mask causes the bit to be set, and
a 0 causes it be be preserved.
value 10010100
mask 00001111
----------------
10011111
An XOR can be used to invert (toggle) specific bits. A 1 in the mask causes a bit to be inverted,
while a 0 causes it be preserved:

value 10010100
mask 00001111
----------------
10011011
Size of Stack pointer and Program counter in 8051:

The stack pointer in the 8051 is 8-bits wide, and it can take a value of 00 to FFH. When the 8051 is
initialized, the SP register contains the value 07H. This means that the RAM location 08 is the first
location used for the stack.

The program counter in the 8051 is 16 bits wide. This means that the 8051 can access program
addresses 0000 to FFFFH, a total of 64K bytes of code.

Which register bank conflicts with stack and why:

There is .a problem with the default setting of the stack. Since SP = 07 when the 8051 is
powered up, the first location of the stack is RAM location 08, which also belongs to register RO of
register bank 1. In other words, register bank 1 and the stack are using the same memory space.

Monotonocity:

Monotonicity is a property of certain types of digital-to-analog converter ( DAC ) circuits. In a

monotonic DAC, the analog output always increases or remains constant as the digital input increases.

Banked registers in ARM:

ARM processors have 37 registers. The registers are arranged in partially overlapping banks.
There is a different register bank for each processor mode. The banked registers give rapid context
switching for dealing with processor exceptions and privileged operations.

Software Interrupt in ARM: A software interrupt instruction (SWI) causes a software interrupt
exception, which provides a mechanism for applications to call operating system routines.

When the processor executes an SWI instruction, it sets the program counter pc to the offset
0×8 in the vector table. The instruction also forces the processor mode to SVC, which allows an
operating system routine to be called in a privileged mode.

Each SWI instruction has an associated SWI number, which is used to represent a particular
function call or feature.

Pipeline Mechanism In Arm Processor:

The organization of an ARM Processor with three stage pipeline consists of the following: Register bank:
This includes various registers as seen in the programmer’s model of ARM.
Barrel Shifter: We have also seen this barrel shifter that is used to do various operations as discussed
earlier in this chapter.
The ALU: This unit performs the various arithmetic and logical operations
Address register and increment: The register stores the address and the incrementer increments the
same so as to point to the next instruction. 5. Data register: It is used as a buffer to store the data when
written to the memory or read from the memory.
Instruction Decoder: As the name says, it decodes the instruction and issues the control signals
accordingly. Hence, the Instruction decoder is associated with the control logic that issues the control
signals. Fig shows the implementation of the three stage pipelining in ARM. In the figure, the flow of the
instruction shows the three stages of pipelining. The instruction is first fetched by the PC (at the top)
giving address to the address register and is incremented using the incrementer, so that the PC points to
the next instruction. The instruction is fetched through the data bus (at the bottom) and is given to the
Instruction Decode and Control unit. This unit decodes the instruction, which is the second stage of the
pipeline and then the instruction is executed by the ALU, multiplier and barrel shifter using the registers
from the register bank.

Modes Of Operation Of Arm Processor:

There are seven processor modes:

Mode Bits Description Family

User usr %10000 Normal program execution, no privileges All

FIQ fiq %10001 Fast interrupt handling All

IRQ irq %10010 Normal interrupt handling All

Supervisor svc %10011 Privileged mode for the operating system All
 Abort abt %10111 For virtual memory and memory protection ARMv3+

Undefined und %11011 Facilitates emulation of co-processors in hardware ARMv3+

System sys %11111 Runs programs with some privileges ARMv4+

User mode:

This is the mode in which user application tasks should run. It has access to the base register set, and no
privileges.
FIQ mode:

The ARM processor supports two types of interrupt handling. There is the regular type of interrupt, and
there is this, the fast interrupt. The difference is that fast interrupts can interrupt regular ones.

In comparison with the 6502 or the x86, an FIQ is similar to an NMI; the difference being that the ARM
has no NMI (FIQs can be disabled). It is, however, the same concept of a two-level interrupt system
where a more important interrupt can interrupt an interrupt!

FIQ mode provides a large number of shadow registers (R8 to R14, CPSR) and is useful for things that
must complete extremely quickly or else data loss is a possibility. The original (8MHz) ARM used FIQ for
networking and floppy disc which had to be serviced as soon as data was available. Modern ARMs would
probably use FIQ for high speed DMA-style transfers.
IRQ mode:

This is the other, regular, interrupt mode. Only R13, R14, and CPSR are shadowed. All interrupts that
don't require extreme speed (clock ticks, screen VSync, keyboard, etc...) will use IRQ mode.
SVC mode:

This is the privileged mode reserved for the operating system. R13, R14, and CPSR are shadowed.

OS calls (SWI) set the processor to SVC mode, and then the processor jumps to &8 (or &FFFF0008).

After system reset, the ARM begins processing at address &0 (or &FFFF0000 if high vectors configured),
with interrupts disabled and in SVC mode. This address is the location of the Reset Vector, which should
be a branch to the reset code.
Abort mode:

An abort is signalled by the memory system as a result of a failure to load either an instruction (Prefetch
Abort) or data (Data abort).

A Prefetch Abort occurs if the processor attempts to execute a failed instruction load (note - no abort
happens if the processor fails to load an instruction, but said instruction is not executed due to a branch
or suchlike).
In ARMv5 a Prefetch Abort can be generated programatically by the use of the breakpoint instruction.

A Data Abort occurs if the processor attempts to fetch data but the memory system says it is unable to.
The abort occurs before the failed instruction alters the processor state.
Undefined mode:

When an undefined instruction is encountered, the ARM will wait for a coprocessor to acknowledge that
it can deal with the instruction (if in co-processor instruction space). If no coprocessor responds, or the
instruction is one that is not defined, then the undefined instruction vector is taken. This will branch to
&4 (or &FFFF0004) to allow such things as software emulation of coprocessors, or other extensions to
the instruction set.
System mode:

A problem with the original design of the ARM is that as processor vectors modify R14 with the return
address, an exception handler (for example, IRQ) that calls subroutines cannot act in a re-entrant way;
for if the IRQ handler is taken while in the IRQ handler and having called a subroutine to handle the
(first) IRQ, the return address in R14 will be trashed by the second IRQ exception.