Lab 5 Counter 2324s2
Lab 5 Counter 2324s2
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1. Introduction 。 C、
2
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In this lab, we are going to design a synchronous counter. The designed circuit will be simulated using the
OrCAD capture and PSpice.
|
2. Synchronous Counter
0
⽇占 、
0 →
4
Using JK flip-flops (7473) and some external gates, design a synchronous counter that loops the sequence:
22 i
4 2
1
⼼
…→4→7→6→0→3→1→4→…
⼀ ( o) l i 1) 00) 01105 、 1 "
Submission:
Submit to SOUL a single PDF file which contains:
(i) The answers for Section 2(a), 2(b) and 2(c).
− All answers must be HAND-WRITTEN. Handwriting using tablets, poor writing, or typing are
NOT accepted.
(ii) Print-screens of the schematic and simulation screen.
(iii) A brief description of the design and simulation.
Note:
− Name the PDF file as DLS_Lab5_<yourname>_<studentID>.pdf
◆ e.g., DLS_Lab5_CHANTaiMan_20002000.pdf
− Late Submission will NOT be accepted.
This is an individual work. You must finish this work alone.
1 / 1
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