Lab Report 07

Submitted To:

Engr. Shahid Ali Bhutta

Submitted By:

Qamar Sultan

22-CP-63

DSD Lab

Computer Engineering Department

University of Engineering & Technology, Taxila

Task 01:
Design a full adder. Use Push Buttons to Input A, B, and Cin. Use LEDs to output S and Cout on the
Nexsys4 Artix 7 board.

Module Code:
module full_adder(
input A,
input B,
input Cin,
output S,
output Cout );
assign S = A ^ B ^ Cin;
assign Cout = (A & B) | (Cin & (A ^ B));
endmodule

Test Bench:
module test_bench();
reg A, B, Cin;
wire S, Cout;
full_adder FA(
.A(A),
.B(B),
.Cin(Cin),
.S(S),
.Cout(Cout) );
initial begin
$dumpfile("test_bench.vcd");
$dumpvars(0, test_bench);
A = 0; B = 0; Cin = 0;
#10 A = 0; B = 1; Cin = 0;
#10 A = 1; B = 1; Cin = 0;
#10 A = 1; B = 1; Cin = 1;
#10; $finish;
end
endmodule

IO File:
set_property IOSTANDARD LVCMOS33 [get_ports A]

set_property IOSTANDARD LVCMOS33 [get_ports B]

set_property IOSTANDARD LVCMOS33 [get_ports Cin]

set_property IOSTANDARD LVCMOS33 [get_ports Cout]

set_property IOSTANDARD LVCMOS33 [get_ports S]

set_property PACKAGE_PIN T16 [get_ports A]

set_property PACKAGE_PIN E16 [get_ports B]

set_property PACKAGE_PIN R10 [get_ports Cin]

set_property PACKAGE_PIN T8 [get_ports Cout]

set_property PACKAGE_PIN V9 [get_ports S]

Simulation:

RTL Analysis:

Task 02:
Design a Verilog Module that outputs high at each sixth high input. Use the push button for input and LED
as output, on the DIGILENT NEXSYS 4 board.

Module Code:
module SHI_70(
input x, reset, clk,
output reg y );
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5, S6 = 6;
reg [2:0] state, next;
//Clock & Reset Logic
always @ ( posedge clk or negedge reset)
if (!reset) state <= S0;
else state <= next;
//Mechine Logic
always @ (state or x)
begin
case (state)
S0: if (x) next = S1;
else next = S0;
S1: if (x) next = S2;
else next = S0;
S2: if (x) next = S3;
else next = S0;
S3: if (x) next = S4;
else next = S0;
S4: if (x) next = S5;
else next = S0;
S5: if (x) next = S6;
else next = S0;
S6: if (x) next = S6;
else next = S0;
endcase
end
//Output
always @ (state)
begin
y = 0;
if (state == S6) y = 1;
else y = 0;
end
endmodule

Test Bench:
module SHI_70_TB;
reg x, reset, clk;
wire y;
SHI_70 dut (
.x(x),
.reset(reset),
.clk(clk),
.y(y) );
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
reset = 0;
#20 reset = 1;
end
initial begin
// Test Case 1: Reset
reset = 1;
x = 0;
#10 reset = 0;
#5;
// Test Case 2: x=0
x = 0;
#10;
// Test Case 3: x=1
 x = 1;
#10;
// Test Case 4: Alternating x
repeat (5) begin
x = 0;
#5;
x = 1;
#5;
end
// Test Case 6: x=1, long duration
x = 1;
#200;
// Test Case 5: x=0, long duration
x = 0;
#200;
$finish;
end
endmodule

IO File:
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports x]
set_property IOSTANDARD LVCMOS33 [get_ports y]
set_property PACKAGE_PIN T16 [get_ports x]
set_property PACKAGE_PIN T8 [get_ports y]
set_property PACKAGE_PIN U9 [get_ports clk]
set_property PACKAGE_PIN U8 [get_ports reset]

Simulations:
RTL Analysis:

Task 03:
Design an 8-bit counter that counts after each second. The counter resets immediately on reset input. Display
the binary count using LEDs on the FPGA board.

Module Code:
module counter(
input clk,
input reset,
input increment,
input decrement,
output reg [7:0] count
);
reg enable;
reg [7:0] mux_out;
wire incr_out;
wire decr_out;
debounce incr_db(
.clk (clk),
.reset (reset),
.in (increment),
.out (incr_out)
);
debounce decr_db(
.clk (clk),
.reset (reset),
.in (decrement),
.out (decr_out)
);
always@(*)
enable = incr_out | decr_out;
always@(*)
begin
case(incr_out)
1'b0: mux_out = count-1;
1'b1: mux_out = count+1;
endcase
end
always@(posedge clk)
if(reset)
count <= #1 0;
else if(enable)
count <= #1 mux_out;
endmodule

Test Bench:
module tb_counter;
reg clk;
reg reset;
reg increment;
reg decrement;
wire [7:0] count;
counter uut (
.clk(clk),
.reset(reset),
.increment(increment),
.decrement(decrement),
.count(count) );
initial
begin
clk = 0;
forever #5 clk = ~clk;
end
initial
begin
reset = 0;
increment = 0;
decrement = 0;
@(posedge clk);
#1 reset = 1;
@(posedge clk);
 #1 reset = 0;
@(posedge clk);
#1 increment = 1;
repeat(2) @(posedge clk);
#1 increment = 0;
decrement = 1;
@(posedge clk);
#1 decrement = 0;
repeat(20) @(posedge clk);
$stop;
end
endmodule

IO File:
set_property IOSTANDARD LVCMOS33 [get_ports {count[7]}]

set_property IOSTANDARD LVCMOS33 [get_ports {count[6]}]

set_property IOSTANDARD LVCMOS33 [get_ports {count[5]}]

set_property IOSTANDARD LVCMOS33 [get_ports {count[4]}]

set_property IOSTANDARD LVCMOS33 [get_ports {count[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {count[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {count[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {count[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports clk]

set_property IOSTANDARD LVCMOS33 [get_ports decrement]

set_property IOSTANDARD LVCMOS33 [get_ports increment]

set_property IOSTANDARD LVCMOS33 [get_ports reset]

set_property PACKAGE_PIN T16 [get_ports decrement]

set_property PACKAGE_PIN R10 [get_ports increment]

set_property PACKAGE_PIN E16 [get_ports reset]

set_property PACKAGE_PIN T8 [get_ports {count[0]}]

set_property PACKAGE_PIN V9 [get_ports {count[1]}]

set_property PACKAGE_PIN R8 [get_ports {count[2]}]

set_property PACKAGE_PIN T6 [get_ports {count[3]}]

set_property PACKAGE_PIN T4 [get_ports {count[5]}]

set_property PACKAGE_PIN T5 [get_ports {count[4]}]

set_property PACKAGE_PIN U7 [get_ports {count[6]}]

set_property PACKAGE_PIN U6 [get_ports {count[7]}]

Net "clk" TNM_NET = sys_clk_pin;

TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;

Simulation:

RTL Analysis: