[AK4499EX]

AK4499EX
Premium Switched Resistor Stereo DAC
1. General Description
The AK4499EX is a new concept Premium multi-bit Stereo DAC with newly developed Switched Resistor
technology, achieving the industry’s leading level low distortion and low noise characteristics. It is suitable
for playback of high-resolution audio sources that are becoming widespread in Network Audio and USB-
DACs Audio systems. Multi-bit Modulator input for a high-precision audio source playback.

Application: AV Receivers, CD/SACD player, Network Audios, USB DACs, USB Headphones,
Measurement Equipment, Control Systems, Public Audios (PA)

2. Features
• Stereo Switched Resistor DAC
• THD+N: -124 dB
• Dynamic Range, S/N: 138 dB (135 dB @Stereo)
• Multi-bit Modulator Data Interface with 5.6448, 11.2896 MHz Clock
- 7-bit Modulator Data
• Mono Mode
• Power Supply:
TVDD = DVDD to 3.6 V, DVDD = 1.7 to 1.98 V,
AVDD = 4.75 to 5.25 V, VDDL/R = 4.75 to 5.25 V
• Digital Input Level: CMOS
• Package: 64-pin HTQFP
• Temperature: -40 to 85 C

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3. Table of Contents

1. General Description ............................................................................................................................ 1

2. Features .............................................................................................................................................. 1
3. Table of Contents ................................................................................................................................ 2
4. Block Diagram and Functions ............................................................................................................. 3
4.1. Block Diagram ................................................................................................................................. 3
4.2. Functions ......................................................................................................................................... 3
5. Pin Configurations and Functions ....................................................................................................... 4
5.1. Pin Configurations ........................................................................................................................... 4
5.2. Pin Functions ................................................................................................................................... 5
5.3. Handling of Unused Pin ................................................................................................................... 8
5.4. Pull-up, Pull-down Pin List ............................................................................................................... 8
6. Absolute Maximum Ratings ................................................................................................................ 9
7. Recommended Operating Conditions............................................................................................... 10
8. Electrical Characteristics ....................................................................................................................11
8.1. Analog Characteristics ....................................................................................................................11
8.2. DC Characteristics ......................................................................................................................... 15
8.3. Switching Characteristics .............................................................................................................. 16
8.4. Timing Diagram.............................................................................................................................. 18
9. Functional Descriptions ..................................................................................................................... 21
9.1. Sampling Speed mode Setting ...................................................................................................... 22
9.2. System Clock ................................................................................................................................. 23
9.3. Audio Inerface Format ................................................................................................................... 24
9.4. Multi-Bit Interface Mode Select, Output Signal Select .................................................................. 26
9.5. Phase Inversion Function (Register Control Mode) ...................................................................... 27
9.6. Sound Control ................................................................................................................................ 28
9.7. Power Up Sequence of External Operational Amplifier for I-V Conversion .................................. 29
9.8. Power Up/Down Function .............................................................................................................. 30
9.9. Internal State ................................................................................................................................. 33
9.10. Register Control Interface............................................................................................................ 37
9.11. Register Map................................................................................................................................ 41
9.12. Register Definitions ..................................................................................................................... 42
10. Recommended External Circuits................................................................................................... 45
10.1. External Connection Example ..................................................................................................... 45
10.2. Grounding and Power Supply Decoupling .................................................................................. 46
10.3. Reference Voltage ....................................................................................................................... 46
10.4. Analog Output .............................................................................................................................. 47
10.5. External Mute Circuit ................................................................................................................... 50
11. Package ......................................................................................................................................... 51
11.1. Outline Dimensions ...................................................................................................................... 51
11.2. Material & Terminal Finish ........................................................................................................... 52
11.3. Marking ........................................................................................................................................ 52
12. Ordering Guide .............................................................................................................................. 53
13. Revision History............................................................................................................................. 53
IMPORTANT NOTICE .......................................................................................................................... 54

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4. Block Diagram and Functions

4.1. Block Diagram

TVDD DVDD DVSS AVDD AVSS

PDN VSSL
VDDL
VCOML
EXTCLN
IOUTLN
OPINLN
SR
MBD1 DAC

MBD2
OPINLP
IOUTLP
MBD3  EXTCLP
Modulator
MBD4 Audio
Interface DWA
MBD5 EXTCRP
IOUTRP
MBD6 OPINRP

MBD7
SR
DAC
BCK
OPINRN
IOUTRN
EXTCRP
VCOMR
VDDR
VSSR
TSTO MCLK VREFHL
Clock
OSR/CSN Control Stop VREFLL
Divider
Register Detection VREFHR
LRSEL0/CCLK/SCL
VREFLR
LRSEL1/CDTI/SDA
DEV1
MUTEN DEV2
SC/CAD0 DSEL2/CAD1 PSN VTSEL/I2C MCLK

Figure 1. Block Diagram

4.2. Functions

Block Functions
Audio Interface BCK is used to clock MBD7-1 data into the shift register.
DWA Processing two’s complement MBD7-1 data by Data Weighted Average.
Converting MBD7-1 data from DWA output to analog signal and that is
SR DAC
designed by Switched Resistor DAC.
Internal registers keep its settings for each mode. Control registers are
Control Register accessed in 3-wire (CSN, CCLK, CDTI) or I2C-Bus (SCL, SDA) control
mode.
Clock Divider Generates the clock for SR DAC from the input clock of the MCLK pin.
MCLK Stop Detection Detects when the master clock input is absent.

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5. Pin Configurations and Functions

5.1. Pin Configurations

EXTCRN
EXTCRP
EXTCLN

EXTCLP

OPINRN
OPINRP

IOUTRN
IOUTRP
OPINLN

VCOMR
OPINLP
IOUTLN

IOUTLP
VCOML
DEV2

DEV1
48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33
VDDL 49 32 VDDR
VDDL 50 VDDL VDDR 31 VDDR
VDDL 51 30 VDDR
VSSL 52 29 VSSR
VSSL 53 AK4499EX 28 VSSR
VSSL 54 27 VSSR
VREFLL 55 64-pin HTQFP 26 VREFLR
VREFLL 56 ( Top View ) 25 VREFLR
VREFLL 57 24 VREFLR
VREFHL 58 23 VREFHR
VREFHL 59 22 VREFHR
VREFHL 60 21 VREFHR
AVDD 61 20 VTSEL/I2C
AVSS 62 AVDD Back TAB ： No t e 19 PSN
MCLK 63 TVDD 18 DSEL2/CAD1
DVDD 64 17 SC/CAD0
10

11

12

13

14

15

16
1
2
3
4
5
6
7
8
9

TSTO

LRSEL1/CDTI/SDA
TVDD

MUTEN
PDN

OSR/CSN
MBD1
MBD2
MBD3
MBD4
MBD5
MBD6
MBD7

LRSEL0/CCLK/SCL
DVSS

BCK

Input
Output
I/O
Power

Note. The exposed pad on the bottom surface of the package must be connected to ground.

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5.2. Pin Functions

Protection Power Down

No. Pin Name I/O Function State
Diode
1 DVSS - - Digital Ground Pin. -
2 TVDD - Digital Power Supply Pin, DVDD to 3.6 V. -
Power Up, Power Down Pin.
When at “L”, the AK4499EX is in power down state Hi-Z
3 PDN I TVDD/DVSS
and is held in reset. The AK4499EX must always (PDN = “L”)
be reset upon power up.
4 BCK I TVDD/DVSS Multi-Bit Data Clock Pin. Hi-Z
5 MBD1 I TVDD/DVSS Multi-Bit Data1 Input Pin. Hi-Z
6 MBD2 I TVDD/DVSS Multi-Bit Data2 Input Pin. Hi-Z
7 MBD3 I TVDD/DVSS Multi-Bit Data3 Input Pin. Hi-Z
8 MBD4 I TVDD/DVSS Multi-Bit Data4 Input Pin. Hi-Z
9 MBD5 I TVDD/DVSS Multi-Bit Data5 Input Pin. Hi-Z
10 MBD6 I TVDD/DVSS Multi-Bit Data6 Input Pin. Hi-Z
11 MBD7 I TVDD/DVSS Multi-Bit Data7 Input Pin. Hi-Z
12 TSTO O TVDD/DVSS Test Output Pin. Hi-Z
PSN pin = “H”: Sampling Speed Mode Setting Pin
in Pin Control mode.
OSR I
“L”: OSR256 mode
13 TVDD/DVSS Hi-Z
“H”: OSR128 mode
PSN pin = “L”, I2C pin = “L”: Chip Select Pin in
CSN I
Register Control mode.
PSN pin = “H”: Audio Interface Format Select and
LRSEL0 I
Data Select Pin in Pin Control mode.
PSN pin = “L”, I2C pin = “L”: Control Data Clock
14 CCLK I TVDD/DVSS Hi-Z
Pin in Register Control mode.
PSN pin = “L”, I2C pin = “H”: Control Data Clock
SCL I
Input Pin
PSN pin = “H”: Audio Interface Format Select and
LRSEL1 I
Data Select Pin in Pin Control mode.
PSN pin = “L”, I2C pin = “L”: Control Data Input
15 CDTI I TVDD/DVSS Hi-Z
Pin in Register Control mode.
PSN pin = “L”, I2C pin = “H”: Control Data Input
SDA I/O
Pin.
Mute State Select Pin.
16 MUTEN I TVDD/DVSS “L”: Mute Hi-Z
“H”: Normal Operation
PSN pin = “H”: Sound Control in Pin Control
mode.
SC I
“L”: Measurement mode
17 TVDD/DVSS Hi-Z
“H”: Sound quality mode
PSN pin = “L”: Chip Address 0 Pin in Register
CAD0 I
Control mode.
PSN pin = “H”: Test Input Pin. Connect to TVDD
DSEL2 I
in Pin Control mode.
18 TVDD/DVSS Hi-Z
PSN pin = “L”: Chip Address 1 Pin in Register
CAD1 I
Control mode.
Pin control mode or Register Control mode Pull-Up to
Select Pin. (Internal pull-up pin) TVDD
19 PSN I TVDD/DVSS
“L”: Register control mode (100 kΩ,
“H”: Pin Control mode typ.)

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PSN pin = “H”: Digital input voltage level of MCLK

select pin in Pin Control Mode.
VTSEL I
“L”: High Level = 1.36 V, Low Level = 0.34 V
20 TVDD/DVSS Hi-Z
“H”: High Level = 2.2 V, Low Level = 0.8 V
PSN pin = “L”: Register Control Interface Select
I2C I
Pin in Register Control mode.
21 VREFHR I VDDR/VSSR Hi-Z
22 VREFHR I VDDR/VSSR Rch High Level Voltage Reference Input Pin. Hi-Z
23 VREFHR I VDDR/VSSR Hi-Z
24 VREFLR I VDDR/VSSR Hi-Z
25 VREFLR I VDDR/VSSR Rch Low Level Voltage Reference Input Pin. Hi-Z
26 VREFLR I VDDR/VSSR Hi-Z
27 VSSR - - Analog Ground Pin. -
28 VSSR - - Analog Ground Pin. -
29 VSSR - - Analog Ground Pin. -
30 VDDR - - Rch Analog Power Supply 5.0 V(typ.) Pin. -
31 VDDR - - Rch Analog Power Supply 5.0 V(typ.) Pin. -
32 VDDR - - Rch Analog Power Supply 5.0 V(typ.) Pin. -
Rch VCOM pin. VCOMR is connected to the
33 VCOMR I VDDR/VSSR midpoint of resistors between VREFHR and Hi-Z
VREFLR.
Bidirectional
Input Pin. Connect to Analog Ground. There is a
34 DEV1 I VDDR/VSSR diode to
Bidirectional Diode between DEV1 and VSSR. VSSR
External Capacitor Connect Pin. This Pin should Pull-Down to
35 EXTCRN O VDDR/VSSR be connected to 1 μF to VSSR. VSSR
(Internal pull-down pin) (250 kΩ, typ.)
Connected to
36 IOUTRN O VDDR/VSSR Current Output Pin. (Rch Negative Signal) OPINRN
(30 Ω, typ.)
Rch Negative Analog Signal Output pin. Connect Connected to
37 OPINRN O VDDR/VSSR to negative input pin of External OPAMP for I-V IOUTRN
Conversion. (30 Ω, typ.)

Rch Positive Analog Signal Output pin. Connect to Connected to

38 OPINRP O VDDR/VSSR negative input pin of External OPAMP for I-V IOUTRP
Conversion. (30 Ω, typ.)
Connected to
39 IOUTRP O VDDR/VSSR Current Output Pin. (Rch Positive Signal) OPINRP
(30 Ω, typ.)
External Capacitor Connect Pin. This Pin should Pull-Down to
40 EXTCRP O VDDR/VSSR be connected to 1 μF to VSSR. VSSR
(Internal pull-down pin) (250 kΩ, typ.)

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External Capacitor Connect Pin. This Pin should Pull-Down to

41 EXTCLP O VDDL/VSSL be connected to 1 μF to VSSL. VSSL
(Internal pull-down pin) (250 kΩ, typ.)
Connected to
42 IOUTLP O VDDL/VSSL Current Output Pin. (Lch Positive Signal) OPINLP
(30 Ω, typ.)
Lch Positive Analog Signal Output pin. Connect Connected to
43 OPINLP O VDDL/VSSL to negative input pin of External OPAMP for I-V IOUTLP
Conversion. (30 Ω, typ.)

Lch Negative Analog Signal Output pin. Connect Connected to

44 OPINLN O VDDL/VSSL to negative input pin of External OPAMP for I-V IOUTLN
Conversion. (30 Ω, typ.)
Connected to
45 IOUTLN O VDDL/VSSL Current Output Pin. (Lch Negative Signal) OPINLN
(30 Ω, typ.)
External Capacitor Connect Pin. This Pin should Pull-Down to
46 EXTCLN O VDDL/VSSL be connected to 1 μF to VSSL. VSSL
(Internal pull-down pin) (250 kΩ, typ.)
Bidirectional
Input Pin. Connect to Analog Ground. There is a
47 DEV2 I VDDL/VSSL diode to
Bidirectional Diode between DEV2 and VSSL. VSSL
Lch VCOM pin. VCOML is connected to the
48 VCOML I VDDL/VSSL midpoint of resistors between VREFHL and Hi-Z
VREFLL.
49 VDDL - - Lch Analog Power Supply 5.0 V(typ.) Pin. -
50 VDDL - - Lch Analog Power Supply 5.0 V(typ.) Pin. -
51 VDDL - - Lch Analog Power Supply 5.0 V(typ.) Pin. -
52 VSSL - - Analog Ground Pin. -
53 VSSL - - Analog Ground Pin. -
54 VSSL - - Analog Ground Pin. -
55 VREFLL I VDDL/VSSL Hi-Z
56 VREFLL I VDDL/VSSL Lch Low Level Voltage Reference Input Pin. Hi-Z
57 VREFLL I VDDL/VSSL Hi-Z
58 VREFHL I VDDL/VSSL Hi-Z
59 VREFHL I VDDL/VSSL Lch High Level Voltage Reference Input Pin. Hi-Z
60 VREFHL I VDDL/VSSL Hi-Z
61 AVDD - - Analog Power Supply 5.0 V(typ.) Pin. -
62 AVSS - - Analog Ground Pin. -
63 MCLK I AVDD/AVSS Master Clock Input Pin. Hi-Z
64 DVDD - - 1.8 V(typ.) Power Supply Pin. -
The TAB on the bottom surface of the package
- TAB - - -
should be connected to Ground.
Note 1. All input pins except internal pull-up pins must not be left floating.
Note 2. The AK4499EX must be powered down by the PDN pin when changing Pin Control mode or
Register Control mode by the PSN pin.

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5.3. Handling of Unused Pin

Unused I/O pins must be connected appropriately.

Pin Control mode

Classification Pin Name Setting
IOUTLP, IOUTLN, OPINLP, OPINLN
Analog Open
IOUTRP, IOUTRN, OPINRP, OPINRN
Digital TSTO Open

Register Control mode (3-wire Serial Control Mode)

Classification Pin Name Setting
IOUTLP, IOUTLN, OPINLP, OPINLN
Analog Open
IOUTRP, IOUTRN, OPINRP, OPINRN
Digital TSTO Open

Register Control mode (I2C-Bus Control Mode)

Classification Pin Name Setting
IOUTLP, IOUTLN, OPINLP, OPINLN
Analog Open
IOUTRP, IOUTRN, OPINRP, OPINRN
TSTO Open
Digital
CSN Connect to DVSS

5.4. Pull-up, Pull-down Pin List

Classification Pin name Internal connection

Pull-up pin (Typ. = 100 kΩ) PSN TVDD
EXTCLP, EXTCLN, VSSL
Pull-down pin (Typ. = 250 kΩ)
EXTCRP,EXTCRN VSSR

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6. Absolute Maximum Ratings

(AVSS = DVSS = VSSL = VSSR = 0 V; Note 3, Note 4)

Parameter Symbol Min. Max. Unit
Digital I/O TVDD -0.3 4.0 V
Digital Core DVDD -0.3 2.35 V
Power Supplies
Clock Interface AVDD -0.3 5.55 V
Analog VDDL/R -0.3 5.55 V
Power Supplies VSSL, VSSR, AVSS, DVSS ΔGND 0 0.3 V
Differences VDDL, VDDR, AVDD ΔVD 0 0.3 V
VREFHL -0.3 VDDL + 0.3 ≤ 5.55 V
High VREF
VREFHR -0.3 VDDR + 0.3 ≤ 5.55 V
Reference VREFLL -0.3 +0.3 V
Low VREF
Voltage VREFLR -0.3 +0.3 V
VCOML -0.3 VDDL + 0.3 ≤ 5.55 V
Common Voltage
VCOMR -0.3 VDDR + 0.3 ≤ 5.55 V
Input Current, Any Pin Except Power Supplies
IIN - ±10 mA
and Reference Voltage
Analog Output Voltage
VOUTA -0.3 VDDL/R + 0.3 ≤ 5.55 V
IOUTLP/LN/RP/RN, OPINLP/LN/RP/RN
Input Voltage
VDEV -0.3 +0.3 V
DEV1, DEV2
Digital Input Voltage VIND -0.3 TVDD + 0.3 ≤ 4.0 V
MCLK Input Voltage VINMCLK -0.3 AVDD + 0.3 ≤ 5.55 V
Ambient Temperature (Power applied) Ta -40 85 C
Storage Temperature Tstg -65 150 C
Note 3. All voltages with respect to ground.
Note 4. AVSS, DVSS, VSSL, VSSR and TAB must be connected to the ground.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed above the recommended operating voltage.

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7. Recommended Operating Conditions

(AVSS = DVSS = VSSL = VSSR = 0 V; Note 3, Note 4)

Parameter Symbol Min. Typ. Max. Unit
Digital I/O TVDD DVDD 1.8/3.3 3.6 V
Power Digital Core DVDD 1.7 1.8 1.98 V
Supplies Clock Interface AVDD 4.75 5.0 5.25 V
Analog VDDL/R 4.75 5.0 5.25 V
VREFHL VDDL - 0.5 - VDDL V
High VREF
VREFHR VDDR - 0.5 - VDDR V
Reference VREFLL - VSSL - V
Low VREF
Voltage VREFLR - VSSR - V
Common VCOML - (VREFHL + VREFLL)/2 - V
Voltage VCOMR - (VREFHR + VREFLR)/2 - V
Note 5. VDDL, VDDR and AVDD must be connected to the same voltage line.
Note 6. VDDL/R must be supplied at the same time as or before VREFHL/R.
Note 7. Regarding external circuit power up sequence refers to 9.7. Power Up Sequence of External
Operational Amplifier for I-V Conversion.

* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

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8. Electrical Characteristics

8.1. Analog Characteristics

OSR128 mode (OSR pin = “H” or OSR bit = “1”)

(Ta = 25 C; TVDD = 1.8 V, DVDD = 1.8 V, AVDD = 5.0 V, AVSS = DVSS = 0 V; VDDL/R = VREFHL/R =
5.0 V, VSSL/R = VREFLL/R = 0 V; VCOML/R = (VREFHL/R + VREFLL/R)/2; MCLK = 22.5792 MHz,
Sampling Frequency = BCK = 5.6448 MHz; Measurement bandwidth = 20 Hz to 20 kHz; Signal
Frequency = 1 kHz; Input Signal Level = 0.805 × Full-scale = 0 dBr (Note 8); External circuit Figure 31;
SC pin = “L” or SC bit = “0”
Parameter Min. Typ. Max. Unit
Dynamic Characteristics (Note 9)
BW = 20 kHz 0 dBr - -124 - dB
THD
BW = 40 kHz 0 dBr - -124 - dB
(Note 10)
BW = 80 kHz 0 dBr - -124 - dB
0 dBr - -124 - dB
BW = 20 kHz
-60 dBr - -72 - dB
0 dBr - -121 - dB
THD+N BW = 40 kHz
-60 dBr - -69 - dB
0 dBr - -118 - dB
BW = 80 kHz
-60 dBr - -66 - dB
Dynamic Range (-60 dBr; A-weighted) - 135 - dB
Stereo mode - 135 - dB
S/N (A-weighted) (Note 11)
Mono mode (Note 12) - 138 - dB
Inter-channel Isolation (1 kHz) 110 120 - dB
DC Accuracy
Inter-channel Gain Mismatch - - 0.3 dB
Gain Drift - 100 - ppm/C
Differential Output Current (IOUTP - IOUTN) (Note 13) - 72.8 - mApp
Center Current (Note 14) - 0 - mA
Load Capacitance (Analog Output Pins) (Note 15) - - 5 pF
Note 8. 0 dBr is defined as 0.805 times the level of a 7-bit full-scale in two's complement format.
Note 9. The AK4191 is used as the input source with DSMSEL[1:0] bits = “00” and OBIT[1:0] bits = “00”.
Note 10. Absolute resistance error of subsequent stage circuits (Figure 31) recommended to be less
than 0.1 % to meet specifications.
Note 11. 2’s complement “0” signal input.
Note 12. External circuits shown in Figure 32 are used in Mono mode.
Note 13. When the input signal is 0 dBr, the output current can be calculated by the following formula:
IOUTL (Typ. @ 0 dBr) = (IOUTLP) - (IOUTLN) = 72.8 mApp × (VREFHL - VREFLL)/5.
IOUTR (Typ. @ 0 dBr) = (IOUTRP) - (IOUTRN) = 72.8 mApp × (VREFHR - VREFLR)/5.
Note 14. Center current is the current that flows each IOUT pin during common output.
When positive input of operational amplifier in I-V Conversion = VCOML/R = (VREFHL/R +
VREFLL/R)/2
Note 15. The load capacitance value of analog output pins (IOUTLP/LN/RP/RN pins,
OPINLP/LN/RP/RN pins) is with respect to ground. The load capacitance should be as small
as possible.

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(Ta = 25 C; TVDD = 1.8 V, DVDD = 1.8 V, AVDD = 5.0 V, AVSS = DVSS = 0 V; VDDL/R = VREFHL/R =
5.0 V, VSSL/R = VREFLL/R = 0 V; VCOML/R = (VREFHL/R + VREFLL/R)/2; MCLK = 22.5792 MHz,
Sampling Frequency = BCK = 5.6448 MHz; Measurement bandwidth = 20 Hz to 20 kHz; Signal
Frequency = 1 kHz; Input Signal Level = 0.805 × Full-scale = 0 dBr (Note 8); External circuit Figure 31
Power Supplies
Parameter Min. Typ. Max. Unit
Power Supply Current
Normal operation (PDN pin = “H”)
- 12 mA
VDDL + VDDR (Note 16) -
- (16) mA
VREFHL + VREFHR - 46 - mA
AVDD - 2 - mA
TVDD - 0.1 - mA
DVDD - 2 - mA
Total power dissipation
- 308 - mW
VDDL/R + VREFHL/R + AVDD + TVDD + DVDD
Power down (PDN pin = “L”) (Note 17)
VDDL/R + VREFHL/R + AVDD + TVDD + DVDD - 10 150 μA
Standby (Note 18)
VDDL/R + VREFHL/R + AVDD + TVDD + DVDD - 1000 - μA
Note 16. The values in () at VDDL/R total power supply current indicate consumption current when
there is zero input data.
Note 17. In power down state, the PSN pin = TVDD and all other digital input pins including clock pins
(MCLK, BCK) are connected to DVSS.
Note 18. In the standby mode, the external clock (MCLK, BCK) is input, and the other digital input pins
are connected to DVSS. The standby mode is set to STBY bit = “1” in the register control
mode.

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OSR256 mode (OSR pin = “L” or OSR bit = “0”)

(Ta = 25 C; TVDD = 1.8 V, DVDD = 1.8 V, AVDD = 5.0 V, AVSS = DVSS = 0 V; VDDL/R = VREFHL/R =
5.0 V, VSSL/R = VREFLL/R = 0 V; VCOML/R = (VREFHL/R + VREFLL/R)/2; MCLK = 22.5792 MHz,
Sampling Frequency = BCK = 11.2896 MHz; Measurement bandwidth = 20 Hz to 20 kHz; Signal
Frequency = 1 kHz; Input Signal Level = 0.805 × Full-scale = 0 dBr (Note 8); External circuit Figure 31;
SC pin = “L” or SC bit = “0”
Parameter Min. Typ. Max. Unit
Dynamic Characteristics (Note 9)
BW = 20 kHz 0 dBr - -116 - dB
THD
BW = 40 kHz 0 dBr - -116 - dB
(Note 10)
BW = 80 kHz 0 dBr - -116 - dB
0 dBr - -116 - dB
BW = 20 kHz
-60 dBr - -71 - dB
0 dBr - -113 - dB
THD+N BW = 40 kHz
-60 dB - -68 - dB
0 dBr - -110 - dB
BW = 80 kHz
-60 dBr - -65 - dB
Dynamic Range (-60 dBr; A-weighted) - 134 - dB
Stereo mode - 134 - dB
S/N (A-weighted) (Note 11)
Mono mode (Note 12) - 137 - dB
Inter-channel Isolation (1 kHz) - 120 - dB
DC Accuracy
Inter-channel Gain Mismatch - - 0.3 dB
Gain Drift - 100 - ppm/C
Differential Output Current (IOUTP - IOUTN) (Note 13) - 72.8 - mApp
Center Current (Note 14) - 0 - mA
Load Capacitance (Analog Output Pins) (Note 15) - - 5 pF

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(Ta = 25 C; TVDD = 1.8 V, DVDD = 1.8 V, AVDD = 5.0 V, AVSS = DVSS = 0 V; VDDL/R = VREFHL/R =
5.0 V, VSSL/R = VREFLL/R = 0 V; VCOML/R = (VREFHL/R + VREFLL/R)/2; MCLK = 22.5792 MHz,
Sampling Frequency = BCK = 11.2896 MHz; Measurement bandwidth = 20 Hz to 20 kHz; Signal
Frequency = 1 kHz; Input Signal Level = 0.805 × Full-scale = 0 dBr (Note 8); External circuit Figure 31
Power Supplies
Parameter Min. Typ. Max. Unit
Power Supply Current
Normal operation (PDN pin = “H”)
- 18 mA
VDDL+VDDR (Note 16) -
- (24) mA
VREFHL+VREFHR - 46 - mA
AVDD - 3 - mA
TVDD - 0.1 - mA
DVDD - 4 - mA
Total power dissipation
- 343 - mW
VDDL/R + VREFHL/R + AVDD + TVDD + DVDD
Power down (PDN pin = “L”) (Note 17)
VDDL/R + VREFHL/R + AVDD + TVDD + DVDD - 10 150 μA
Standby (Note 18)
VDDL/R + VREFHL/R + AVDD + TVDD + DVDD - 1000 - μA

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 [AK4499EX]

8.2. DC Characteristics

(Ta = -40 to 85 C; VDDL/R = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = DVDD to 3.6 V, DVDD =
1.7 to 1.98 V; unless otherwise specified.)
Parameter Symbol Min. Typ. Max. Unit
MCLK pin (Note 19)
(VTSEL pin = “L” or VTSEL bit = “0”)
High-Level Input Voltage VIHCK 1.36 - - V
Low-Level Input Voltage VILCK - - 0.34 V
MCLK pin (Note 19)
(VTSEL pin = “H” or VTSEL bit = “1”)
High-Level Input Voltage VIHCK 2.2 - - V
Low-Level Input Voltage VILCK - - 0.8 V
1.7 V  TVDD < 3.0 V (except MCLK pin)
High-Level Input Voltage VIH 80 %TVDD - - V
Low-Level Input Voltage VIL - - 20 %TVDD V
3.0 V  TVDD  3.6 V (except MCLK pin)
High-Level Input Voltage VIH 70 %TVDD - - V
Low-Level Input Voltage VIL - - 30 %TVDD V
Low-Level Output Voltage
(SDA pin, 2.0 V < TVDD  3.6 V: Iout = 3 mA) VOL - - 0.4 V
(SDA pin, 1.7 V  TVDD  2.0 V: Iout = 3 mA) VOL - - 20%TVDD V
Input Leakage Current (Note 20) Iin -10 - +10 μA
Note 19. The VTSEL pin should be changed while the PDN pin is “L”, and VTSEL bit should be
changed while STBY bit = “1”, MCLK is stopped with MSTBYN bit = “0”, MUTEN pin = “L” or
MUTEN bit = “0”.
Note 20. The PSN pin has internal pull-up resistors. Therefore, the PSN pin is not included in this
specification.

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 [AK4499EX]

8.3. Switching Characteristics

(Ta = -40 to 85 C; VDDL/R = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = DVDD to 3.6 V, DVDD =
1.7 to 1.98 V, CL = 20 pF)
Parameter Symbol Min. Typ. Max Unit
Master Clock Timing, 11.2896MHz (typ.)
Frequency fCLK 10 11.2896 13.824 MHz
Duty Cycle dCLK 45 50 55 %
Master Clock Timing, 22.5792MHz (typ.)
Frequency fCLK 20 22.5792 27.648 MHz
Duty Cycle dCLK 45 50 55 %
BCK Timing @ OSR pin = “H” or OSR bit = “1”
Frequency fBCK 5 5.6448 6.912 MHz
Duty Cycle dBCK 45 50 55 %
BCK Timing @ OSR pin = “L” or OSR bit = “0”
Frequency fBCK 10 11.2896 13.824 MHz
Duty Cycle dBCK 45 50 55 %
Frequency Ratio from MCLK to BCK @ OSR pin = “H” or OSR bit = “1”
MCLK = 11.2896 MHz - 2 - -
MCLK = 22.5792 MHz - 4 - -
Frequency Ratio from MCLK to BCK @ OSR pin = “L” or OSR bit = “0”
MCLK = 11.2896 MHz - 1 - -
MCLK = 22.5792 MHz - 2 - -
Multi-bit Audio Interface Timing
Multi-bit Mono mode
(STME bit = “0”)
(LRSEL1-0 pins = “HH”)
MBD7-1 Hold Time tMBH 5 - - nsec
MBD7-1 Setup Time tMBS 5 - - nsec
Multi-bit Stereo mode
(STME bit = “1”)
(LRSEL1-0 pins = “LL”, “LH”, “HL”)
BCK Edge to MBD7-1 tBMD -5 - 5 nsec

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 [AK4499EX]

Parameter Symbol Min. Typ. Max. Unit

Control Interface Timing (3-wire Serial Control Mode):
CCLK Period tCCK 200 - - nsec
CCLK Pulse Width Low tCCKL 80 - - nsec
Pulse Width High tCCKH 80 - - nsec
CDTI Setup Time tCDS 40 - - nsec
CDTI Hold Time tCDH 40 - - nsec
CSN “H” Time tCSW 150 - - nsec
CSN “” to CCLK “” tCSS 50 - - nsec
CCLK “” to CSN “” tCSH 50 - - nsec
2
Control Interface Timing (I C-Bus Control Mode):
SCL Clock Frequency fSCL - - 400 kHz
Bus Free Time Between Transmissions tBUF 1.3 - - μsec
Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 - - μsec
Clock Low Time tLOW 1.3 - - μsec
Clock High Time tHIGH 0.6 - - μsec
Setup Time for Repeated Start Condition tSU:STA 0.6 - - μsec
SDA Hold Time from SCL Falling (Note 21) tHD:DAT 0 - - μsec
SDA Setup Time from SCL Rising tSU:DAT 0.1 - - μsec
Rise Time of Both SDA and SCL Lines tR - - 0.3 μsec
Fall Time of Both SDA and SCL Lines tF - - 0.3 μsec
Setup Time for Stop Condition tSU:STO 0.6 - - μsec
Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 - 50 nsec
Capacitive load on bus Cb - - 400 pF
Power down & Reset Timing (Note 22)
PDN Accept Pulse Width tAPD 600 - - nsec
PDN Reject Pulse Width tRPD - - 30 nsec
Note 21. The data must be held for more than 300 nsec (the falling time of SCL).
Note 22. The PDN pin must be held “L” for more than 600 nsec to ensure a reliable reset.

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 [AK4499EX]

8.4. Timing Diagram

1/fCLK

VIHCK
MCLK
VILCK
tCLKH tCLKL dCLK = tCLKH × fCLK × 100,
tCLKL × fCLK × 100

Figure 2. Clock Timing

1/fBCK

VIH
BCK
VIL

tMBS tMBH

VIH
MBD7-1
VIL

Figure 3. Audio Interface Timing

(Mono mode, STME bit = “0”, PSN pin = “L”, LRSEL1-0 pins = “HH”, PSN pin = “H”)

1/fBCK

VIH
BCK
VIL
tBMD tBMD

VIH
MBD1/2/3/4/5/6/7
VIL

tBMD tBMD
VIH
MBD1/2/3/4/5/6/7
VIL

Figure 4. Audio Interface Timing

(Stereo mode, STME bit = “1”, PSN pin = “L”, LRSEL1-0 pins = “LL”, “LH”, “HL”, PSN pin = “H”)

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 [AK4499EX]

VIH
CSN
VIL

tCSS tCCKL tCCKH tCCK

VIH
CCLK
VIL

tCDS tCDH

VIH
CDTI C1 C0 R/W A4
VIL

Figure 5. WRITE Command Input Timing

tCSW

VIH
CSN
VIL

tCSH

VIH
CCLK
VIL

VIH
CDTI D3 D2 D1 D0
VIL

Figure 6. WRITE Data Input Timing

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 [AK4499EX]

VIH
SDA
VIL
tBUF tLOW tR tHIGH tF
tSP
VIH
SCL
VIL

tHD:STA tHD:DAT tSU:DAT tSU:STA tSU:STO

Stop Start Start Stop

Figure 7. I2C-Bus mode Timing

tAPD tRPD

VIH
PDN
VIL

Figure 8. Power Down & Reset Timing

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 [AK4499EX]

9. Functional Descriptions

Each function of the AK4499EX is controlled by pins (Pin Control mode) or registers (Register Control
mode) (Table 1). Select the control mode by setting the PSN pin. The AK4499EX must be powered
down by the PDN pin when changing the PSN pin setting. There is a possibility of malfunction if the
device is not powered down when changing the control mode since the previous setting is not
reinitialized.

Register settings are invalid in Pin Control mode, and pin settings are invalid in Register Control mode.
Table 2 shows available functions of each control mode.

Table 1. Pin/Register Control Mode Select

PSN pin Control Mode
L Register Control mode
H Pin Control mode

Table 2. Function List Pin/Register Control Mode

Function Pin Control mode Register Control mode
Operation rates select
OSR pin OSR bit
OSR256/OSR128
Stereo/Mono mode
STME bit
Select LRSEL1-0 pins
Output Signal Select LSELN, RSELN bit
Sound Control SC pin SC bit
VIH/L level select of
VTSEL pin VTSEL bit
MCLK
Phase Inversion Not available (Note 23) INVL/R bit
On/off control of
Not available (Note 24) MSTBN bit
standby by MCLK
MUTE Function MUTEN pin MUTEN pin, MUTEN bit

Note 23. In Pin Control mode, the phase inversion function cannot be used.
Note 24. In Pin Control mode, the standby function by MCLK is forced ON.

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 [AK4499EX]

9.1. Sampling Speed mode Setting

The AK4499EX has two sampling speed mode, such as OSR256 mode and OSR128 mode. The
AK4499EX is set OSR256 mode when setting OSR pin = “L” or OSR bit = “0”, and it is set OSR128
mode when setting OSR pin = “H” or OSR bit = “1”.

In case the data sample rate is changed with OSR pin or bit, the AK4499EX should be mute by MUTEN
pin or bit to prevent output the noise from the AK4499EX. OSR pin or bit should be changed more than
50 μsec later MUTEN pin or bit signal down edge. MUTEN pin or bit signal should be turned up at 50
μsec later OSR pin or bit fixed setting and BCK clock frequency changing.

MUTEN pin
(1)

MUTEN bit
(in Register Control mode) (2) (2)
Internal
MUTE signal
(4) (5)

BCK Input
(5)
OSR pin
Setting 1 Setting 2
or OSR bit

Internal State Normal Operation Mute Initialize Normal Operation

MBD7-1 Input “0” data

(3)
Current Output
(IOUTLP/RP)

Notes:
(1) Both MUTEN pin and MUTEN bit are enable in Register Control mode. The period of MUTEN pin
= “L” or MUTEN bit = “0” must be 100 μsec or more continuously.
(2) It takes up to 77 μsec until the internal MUTE signal is changed when changing MUTEN pin or
MUTEN bit.
(3) The AK4499EX output “0” data via Current Output pins (IOUTLP, IOUTLN, IOUTRP, IOUTRN)
when the internal MUTE signal is “1”.
(4) MCLK frequecny should be changed more than 77 μsec later from setting MUTEN pin = “L” or
MUTEN bit = “0”. This sequence avoids noisy data output caused by the frequency ratio of MCLK
to BCK being out of the normal range.
(5) When MUTEN is released, the initialization sequence is executed. The period between the
switching of the BCK clock frequency or OSR setting and the release of MUTEN pin or MUTEN bit
is at least 50 μsec to execute the initialization sequence correctly.

Figure 9. OSR pin and bit setting sequence

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9.2. System Clock

The external clocks, which are required to operate the AK4499EX, are MCLK and BCK. In OSR256
mode, the MCLK speed is same or twice against BCK speed. In OSR128 mode, the MCLK speed is
twice or quadruple against BCK speed. The AK4499EX will detect the MCLK and BCK frequency ratio
to generate the internal operation clock from MCLK automatically. The phase between MCLK and BCK
is not critical. The frequency of operating SR DAC is same as that of BCK.

The frequency of MCLK should be changed in Power Down, Standby or Mute states. This sequence
avoids noisy data output caused by the frequency ratio of MCLK to BCK being out of the normal range.
Refer to 9.9.3. Mute Function for the detailed sequence.

The AK4499EX is automatically placed in standby state when MCLK is stopped for more than 1 μsec
during a normal operation, and the analog output becomes floating state. When MCLK is input again, the
AK4499EX exits standby state and starts operation. This standby function will be disable by setting
MSTBN bit = “1” in Register Control mode. The AK4499EX is in power down state until MCLK and BCK
are supplied, and the analog output is floating state when power down is released (PDN pin = “L” → “H”).

Table 3. BCK, MCLK frequency and Sampling Speed Mode

Sampling 44.1 kHz base 48 kHz base Frequency
OSR pin
Speed BCK MCLK BCK MCLK Ratio from
or OSR bit
Mode frequency frequency frequency frequency MCLK to BCK
11.2896 MHz 12.288 MHz 1
L or 0 OSR256 11.2896 MHz 12.288 MHz
22.5792 MHz 24.576 MHz 2
11.2896 MHz 12.288 MHz 2
H or 1 OSR128 5.6448 MHz 6.144MHz
22.5792 MHz 24.576 MHz 4

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 [AK4499EX]

9.3. Audio Inerface Format

Two audio interface format modes, such as Multi-bit Mono mode and Multi-bit Stereo mode, are
selectable by using the LRSEL1-0 pins in Pin Control mode and STME bit in Register Control mode.

Table 4. Audio Interface Format Select (Pin Control mode)

LRSEL1 pin LRSEL0 pin Audio Interface Format
L L
L H Multi-Bit Stereo
H L
H H Multi-Bit Mono

Table 5. Audio Interface Format Select (Register Control mode)

STME bit Audio Interface Format
0 Multi-Bit Mono
1 Multi-Bit Stereo

9.3.1. Multi-Bit Mono Interface mode (single channel mode, no adding)

In this mode, the AK4499EX receives one channel of audio data. The data is two's complement format,
each of which must be input to the MBD7-1 pins in synchronizing to BCK. The data is read out the rising
edge of BCK input. Figure 10 shows the data format in Multi-bit Mono mode. D0[7:1], D1[7:1], D2[7:1]
and D3[7:1] in the figure are one channel data.

BCK

MSB MBD7 D0[7] D1[7] D2[7] D3[7]

MBD6 D0[6] D1[6] D2[6] D3[6]

MBD5 D0[5] D1[5] D2[5] D3[5]

MBD4 D0[4] D1[4] D2[4] D3[4]

MBD3 D0[3] D1[3] D2[3] D3[3]

MBD2 D0[2] D1[2] D2[2] D3[2]

LSB MBD1 D0[1] D1[1] D2[1] D3[1]

Figure 10. Multi-Bit Mono Interface mode

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 [AK4499EX]

9.3.2. Multi-Bit Stereo Interface mode

In this mode, the AK4499EX receives stereo audio data. The data is two's complement format, each of
which must be input to the MBD7-1 pins in synchronizing to BCK. The data is read out by the BCK
input. Figure 11 shows the data format in Multi-bit Stereo mode. R0[7:1], L1[7:1], R1[7:1], L2[7:1],
R2[7:1] and L3[7:1] in the figure are one channel data.

BCK Lch Rch

MBD7 R0[7] L1[7] R1[7] L2[7] R2[7] L3[7]

MSB

MBD6 R0[6] L1[6] R1[6] L2[6] R2[6] L3[6]

MBD5 R0[5] L1[5] R1[5] L2[5] R2[5] L3[5]

MBD4 R0[4] L1[4] R1[4] L2[4] R2[4] L3[4]

MBD3 R0[3] L1[3] R1[3] L2[3] R2[3] L3[3]

MBD2 R0[2] L1[2] R1[2] L2[2] R2[2] L3[2]

LSB
MBD1 R0[1] L1[1] R1[1] L2[1] R2[1] L3[1]

Figure 11. Multi-Bit Stereo Interface mode

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 [AK4499EX]

9.4. Multi-Bit Interface Mode Select, Output Signal Select

(1) Register Control Mode (PSN pin = “L”)

Input and output combination of the AK4499EX can be changed by LSELN bit and RSELN bit (Table 6).
These functions are available on Multi-bit Stereo Interface audio format (STME bit = “1”).

Table 6. Output Signal Selection (Register Control mode)

LSELN bit RSELN bit IOUTLP/N IOUTRP/N
0 0 Lch Input Rch Input (default)
0 1 Lch Input Lch Input
1 0 Rch Input Rch Input
1 1 Rch Input Lch Input

(2) Pin Control Mode (PSN pin = “H”)

Audio interface format mode and Input/output combination of the AK4499EX can be changed by the
LRSEL1-0 pins (Table 7).

Table 7. Audio Interface Format and Output Signal Selection (Pin Control mode)
Audio Interface Output Selection
LRSEL1 pin LRSEL0 pin
Format IOUTLP/N IOUTRP/N
L L Lch Input Rch Input
L H Multi-Bit Stereo Lch Input Lch Input
H L Rch Input Rch Input
H H Multi-Bit Mono Mono Input Mono Input

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 [AK4499EX]

9.5. Phase Inversion Function (Register Control Mode)

The output signal phase can be inverted by INVL bit and INVR bit (Table 8).

Table 8. Phase Inversion Function

INVL bit INVR bit IOUTLP/N IOUTRP/N
0 0 Normal Normal (default)
0 1 Normal Invert
1 0 Invert Normal
1 1 Invert Invert

LSELN bit
INVL bit
Lch Input “0”
“1”
- IOUTL Output
1
“1”
“0”
RSELN bit
INVR bit
“1”
“1”
Rch Input - IOUTR Output
1
“0”
“0”

Figure 12. Output Signal Select and Phase Inversion Block Diagram

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9.6. Sound Control

The AK4499EX has a function to control the sound quality by setting SC pin or SC bit (Table 9). The
analog characteristics of the AK4499EX are specified in Setting 1, and the characteristics are not
guaranteed at Setting 2.

Table 9. Sound Quality Select Mode

SC pin (bit) Sound
L (0) Measurement Mode (Setting 1)
H (1) Sound Quality Mode (Setting 2)

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9.7. Power Up Sequence of External Operational Amplifier for I-V Conversion

The output current of the AK4499EX is converted voltage by external I-V conversion circuit. The
operational amplifier used in this I-V conversion circuit must be powered up or stopped while the
AK4499EX is powered up. By doing this, a feedback path of the operational amplifier is maintained, and
it can protect the AK4499EX from fatal damage caused by excessive voltage input.

AK4499EX Power
0V
(1) (4)
External OPAMP Power (+)
(I-V Circuit) 0V

(2) (3)
External OPAMP Power (-) 0V
(I-V Circuit)

External OPAMP Output Hi-Z (near VSS) Hi-Z (near VSS)

(VOUTP - VOUTN)

Normal Operation

Notes:
(1) Power up the AK4499EX. Refer to 9.8. Power Up/Down Function.
(2) Power up an external operational amplifier after power up the AK4499EX.
(3) When power down the system, the external amplifier must be powered down before the
AK4499EX.
(4) Power down the AK4499EX after the external amplifier. Refer to 9.8. Power Up/Down Function.

Figure 13. Power Up Sequence of External Operational Amplifier for I-V Conversion

There is a possibility of IC destruction due to breakdown of the withstanding voltage of the analog
output pins (IOUTLP/LN/RP/RN) if the power supply of the external operational amplifier is turned on
before power up the AK4499EX. Therefore, connect a Zener diode (VRWM = 6 to 7 V) between each
VDDL/R and VSSL/R if the power up/down sequence shown in Figure 13 cannot be followed.

If the power supply of the external amplifier is turned on before power up the AK4499EX, there is a
possibility that click noise occurs due to DC difference. Connect an external mute circuit to the analog
signal line to prevent this click noise (Figure 35).

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 [AK4499EX]

9.8. Power Up/Down Function

The AK4499EX is powered down by setting the PDN pin to “L”. In power down state, all circuits stop
operation and initialized, and the analog output becomes floating (Hi-Z) state. The PDN pin must be
held “L” for more than 600 nsec to ensure a reliable reset. There is a possibility of malfunctions with the
“L” pulse less than 600 nsec. Power down is released by setting the PDN pin to “H” from “L”.

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 [AK4499EX]

(1) Register Control mode (PSN pin = “L”)

The PDN pin = “H” and MSTBN bit = “0”, the AK4499EX is started to output analog signal by inputting
MCLK. If the MSTBN bit is changed from “0” to “1” after the PDN pin sets to “H”, the analog outputs of
the AK4499EX are “0” data outputs, not Hi-Z, even when MCLK is not supplied. After that all internal
circuits are turned on and the AK4499EX is set in normal operating state, after the MUTEN pin = “H”
and MUTEN bit = “1” is set and BCK is input. Figure 14 shows system timing example of power
down/up.
Power
(TVDD,DVDD,AVDD)

Power (10)
(VDDL/R)

Analog Reference
(VREFHL/R)

PDN pin (1)

Clock Input (5) (8)

(MCLK, BCK)

MUTEN pin and

MUTEN bit
(7) (7)

Internal State Power Down Mute Initialize Normal Mute Power Down
Operation

“0”data “0”data (8)

MBD7-1 Input

Mode Setting (8)

(9)
(3) (6) (3)
Current Output (2) Hi-Z (2) Hi-Z
(IOUTLP/RP)

External Mute (4) (4)

Mute ON Mute ON

Notes:
(1) The PDN pin must be held “L” for more than 600 nsec after supplying TVDD, DVDD, AVDD and
VDDL/R reached 90 %.
(2) Analog outputs are floating (Hi-Z) in power down state.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) Mute the analog output externally if click noise (3) adversely affect system performance.
(5) Clock inputs (MCLK and BCK) can be stopped in power down state.
(6) Click noise occurs at the edge of mode setting signals (LRSELN bit, LRSELN bit and SC bit).
This noise is output even if “0” data is input.
(7) Setting MUTEN pin = “H” and MUTEN bit = “1”, it is available to output signal and all circuit is
powered up. When MUTEN is released, the initialization sequence is executed. It takes up to
77 μsec until the internal MUTE signal is changed when changing MUTEN pin and MUTEN bit.
(8) Do not input all clocks, data and mode setting signals when power supplies are powered down.
(9) It takes about 7-BCK cycles to output the analog signal corresponding to the digital input.
(10) VDDL/R must be supplied at the same time as or before VREFHL/R.

Figure 14. Power up/down sequence example in Register Control mode

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 [AK4499EX]

(2) Pin Control mode (PSN pin = “H”)

The PDN pin = “H”, the AK4499EX is started to output analog signal by inputting MCLK. After that all
internal circuits are turned on and the AK4499EX is set in normal operating state, after the MUTEN pin
= “H” is set and BCK is input. Figure 15 shows system timing example of power down/up.

Power
(TVDD,DVDD,AVDD)

Power (10)
(VDDL/R)

Analog Reference
(VREFHL/R)

PDN pin (1)

Clock Input (5) (8)

(MCLK, BCK)

MUTEN pin
(7) (7)

Internal State Power Down Mute Initialize Normal Mute Power Down
Operation

“0”data “0”data (8)

MBD7-1 Input

Mode Setting (8)

(9)
(3) (6) (3)
Current Output (2) Hi-Z (2) Hi-Z
(IOUTLP/RP)

External Mute (4) (4)

Mute ON Mute ON

Notes:
(1) The PDN pin must be held “L” for more than 600 nsec after supplying TVDD, DVDD, AVDD and
VDDL/R reached 90 %.
(2) Analog outputs are floating (Hi-Z) in power down state.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) Mute the analog output externally if click noise (3) adversely affect system performance.
(5) Clock inputs (MCLK and BCK) can be stopped in power down state.
(6) Click noise occurs at the edge of mode setting signals (LRSEL0 pin, LRSEL1 pin and SC pin).
This noise is output even if “0” data is input.
(7) Setting the MUTEN pin = “H”, it is available to output signal and all circuit is powered up. When
MUTEN is released, the initialization sequence is executed. It takes up to 77 μsec until the
internal MUTE signal is changed when changing the MUTEN pin.
(8) Do not input all clocks, data and mode setting signals when power supplies are powered down.
(9) It takes about 7-BCK cycles to output the analog signal corresponding to the digital input.
(10) VDDL/R must be supplied at the same time as or before VREFHL/R.

Figure 15. Power up/down sequence example in Pin Control mode

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9.9. Internal State

The AK4499EX has five states shown in Table 10. Power Down, Standby and Mute states are
controlled by PDN pin, STBY bit, MCLK input, MUTEN pin and MUTEN bit.

Table 10. Internal States

MUTEN Audio IOUTLP/N,
PDN STBY MCLK SR
State pin (bit) Interface, IOUTRP/N
pin bit input DAC
(Note 26) DWA state
Power Down L - (*) - (*) - (*) OFF OFF Hi-Z
Standby H 1 - (*) - (*) OFF OFF Hi-Z
Standby (MCLK Stop) Not
H 0 - (*) OFF OFF Hi-Z
(Note 25) Supplied
Mute H 0 Supplied L (0) OFF ON “0” data
Normal Operation H 0 Supplied H (1) ON ON Signal output
(*); - means “Do not care”

Note 25. In Register Control mode, this function is valid by MSTBN bit = “0” setting. Output pins and
internal state depends on the PDN pin, STBY bit and the MUTEN pin setting, in case MSTBN
bit = “1”.
Note 26. The internal state depends only on the setting of the MUTEN pin in Pin Control mode, and it
depends on the setting of the MUTEN pin and MUTEN bit in Register Control mode (Table 11).

9.9.1. Standby Sequence by MCLK Input

The AK4499EX detects a clock stop and all circuits except MCLK stop detection circuit and Control
Register stops operation if MCLK is not input for more than 1 μsec during operation (PDN pin = “H”). In
this case, the analog output goes floating state (Hi-Z). The AK4499EX returns to normal operation after
starting to supply MCLK again. This function is disabled to set MSTBN bit = “1” in Register Control mode.

PDN pin (4)

MCLK Input MCLK Stop

(1) (1)
Internal State Normal Operation Standby Normal Operation

MBD7-1 Input (3)

Output Current (2) Hi-Z

(IOUTLP/RP)

Notes:
(1) The AK4499EX detects MCLK stop and becomes standby state when MCLK edge is not
detected for more than 1 μsec during operation.
(2) The analog output goes to floating state (Hi-Z).
(3) Click noise can be reduced by inputting “0” data when stopping and resuming MCLK supply.
(4) Resume MCLK input to release the standby state by MCLK. In this case, power up sequence by
the PDN pin is not necessary.

Figure 16. Standby Sequence by MCLK Input

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 [AK4499EX]

9.9.2. Standby Sequence by STBY bit

The AK4499EX is in standby by setting STBY bit. All circuits stop operation with STBY bit = “1” except
MCLK stop detection, Control register and Clock divider circuits. In this case, the analog output
becomes floating (Hi-Z). Figure 17 shows Standby sequence by Standby bit.

STBY bit

MUTEN bit

Internal State Normal Operation Standby Normal Operation

MBD7-1 Input “0” data

(2) (2)
Current Output (1) Hi-Z
(IOUTLP/RP)

Notes:
(1) The analog output goes to floating state (Hi-Z), STBY bit = “1”.
(2) Click noise can be reduced by inputting “0” data.

Figure 17. Standby Sequence by STBY bit

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 [AK4499EX]

9.9.3. Mute Function

(1) Register Control mode (PSN pin = “L”)

MUTE function starts by the MUTEN pin = “L” or MUTEN bit =”0” in Register Control Mode. The mute
state setting is as shown in Table 11.

Table 11. MUTE state setting

MUTEN pin MUTEN bit Operation
L 0 Mute
L 1 Mute
H 0 Mute
H 1 Normal Operation

Audio Interface and DWA are stopped by setting MUTEN pin to “L” or MUTEN bit to “0”, and the
AK4499EX output “0” data via Current Output pins (IOUTLP, IOUTLN, IOUTRP, IOUTRN). Figure 18
shows Mute sequence by MUTEN pin and MUTEN bit.

MUTEN pin
(1)

MUTEN bit
(2) (2)
Internal
MUTE signal
(4) (5)

MCLK Input

Internal State Normal Operation Mute Initialize Normal Operation

MBD7-1 Input “0” data

(6) (3) (6)

Current Output
(IOUTLP/RP)

Notes:
(1) Both MUTEN pin and MUTEN bit are enable in Register Control mode. The period of MUTEN pin
= “L” or MUTEN bit = “0” must be 100 μsec or more continuously.
(2) It takes up to 77 μsec until the internal MUTE signal is changed when changing MUTEN pin and
MUTEN bit.
(3) The AK4499EX output “0” data via Current Output pins (IOUTLP, IOUTLN, IOUTRP, IOUTRN)
when the internal MUTE signal is “1”.
(4) MCLK frequency should be changed more than 77 μsec later from setting MUTEN pin = “L” or
MUTEN bit = “0”. This sequence avoids noisy data output caused by the frequency ratio of MCLK
to BCK being out of the normal range.
(5) When MUTEN is released, the initialization sequence is executed. The period between the
switching of the clock frequency and the release of MUTEN pin or MUTEN bit is at least 50 μsec
to execute the initialization sequence correctly.
(6) It takes about 7-BCK cycles to output the analog signal corresponding to the digital input.

Figure 18. Mute function in Register Control mode

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 [AK4499EX]

(2) Pin Control mode (PSN pin= “H”)

Audio Interface and DWA are stopped by setting the MUTEN pin to “L”, and the AK4499EX output “0”
data via Current Output pins (IOUTLP, IOUTLN, IOUTRP, IOUTRN). Figure 19 shows Mute sequence
by the MUTEN pin.

(1)
MUTEN pin
(2) (2)
Internal
MUTE signal
(4) (5)

MCLK Input

Internal State Normal Operation Mute Initialize Normal Operation

MBD7-1 Input “0” data

(6) (3) (6)

Current Output
(IOUTLP/RP)

Notes:
(1) The period of the MUTEN pin = “L” must be 100 μsec or more continuously.
(2) It takes up to 77 μsec until the internal MUTE signal is changed when changing the MUTEN pin.
(3) The AK4499EX output “0” data via Current Output pins (IOUTLP, IOUTLN, IOUTRP, IOUTRN)
when the internal MUTE signal is “1”.
(4) MCLK frequency should be changed more than 77 μsec later from setting the MUTEN pin = “L”.
This sequence avoids noisy data output caused by the frequency ratio of MCLK to BCK being out
of the normal range.
(5) When MUTEN is released, the initialization sequence is executed. The period between the
switching of the clock frequency and the release of the MUTEN pin is at least 50 μsec to execute
the initialization sequence correctly.
(6) It takes about 7-BCK cycles to output the analog signal corresponding to the digital input.

Figure 19. Mute function in Pin Control mode

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9.10. Register Control Interface

The AK4499EX has register control interface. This interface is enabled when the PDN pin is “H”. Control
interface mode can be switched by the I2C pin (Table 12). The I2C pin should be set while the PDN pin
is “L”. Setting the PDN pin to “L” resets the registers to their default values.

Table 12. Register Control Interface Mode Select

I2C pin Mode
L 3-wire Serial Control Mode
H I2C-Bus Control Mode

9.10.1. 3-wire Serial Control Mode (I2C pin = “L”)

Internal registers may be written to through 3-wire µP interface pins: CSN, CCLK and CDTI. The data
on this interface consists of Chip address (2-bit, C1/0), Read/Write (1-bit; fixed to “1”, write only),
Register address (MSB first, 5-bit) and Control data (MSB first, 8-bit). The data is output on a falling
edge of CCLK, and the data is received on a rising edge of CCLK. Writing data is enabled by capturing
D0. The maximum clock speed of CCLK is 5 MHz. If the address exceeds “02H”, the address counter
will “roll over” to “00H” and the next write address will be “00H”.

Setting the PDN pin to “L” resets the registers to their default values.

C1-0 : Chip Address (C1 bit = CAD1 pin, C0 bit = CAD0 pin)
R/W : READ/WRITE (Fixed to “1”, Write only)
A4-0 : Register Address
D7-0 : Control Data

Figure 20. Control I/F Timing

Notes:
(1) The AK4499EX does not support read commands in 3-wire serial control mode.
(2) When the PDN pin = “L”, writing into control registers is prohibited.
(3) The control data cannot be written when the CCLK rising edge is 15 times or less during CSN is
“L”

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 [AK4499EX]

9.10.2. I2C-Bus Control Mode (I2C pin = “H”)

The AK4499EX supports the fast-mode I2C-Bus.

(1) WRITE Operation

Figure 21 shows the data transfer sequence for the I2C-Bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (Figure 27). After the START condition, a slave address is sent. This address is seven bits
long followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the
slave address are fixed as “00100”. The next bits are CAD1 and CAD0 (device address bits). This bit
identifies the specific device on the bus. The hard-wired input pin (CAD1 pin, CAD0 pin) sets these
device address bits (Figure 22). If the slave address matches that of the AK4499EX, the AK4499EX
generates an acknowledge and the operation is executed. The master must generate the acknowledge-
related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 28). A
R/W bit value of “1” indicates that the read operation is to be executed, and “0” indicates that the write
operation is to be executed.

The second byte consists of the control register address of the AK4499EX, and the format is MSB first.
The most significant three bits are fixed as “000” (Figure 23). The data after the second byte contains
control data. The format is MSB first, 8-bit (Figure 24). The AK4499EX generates an acknowledge after
each byte is received. Data transfer is always terminated by a STOP condition generated by the master.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 27).

The AK4499EX can perform more than one byte write operation per sequence. After receipt of the third
byte the AK4499EX generates an acknowledge and awaits the next data. The master can transmit
more than one byte instead of terminating the write cycle after the first data byte is transferred. After
receiving each data packet, the internal address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds “02H” prior to generating a stop
condition, the address counter will “roll over” to “00H” and the previous data will be overwritten.

The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state
of the data line can only be changed when the clock signal on the SCL line is LOW (Figure 29) except
for the START and STOP conditions.

S
T S
A R/W= “0” T
R O
T P
Slave Sub
SDA S
Address Address(n)
Data(n) Data(n+1) Data(n+x) P

A A A A A A
C C C C C C
K K K K K K

Figure 21. Data Transfer Sequence in I2C-Bus Mode

0 0 1 0 0 CAD1 CAD0 R/W

(CAD1 and CAD0 are set by pin)
Figure 22. The First Byte

0 0 0 A4 A3 A2 A1 A0
Figure 23. The Second Byte

D7 D6 D5 D4 D3 D2 D1 D0
Figure 24. Byte Structure after The Second Byte

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 [AK4499EX]

(2) READ Operation

Set the R/W bit = “1” for the READ operation of the AK4499EX. After transmission of data, the master
can read the next address’s data by generating an acknowledge instead of terminating the write cycle
after the receipt of the first data word. After receiving each data packet, the internal address counter is
incremented by one, and the next data is automatically taken into the next address. If the address
exceeds “02H” prior to generating stop condition, the address counter will “roll over” to “00H” and the
data of “00H” will be read out.

The AK4499EX supports two basic read operations: Current Address Read and Random Address
Read.

(2)-1 Current Address Read

The AK4499EX has an internal address counter that maintains the address of the last accessed word
incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next
CURRENT READ operation would access data from the address “n+1”. After receipt of the slave
address with R/W bit “1”, the AK4499EX generates an acknowledge, transmits 1-byte of data to the
address set by the internal address counter and increments the internal address counter by 1. If the
master does not generate an acknowledge but generates a stop condition instead, the AK4499EX
ceases the transmission.

S
T S
A R/W= “1” T
R O
T P
Slave
SDA S
Address
Data(n) Data(n+1) Data(n+2) Data(n+x) P

A A A A A A
C C C C C C
K K K K K K

Figure 25. Current Address Read

(2)-2 Random Address Read

The random read operation allows the master to access any memory location at random. Prior to
issuing the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation.
The master issues a start request, a slave address (R/W bit = “0”) and then the register address to
read. After the register address is acknowledged, the master immediately reissues the start request and
the slave address with the R/W bit “1”. The AK4499EX then generates an acknowledge, 1 byte of data
and increments the internal address counter by 1. If the master does not generate an acknowledge but
generates a stop condition instead, the AK4499EX ceases the transmission.

S S
T T S
A R/W= “0” A R/W= “1” T
R R O
T T P
Slave Sub Slave
SDA S
Address Address(n)
S
Address
Data(n) Data(n+1) Data(n+x) P

A A A A A A A
C C C C C C C
K K K K K K K

Figure 26. Random Address Read

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 [AK4499EX]

SDA

SCL

S P
start condition stop condition

Figure 27. Start Condition and Stop Condition

DATA
OUTPUT BY
TRANSMITTER

not acknowledge

DATA
OUTPUT BY
RECEIVER
acknowledge

SCL FROM
1 2 8 9
MASTER

S
clock pulse for
acknowledgement
START
CONDITION

Figure 28. Acknowledge (I2C-Bus)

SDA

SCL

data line change

stable; of data
data valid allowed

Figure 29. Bit Transfer (I2C-Bus)

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 [AK4499EX]

9.11. Register Map

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 Default

00H Control1 MSTBN VTSEL OSR STME LSELN RSELN STBY MUTEN 00
01H Control2 SC DSEL[4] 0 0 0 0 INVL INVR 00
02H Control3 DSEL[3] DSEL[2] DSEL[1] DSEL[0] 0 0 0 TST 00

Notes:
(1) In 3-wire serial control mode, the AK4499EX does not support read commands.
(2) The AK4499EX supports read command in I2C-Bus control mode.
(3) If the address exceeds “02H”, the address counter will “roll over” to “00H” and the next
write/read address will be “00H”.
(4) Bits indicated as 0 in each address must contain a “0” value. Malfunctions may occur if writing
“1” value to these bits.
(5) Writing after 03H is forbidden. Malfunctions may also occur by this action.
(6) When the PDN pin goes to “L”, the registers are initialized to their default values.

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 [AK4499EX]

9.12. Register Definitions

【00H】
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control1 MSTBN VTSEL OSR STME LSELN RSELN STBY MUTEN
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

MUTEN: The AK4499EX is set in Mute state (Table 10).

0: Mute (default)
1: Normal Operation

STBY: Standby ON/OFF control bit

0: Normal Operation (default)
1: Standby

LSELN, RSELN:
Input and output combination can be changed by LSELN bit and RSELN bit (Table 6).

STME: Audio interface format mode select bit (Table 5).

0: Multi-bit Mono mode (default)
1: Multi-bit Stereo mode

OSR: Sampling speed mode setting bit (Table 3).

0: OSR256 mode (default)
1: OSR128 mode

VTSEL: Digital input voltage level of MCLK select bit.

0: High Level = 1.36 V, Low Level = 0.34 V (default)
1: High Level = 2.2 V, Low Level = 0.8 V

MSTBN: Stand-by mode by MCLK input enable.

0: enable (default)
1: disable

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 [AK4499EX]

【01H】
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Control2 SC DSEL [4] 0 0 0 0 INVL INVR
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

INVL, INVR:
The output signal phase can be inverted by INVL bit and INVR bit (Table 8).

DSEL [4]: “0” value must be written to this bit. Otherwise, malfunction may occur.

SC: Sound control

0: Measurement mode (default)
1: Sound quality mode

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 [AK4499EX]

【02H】
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Control3 DSEL [3] DSEL[2] DSEL[1] DSEL[0] 0 0 0 TST
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

TST: Test bit. “0” value must be written to this bit. Otherwise, malfunction may occur.

DSEL [3:0]: “0100” value must be written to this bit. Otherwise, malfunction may occur.

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 [AK4499EX]

10. Recommended External Circuits

10.1. External Connection Example

Reference Reference
Digital 1.8V Voltage 5.0V Voltage 0V Analog 5.0V
ZD
10u 2200u 10u
+ + +
51 0.1u 0.1u 0.1u
Ground
VR

VREFHL 58
VREFLL 57

VREFLL 55
VREFHL 60

VREFLL 56

VSSL 54
AVDD 61

VREFHL 59

VSSL 53
AVSS 62

VSSL 52
MCLK 63

VDDL 51
DVDD 64

VDDL 50
VDDL 49
EF
HR
VREFHL
+ 2k
10u VoffL
1 DVSS
10u 0.1u VCOML 48 +
+ 10u 2k
2 TVDD
DEV2 47 VR
3 PDN 1u VREFLL
EF
AK4191 EXTCLN 46 +

Circuit
BCK HR
4

I-V
LN
IOUTLN 45
AK4499EXEQ

Ext. Mute
Lch LPF
5 MBD1

Lch Out
Circuit
OPINLN 44

Mute
Lch

Lch
6 MBD2
OPINLP 43

Circuit
MBD3

I-V
LP
7
IOUTLP 42
8 MBD4 1u
EXTCLP 41 + +15V
9 MBD5 1u
EXTCRP 40 + -15V

Circuit
10 MBD6 N

RP
I-V
IOUTRP 39

Ext. Mute
Rch LPF
11 MBD7 N

Rch Out
Circuit
OPINRP 38

Mute
Rch

Rch
N.C. 12 TSTO
OPINRN 37

Circuit

RN
I-V
13 OSR/CSN
IOUTRN 36
14 LRSEL0/CCLK/SCL 1u
EXTCRN 35 + +15V
15 LRSEL1/CDTI/SDA DEV1 34 -15V
18 DSEL2/CAD1

VREFHR
16 MUTEN VCOMR 33
20 VTSEL/I2C
17 SC/CAD0

22 VREFHR
23 VREFHR

2k
21 VREFHR

26 VREFLR
24 VREFLR
25 VREFLR

VoffR
32 VDDR
30 VDDR
31 VDDR
27 VSSR

uP
28 VSSR
29 VSSR

+
19 PSN

10u 2k
VR
VREFLR
EF
HR
0.1u 0.1u
+ 2200u + 10u Ground
ZD +
Electrolytic Capacitor
Reference Reference Analog 5.0V
Ceramic Capacitor
Voltage 5.0V Voltage 0V
Resistor

(AVDD = VDDL/R = VREFHL/R = 5.0 V, TVDD = DVDD = 1.8V, Register Control Mode)

Notes:
(1) Power lines of AVDD, TVDD and VDDL/R should be distributed separately, from the point with low
impedance of regulators or other parts.
(2) AVSS, DVSS add VSSL/R must be connected to the same ground. (The ground should have low
impedance as a solid pattern. THD+N characteristics will degrade if there are impedances
between each VSS.)
(3) Connect VCOML/R and positive input pin of I-V conversion op-amp from the midpoint each Voff
circuits that connects VREFHL/R and VREFLL/R via the external voltage divider resistors. Voff
lines do not connect any other pins except VCOML/R and positive input pins.
(4) It is recommended to input MCLK via a 51 Ω damping resistor. Without the resistor, there is a
possibility that THD+N characteristic degrades because of high-frequency noise of MCLK.
(5) All digital input pins except pull-up pins should not be allowed to float.
(6) There is a possibility of IC destruction due to breakdown of the withstanding voltage of the analog
output pins (IOUTLP/LN/RP/RN). Connect a Zener diode (VRWM = 6 to 7 V) between each
VDDL/R and VSSL/R if the power up/down sequence shown in Figure 13 cannot be followed.
(7) Figure 35 is not necessary for the AK4499EX. Refer to 10.5. External Mute Circuit for details.

Figure 30. Typical Connection Diagram

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 [AK4499EX]

10.2. Grounding and Power Supply Decoupling

To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, TVDD,
DVDD and VDDL/R. AVDD and VDDL/R are supplied from analog supply in system, and TVDD and
DVDD are supplied from digital supply in system. Power lines of VDDL/R should be distributed
separately, from the point with low impedance of regulators or other parts.

AVSS, DVSS and VSSL/R must be connected to the same ground. Decoupling capacitors for high
frequency should be placed as near as possible to the AK4499EX.

10.3. Reference Voltage

The differential voltage between the VREFHL/R pins and the VREFLL/R pins set the analog output
current. The VREFHL/R pins are normally connected to 5.0V reference voltage, and the VREFLL/R pins
are normally connected to the 0V reference voltage. Connect a 0.1 µF ceramic capacitor and 2200 µF
electrolytic capacitor between the VREFHL/R pins and the VREFLL/R pins.

The VREFHL/R and VREFLL/R pins should avoid noises from other power supplies. Connect the
VREFHL/R to the analog 5.0V via a 1 Ω resistor, and the VREFLL/R pins to the analog ground via a 1 Ω
resistor when it is difficult to obtain expected analog characteristics because of noises from other power
supplies (A low pass filter of fc = 36 Hz will be composed with the 2200 µF capacitor and the 1 Ω
resistor. It removes signal frequency noise from other power supply lines). However, the direct voltage
at the VREFHL/R and VREFLL/R pins drops ±23 mV since a current of ±23 mA flows at VREFH/L via 1
Ω resistor.

The ceramic capacitors should be connected as near as possible to the pins. All digital signals,
especially clocks, should be kept away from the VREFHL/R and VREFLL/R pins to avoid unwanted
coupling into the AK4499EX.

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 [AK4499EX]

10.4. Analog Output

Figure 31 shows an example of Lch external I-V conversion circuit of the AK4499EX. The analog
outputs are full differential current outputs. The Differential Output Current (IOUTP - IOUTN) is 72.8
mApp (typ.). The output current is converted to voltage by the I-V conversion circuit. The common
voltage of the current output pins (IOUTLN/LP/RN/RP, OPINLN/LP/RN/RP) is 2.5 V(typ.). The common
voltage of the signal after I-V conversion (VOUTLP/LN/RP/RN) can be adjusted by changing the
positive inputs of op-amp for I-V conversion and the VCOML/R input from (VREFHL/L + VREFLL/R)/2.
For example, input Voff = 1.9 V to obtain 0 V signal common voltage at Rfb = 360 Ω.

The output range of I-V conversion is 4.6 Vrms centered around signal common voltage, and 9.2 Vrms
after differential summing. IOUTLP/RP current and IOUTLN/RN current cannot be summed. The
differential outputs are summed externally after I-V conversion.

AK4499EX I-V Conversion Circuit

VCOML Voff

+15V
Rfb:360
-15V
IOUTLN +
10u LPF Circuit
180p
0.1u 500 100
- VOUTLP Analog
OPINLN Voff +
* Out
2.5V 10u
+ 1.2n
0.1u
1n
+ Voff Circuit
10u
1.2n VREFHL
0.1u
OPINLP -
2k 2.5V
Voff +
2.5V *
10u
VOUTLN 500 100 + Voff
180p + 10u
0.1u 2k
IOUTLP 0.1u
VREFLL
Rfb:360

VCOMR Voff

Figure 31. Lch External I-V Conversion Circuit Example (same for Rch)

Notes:
(1) Input voltage range of the positive input of op-amp for I-V conversion circuit is from 0.5 V (typ.)
to 2.5 V (typ.). The signal common voltage (VOUTLP and VOUTLN) does not have to be 0 V.
(2) Resistors used in the I-V conversion circuit are recommended to be within 0.1 % of absolute
error to meet specifications.

Table 13. Frequency Response of Differential Output Circuit

Gain (1 kHz, typ.) 0.0 dB
Frequency 20 kHz -0.18 dB
Response 40 kHz -0.69 dB
(ref: 1 kHz, typ.) 80 kHz -2.28 dB

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 [AK4499EX]

10.4.1. Mono mode

In mono mode, connect I-V conversion voltage output terminals with resistors and take differential
output from the midpoint (Voff) of the connection as shown in Figure 32.

AK4499EX I-V Conv. Circuit +15

-15

360
IOUTLN
+
180p 10u
510 100
- 0.1u
OPINLN Voff L +
*
10u 1.2n
+
0.1u 1n
+
10u 1.2n 100
OPINLP - 0.1u
Voff L + 100
* 510 100
180p 10u
+
0.1u
IOUTLP VOUTP
360

360
IOUTRP
+ 100 VOUTN
180p 10u 510 100 100
- 0.1u
OPINRP Voff R +
*
10u 1.2n
+
0.1u
+
1n Voff Circuits.
10u
1.2n There are two circuits.
OPINRN - 0.1u
Voff R +
*
10u VREFHx
180p + 510 100
0.1u 2k 2.5V
IOUTRN
Voff x
360 + 10u
2k
0.1u
VREFLx
x = L/R

Figure 32. External I-V Conversion Circuit Example (Mono mode)

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 [AK4499EX]

10.4.2. External Analog Low Pass Filter Example

Differential voltage signal after I-V conversion is summed by differential summing circuit (low pass
filter). Figure 33 shows an example of differential summing circuit and Table 14 shows the frequency
response.

AK4499EX I-V Conv.Circuit Differential Summing Circuit

+15V

-15V
IOUTLN

1200 600
OPINLN
68n 3.3n +
VOUTLN 10u
15 0.1u
2
-
7 VOUTL
3
+
3.3n
* 4
10u
Analog
15 + Out
OPINLP VOUTLP 0.1u

1200 68n 600

IOUTLP
Voff Circuit

Figure 33. External 2nd Order LPF Circuit Example for PCM mode (fc = 112 kHz (typ.), Q = 0.692 (typ.))

Table 14. Frequency Response of External LPF Circuit Example

Gain (1 kHz, typ.) -6.02 dB
Frequency 20 kHz -6.04 dB
Response 40 kHz -6.14 dB
(ref:1 kHz, typ.) 80 kHz -7.19 dB

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 [AK4499EX]

10.4.3. Feedback Loop of External Operational Amplifier

Figure 34 shows the internal state of the AK4499EX when the analog output is Hi-Z and when the
analog output is “0” data output. Feedback loop of the external amplifier is always maintained while the
power supply of the AK4499EX is on.

AK4499EX I-V Conv. Circuit AK4499EX I-V Conv. Circuit

IOUTLN IOUTLN

(VREFHL
+VREFLL)/2
-
- +
Voff
OPINLN
Voff +
* OPINLN *

OPINLP OPINLP
-
-
Voff +
Voff + (VREFHL *
*
+VREFLL)/2

IOUTLP IOUTLP

Hi-Z “0” data output

Figure 34. Internal State of the AK4499EX when Outputting Hi-Z or “0” data output

10.5. External Mute Circuit

Click noise may occur due to DC offset if the power up/down sequence shown in Figure 13 cannot be
followed and external operational amplifier is powered up before the AK4499EX. Connect external mute
circuits shown in Figure 35 to analog signal lines to prevent a click noise. The external mute circuit
should be connected to the signal after I-V conversion (Figure 30). Base current will be input to the
transistor RN2202 when the power (5.0 V typ.) is not supplied to the VDDL/R pins. In this case, emitter
current flows to the 2SC3327 via 3.8 kΩ resistance as base current and the analog signal line is short to
the signal ground. Note that there is a possibility that THD+N performance degrades about 3 dB by
connecting an external mute circuit.

+15V +15V

10k 10k

3.8k 3.8k
VDDL VDDR
RN2202 RN2202

3.8k 3.8k

2SC3327 2SC3327

220 VOUTL 220 VOUTR

VOUTL VOUTR

Figure 35. External Mute Circuit Example

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11. Package

11.1. Outline Dimensions

64-pin HTQFP10×10 (Unit: mm)

12.0 ± 0.20

C
64 49

1 48

A
12.0 ± 0.20

10.0 ± 0.20
16 33

32
17 0.50 0.22 ± 0.05
0.10 M S A C

10.0 ± 0.20
1.00 ± 0.05
1.2 MAX

S
0.09 ~ 0.2
0.05 ~ 0.15

0.10 S
0.60 ± 0.15
(5.95)

(5.95)

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 [AK4499EX]

11.2. Material & Terminal Finish

Package molding compound: Epoxy, Halogen (Br and Cl) free

Lead frame material: EFTEC-64T
Terminal surface treatment: Solder (Pb free) plate

11.3. Marking

AKM
AK4499EXEQ

XXXXXXX

64
1

1) Pin #1 indication
2) Date Code: XXXXXXX (7 digits)
3) Marking Code: AK4499EXEQ
4) AKM Logo

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 [AK4499EX]

12. Ordering Guide

AK4499EXEQ -40 to +85 C 64-pin HTQFP (0.5 mm pitch)

AKD4499EX Evaluation Board for AK4499EX

13. Revision History

Date (Y/M/D) Revision Reason Page Contents

22/07/dd 00 First Edition

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 [AK4499EX]

IMPORTANT NOTICE

0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application
of AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor
grants any license to any intellectual property rights or any other rights of AKM or any third party
with respect to the information in this document. You are fully responsible for use of such
information contained in this document in your product design or applications. AKM ASSUMES
NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM
THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
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3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations
in which a malfunction or failure of the Product could cause loss of human life, bodily injury or
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4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
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5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws
and regulations that regulate the inclusion or use of controlled substances, including without
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6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without
prior written consent of AKM.
Rev.1

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