DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Date: - / / ---------
Enrolment no.:-………………. Signature of Professor
EXPERIMENT-01
.
.

AIM: To study Logic Gates and verify Truth Tables.

Apparatus Required:
1. Digital board DB01.
2. DC power supply+5V from external source or Digital Lab ST2611.
3. Digital multi meter or Digital Lab ST261l.
Theory:
Logic Gate is a digital circuit with one or more input but only one output. AND, OR, NAND, NOR,
NOT, EX-OR Gates are some examples of Logic Gates. Each Gate has one or two binary input variable
designated by X & Y and one binary output variable Z. The logic diagram and Truth Table of Logic
Gates is shown in experiment section.

OR Gate: The OR gate has two or more than two inputs and one output. This operation is
represented by a plus sign e.g. X +Y= Z is read X or Y is equal to Z meaning that Z=1 if X=1 or if Y=1
or if both X=1 & Y=l. If both X=0 & Y=0 then Z=0.The output voltage of OR Gate is high if any or all
of the input voltages are high that is +5 V or 1 (TTL level is used). Logic equation is Z = X + Y (X & Y
are inputs & Z is output.).

AND Gate: It has two or more than two inputs. This operation is represented by a dot or by absence
of an operator e.g. X.Y=Z or XY=Z is read X AND Y is equal to Z. The logical operation AND is
interpreted to mean that Z=l if and only if X=l and Y=l otherwise Z=0.

NOT Gate: It has one input and one output. This operation is represented by prime (bar). For
example X= Z is read X not equal to Z" meaning that Z is what X is not. In other words if X=l, then Z=0
but if X= 0 then Z=l.
Note: Refer Truth Tables and logic diagrams shown in experiment section.

Logic diagram & Observation table: X Y Z

(Logic 1 = +5 V & Logic 0 = GND) 0 0
0 1
1 0
1 1

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OR Gate
X Y Z
0 0
0 1
1 0
AND Gate 1 1

X Z
0
1
NOT Gate
Procedure:
1. Connect +5 V and ground to their indicated position on DB01 experiment board from external DC
power supply or from DC power block of Digital Lab ST2611.
2. Connect inputs 00, 01, 10, 11 as per Truth Table to pin X and Y of AND Gate.
3. Switch on the power supply.
4. Observe output Z of AND Gates on multi meter or on logic probe or on LED display of Digital
Lab ST2611 and prove Truth Tables.
Repeat above steps for remaining Logic Gates.
General Descriptions

AND-Gate(IC 7408): The 74HC/HCT08 are high-speed Si-gate CMOS devices and are pin compatible
with low power schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT08 provide the 2-input AND function.

OR-Gate(IC 7432):
The 74HC/HCT32 are high-speed Si-gate CMOS devices and are pin compatible with low power
schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The
74HC/HCT32 provide the 2-input OR function.

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 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

NOT-Gate(IC 7404):
The 74HC/HCT04 are high-speed Si-gate CMOS devices and are pin compatible with low power
schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The
74HC/HCT04 provides six inverting buffers.
Pin out diagram:
(Pin 14 = Vcc = + 5V)

Conclusion:
------------------------------------------------------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------------------- --.

Assignment Questions:

1. Simplify the Boolean function F=AB+ (AC)’+AB’C (AB+C).

2. Simplify the Boolean function F= (XY’+XYZ)’+X (Y+XY’))’.
3. Obtain the canonical sum of products form of function F (A, B) =A+B.
4. Implement and Obtain the canonical sum of products form of function
F (A, B, C, D) =AB+ACD.
5. Implement and Obtain the canonical product of sum form of function
F (A, B, C) = (A+B’) (B+C) (A+C’).
6. Implement and Obtain the canonical product of sum form of function
F (A, B, C) =A+B’C.
7. Realize the function F=B’C’+A’C’+A’B’ by basic gates.
8. Realize the function F= (A+C) (A+D’) (A+B+C’) using basic gates only.
9. Define Logic Gate?
10. Write down the uses of logic gates?

[ DIGITAL LOGIC AND DESIGN ] 3

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Date: - / / ---------
Enrolment no.:-………………. Signature of Professor

EXPERIMENT-02
.
.
AIM: To study implementation of AND, NOT and OR function with NAND and NOR Gate.
Apparatus required:
1. Digital board DB02.
2. DC power supply +5V from external source or Digital Lab ST2611.
3. Digital multi meter or Digital Lab ST2611.

Theory:
NAND & NOR Gates are said to be universal Gate because any digital system can be implemented with
them. To show that any Boolean function can be implemented with NAND Gates. It is only need to
show that logic operations AND, OR, NOT can be implemented with NAND & NOR Gates.
The implementation of AND, OR, NOT operation with NAND Gate is shown in Logic diagram in
Experiment section. The NOT operation is obtained from a two input NAND Gate. The inputs of NAND
Gate are shorted to get NOT operation. The AND operation requires two NAND Gates. The first
produces the inverted AND and second acts as an inverter to produce Normal output. The OR operation
is achieved through a NAND Gate with additional inverters in each input.
The NOR function is dual of the NAND function. All procedures and rules for NOR logic form a dual of
the corresponding procedures and rules developed for NAND logic. The conversion of NOR to AND,
OR, NOT is shown Logic diagram in Experiment section. NOT operation is obtained from a 2 input
NOR Gate with both the inputs shorted. The OR operation requires two NOR Gates. The first produces
the inverted OR and the second acts as an inverter to obtain normal output. The AND operation is
achieved through a NOR Gate with additional inverters at each input. The logic diagram and truth table
of Logic Gates is shown in experiment section

X Y Z
Logic diagram & Observation table:
0 0
(Logic 1 = +5 V & logic 0 = GND)
0 1
1 0
1 1

NAND Gate

[ DIGITAL LOGIC AND DESIGN ] 4

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

X Y Z
0 0
0 1
NOR Gate 1 0
1 1

Procedure:
1. Connect +5 V and ground to their indicated position on DB02 from external DC power supply or
from DC power block of Digital Lab ST2611.
2. Connect inputs 00, 01, 10, 11 as per truth table to pins X and Y of OR Gate switch ON the power
supply.
3. Observe output Z of Gate on multi meter or on logic probe or on LED display of Digital Lab ST2611
and prove truth table.
4. Repeat above steps for remaining Logic Gates.

General Descriptions:

NAND Gate:
The 74HC/HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power
schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The
74HC/HCT00 provide the 2-input NAND function.

NOR-Gate:
The 74HC/HCT02 is High speed CMOS Devices and are pin compatable with low power schottky TTL
(LSTTL). They are specified in compliance with JEDEC standard number 7A. The 74HC/HCT02
provide the 2-input .

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 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Conclusion:
----------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------
Assignment Questions:
1. Implement the function by NAND gates only, F=B (A+CD) +AC’.
2. Realize the function by NOR gates only, F=A (B+CD) +BC’.
3. Realize the function F=Y’Z’+X’Z’+X’Y’ by NAND gates only.
4. Realize the function F= (A+B) (A’+C) (B+D) by NOR gates only.
5. Implement the function F= (XY)’+X+(Y+Z)’ by NAND gates only.
6. Implement the function F=A+BCD’ using NAND gates only.
7. Realize the function Y=BD’E+BF+C’D’E+C’F+A using NAND gates only.
8. Implement the function F=BC’+A’B+D by NOR gates only.
9. What do you mean by Universal logic gate?
10. Implement AND, OR logic gate with the help of universal gate, with its truth table?

[ DIGITAL LOGIC AND DESIGN ] 6

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Date: - / / ---------
Enrolment no.:-………………. Signature of Professor

EXPERIMENT-03
.
.

AIM: To study methods of generating function EX – OR.

Apparatus required:
1. Digital board DB03.
2. DC powers supply +5 V from external source or Digital Lab ST2611.
3. Digital multi meter or Digital Lab ST2611.
Theory:
The exclusive-OR (EX-OR) is a logic block that compares a bit of data. When the bits are alike, the EX-
OR output is 0 and when the bits are not alike, EX-OR output is 1. With inputs X & Y EX-OR equation
is
Z = X'.Y +X.Y'=X Y

In similar manner a function of three or more variables can be expressed as

Z= (X  Y)  W = X  (Y  W) = X  Y  W.

This implies the possibility of using exclusive-OR Gates with three or more inputs. Although there are
many ways of implementing EX-OR, two logic diagrams are shown in experiment section. In first
method four NAND Gates are used to implement EX-OR function. The inputs to the first stage NAND
Gate are X & Y and the output is (XY)'. X and (XY)' are inputs to upper NAND Gate of second stage.

Its output is [X.(XY)']' = X'+XY ( Demorgan’s theorem)

(X.Y)'=(X'+Y').

The inputs to second NAND Gate are Y & (XY)'.

It's output is (Y'+X.Y)

Similarly output of last stage NAND Gate is

[(X’+XY). (Y'+XY)] = X'Y + Y'X.

In second method 2 NOT Gates, 2 AND Gates and 1 OR Gate are used. Inputs to I NAND Gate are X &
Y' and output is XY' similarly outputs of II NAND Gate is X'Y. These two outputs are inputs to OR
Gate. Its output is
Z =X'Y+Y'X.
Note: Refer Truth Tables and logic diagrams shown in experiment section.

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 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Logic diagram & Observation table:

(Logic 1= +5V & Logic 0= GND)

Fig. 1EX-OR Gate using NAND Gates

x y z
0 0
0 1
1 0
1 1
Fig. 2 EX-OR Gate using NOT, AND and OR Gates
Procedure:
1. Connect +5 V and ground to their indicated position on DB03 experiment board from external DC
power supply or from DC power block of Digital Lab ST2611.
2. Connect inputs 00, 01. 10, 11 as per Truth Table to pins X and Y of EX-OR Gate shown in fig 1.
3. Switch on the power supply.
4. Observe output Z of Gate on multi meter or on logic probe or LED display of Digital Lab ST2611
and prove Truth Table.
5. Repeat above steps for fig 2.
6.
Conclusion:
----------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------
Assignment Questions:
1. Simplify the Boolean function F=A’BC+A’BC’+ABC’+AB’C using Karnaugh map.
2. Using K map, simplify the expression F=A’BC’+ABC+ABC’.
3. Simplify the expression F=A’B’C+A’BC+A’BC’+AB’C+ABC by K map.
4. Implement and Simplify the expression F (A, B, C) =∑ (0, 2, 4, 5, 6).
5. Simplify the expression F (A, B, C, D) =m1+m5+m10+m11+m12+m13+m15.
6. Plot the logical expression F (A, B, C, D) =ABCD+AB’C’D’+AB’C+AB on four variables
Karnaugh map. Obtain the simplified expression.
7. Obtain the minimal sum of the products for the function
F(A,B,C,D,E)=∑(0,2,5,7,9,11,13,15,16,18,21,23,25,27,29,31).
8. Using Karnaugh map method obtain the minimal sum of the products expression for the
function F(A,B,C,D)=∑(0,2,3,6,7) + d(8,10,11,15).
9. Using Karnaugh map method obtain the minimal product of the sums expression for the
function F(A,B,C,D)=∑(0,2,3,6,7) + d(8,10,11,15).

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 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

10. Draw the logic circuit of EX-OR with the help of NAND gate?
11. What is Demorgan’s theorem? Explain?

[ DIGITAL LOGIC AND DESIGN ] 9

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Date: - / / ---------
Enrolment no.:-………………. Signature of Professor
EXPERIMENT-04
.
.

AIM:To study and verify Truth Table for the following digital circuits:
1. 2 Bit Binary Half Adder.
2. 3 Bit Binary Full Adder.

Apparatus required:
1. Digital board DB08.
2. DC Power Supply +5 V from external source or ST2611 Digital lab.
3. Digital Multimeter or Digital Lab ST2611.

Theory:

Half Adder:
The combinational circuit that performs the addition of two bits is called a Half Adder. This circuit has
two binary inputs and two binary outputs. The input variable X, Y designate the augends and addend
bits, the output variables Sh, Ch produces the sum and carry. The logic diagram and Truth Table are
shown in experiment section. The Boolean equation is

Sh = X’.Y +X.Y’= XY

Ch = X.Y
Full Adder:
The circuit that performs the addition of three bits (two significant bits and a previous carry) is called a
full adder. It consists of three inputs X, Y, Z. Two of the input variable, denoted by X and Y, represents
the two significant bits to be added. The third input, Z, represents the carry from the previous lower
significant position. The output Sf gives the value of the least significant bit of sum and Cf gives the
output carry. The logic diagram for 3-bit full adder is shown in experiment section. The Boolean
equation is

Sf = X’Y’Z + X’YZ’+ XY’Z’+ XYZ

Cf = X.Y + X.Z +Y.Z
The full adder introduced above forms the sum of two bits and a previous carry. Two binary numbers of
n bits each can be added in parallel by means of binary parallel adder. Consider two 2 bit numbers Y0
X0, Y1 X1
Y0 X0 Y0 X0
+ Y1 X1 = Y1 X1
SUM C0 S1 S0

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 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

It can also be constructed with two full adders in cascade, with the output carry from one full adder
connected to the input carry of the next full adder. An n bit parallel adder requires n full adder. The
Truth Table and logic diagram for 2 bit binary parallel adder is shown in experiment section.

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 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Logic diagram & Observation table:

(Logic 1 = +5 V & Logic 0=GND)
X Y Ch Sh
0 0
0 1
1 0
1 1

Fig. 1. 2 Bit Binary Half Adder

X Y Z Cf Sf
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
Fig.2. 3 Bit Binary Full Adder 1 1 1

Truth Table
Conclusion:
------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------

Assignment Questions:
1. Design half adder using basic gates. Write its truth table.
2. Realize half adder using NOR gates only.
3. Realize half subtractor using basic gates. Write its truth table.
4. Design half subtractor uing NAND gates only.
5. Implementation half adder using NAND gates only.

[ DIGITAL LOGIC AND DESIGN ] 12

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Date: - / / ---------
Enrolment no.:-………………. Signature of Professor
EXPERIMENT-05
.
.

AIM:To study and verify Truth Table for the following digital circuits:
1.2 Bit Binary Parallel Adder.
2.2 Bit Binary Half Subtractor.

Apparatus required:
1. Digital board DB08.
2. DC Power Supply +5 V from external source or ST2611 Digital lab.
3. Digital Multimeter or Digital Lab ST2611.

Half subtractor:
A half subtractor is a combinational circuit that subtracts two bits and produces their difference. It has
two inputs X, Y. X is minuend and Y is subtrahend. The output bits are designated by B h, Dh. Dh is
difference bit and Bh is borrow bit (generates the binary signal that informs the next stage

That a 1 has been borrowed). The logic diagram and Truth Table for 2 bit half subtractor is shown in
experiment section.

The Logic equation is

Dh = X’Y+XY’= XY

Y0 X0 Y1 X1 C0 S1 S0

0 0 0 1

0 1 0 1

0 1 1 1

1 0 1 0

1 0 1 1

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 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Fig. 3. 2 Bit Binary Parallel Adder Truth Table

X Y Bh Dh
0 0
0 1
1 0
1 1
Fig.4. 2 Bit Binary Half Subtractor Truth Table

Procedure:
1. Connect +5 V and ground to their indicated position on DB08 from external DC power supply or
from DC power block of Digital Lab ST2611.
2. Switch ON the power supply.
3. Connect inputs X, Y as per Truth Table to 2 bit binary Half Adder.
4. Observe output Sh, Ch on multimeter or on LED display of Digital Lab ST2611 and prove Truth
Table.
5. Switch Off the power supply.
6. Connect output Sh, Ch of 2 bit binary Half Adder to input Sh, Ch of 3 bit binary Full Adder.
7. Connect input X, Y, Z to 3 bit binary Full Adder as per Truth Table shown.
8. Observe output Sf, Cf on multimeter or on LED display of Digital Lab ST2611 and prove Truth
Table.
Repeat above steps and prove Truth Table for 2 bit binary parallel Adder and 2 bit binary Half
Subtractor.

Conclusion:
------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------

Assignment Questions:

1. Design half adder using NAND gates only.

2. Implementation half subtractor using NOR gates only.
3. Design full adder using NAND gates only.
4. Design full adder using NOR gates only.
5. Design full subtractor using NOR gates only.
6. What is the Half-Adder & Half-Subtractor? Explain with the help of its logic diagram.
7. What is the parallel binary adder? Explain with logic diagram.
8. Design full subtractor using NAND gates only.

[ DIGITAL LOGIC AND DESIGN ] 14

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Date: - / / ---------
Enrolment no.:-………………. Signature of Professor
EXPERIMENT-06
.

AIM: To study following Flip-flops:

1. R-S
2. D
3. J-K
4. T

Apparatus required:

1. Digital board, DB11

2. DC Power Supply +5 V
3. Digital Multimeter or Digital Lab ST2611.
4. TTL Clock Generator of 2 KHz

Theory:
Flip-flops are binary cells capable of storing one bit of information. A Flip-flop has two outputs, one for
the normal value and one for complement value of the bit stored in it. A flip-flop circuit can maintain a
binary state indefinitely (as long as power is delivered to the circuit) until directed by an input signal to
switch states.

Clocked RS Flip-flop:

Clocked RS Flip-flop shown in fig.1 consists of two NOR Gates and two AND Gates. The input S and R
are set and reset input and output Q and Q’ are normal and complement output. The input CP is input for
giving clock pulse. Flip-flop will change state only when CP goes from 0 to 1.

The output of two AND Gates remain at 0 as long as the clock pulse CP is 0, regardless of the S and R
input values. When the clock pulse goes to logic high level i.e. 1, information from the S and R is
allowed to reach the basic flip-flop. The set state is reached with S = 1, R = 0, and CP = 1. (For set state,
Q = 1 and for reset state, Q = O) To change to the clear state, the inputs must be S = 0, R = 1, CP = 1.
With both S = 1 and R = 1, the occurrence of a clock pulse causes both outputs to momentarily go to 0.
When the pulse is removed, the state of flip-flop is indeterminate, i.e., either state may result, depending
on whether the set or the reset input of the basic flip-flop remains a 1 longer before the transition to 0 at
the end of the pulse. The characteristics table is shown in experiment section along with logic diagram.

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 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Logic diagram & Observation table:

CP
Q S R Q (t +1)
Transition
0 →1 0 0
0 →1 0 1
0 →1 1 0
0 →1 1 1
0 →1 0 0
0 →1 0 1
0 →1 1 0
0 →1 1 1
Fig. R-S Flip-flop
(Q=Present State, Q (t+1) = Next state)
Truth Table for R-S Flip-flop

D Flip-flop:
The logic symbol and characteristics table for D flip-flop is shown in fig. 2. It has only one data input
(D) and clock input (CP). The outputs are labeled Q and Q’. The data (0 or 1) at the input 0 is delayed
one clock pulse from getting to output Q. SD and CD are active low input (Negative edge trigger) to set
and reset the flip-flop i.e. these inputs will be effective when logic 0 is applied. A D Flip flop is a
bistable circuit whose 0 input is transferred to the output after a clock pulse is received.

CP
Q D Q( t + 1)
Transition

1→ 0 0
1→ 0 1
1→ 0 0
1→ 0 1
Fig. 2 Fig. 3
Truth Table

D Flip-flop

As long as the clock input is at 0, Gates 3, 4 have a 1 in their outputs, regardless of the value of the other
inputs. The D input is sampled during the occurrence of a clock pulse (CP=1). If it is 1, the output of
Gate 3 goes to 0, switching the flip-flop to the set state (unless it was already set). If it is a 0 the output
of Gate 4 goes to 0, switching the flip-flop to the clear state.

[ DIGITAL LOGIC AND DESIGN ] 16

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

J-K Flip-flop:
A J-K flip-flop is refinement of R-S flip-flop in that the indeterminate state of the RS type is defined in
the JK type. Inputs J, K is used to set and clear the flip-flop. When both J, K are high simultaneously,
the flip-flop switches to its complement state, that is, if Q = 1, it switches to Q= 0, and vice versa. A CP
signal which remains a 1 (While J=K = 1) after the outputs have been complemented once will cause
repeated and continuous transitions of the output. To avoid this undesirable operation, the clock pulse
must have a time duration which is shorter than the propagation through the flip-flop.
The JK flip-flop shown above behaves like an R-S flip-flop, except when both J and K are 1, the clock
pulse is transmitted through one AND Gates only- the one whose input is connected to the flip-flop
output which is presently 1. Thus, if Q = 1, the output of the upper AND Gate become 1 upon
application of a clock pulse, and the flip-flop is cleared. If Q = 0, the output of lower AND Gate
becomes a 1 and the flip-flop is set. In either case, the output state of the flip-flop is complemented.
CP
Q J K Q (t +1)
Transition
1→ 0 0 0
1→ 0 0 1
1→ 0 1 0
1→ 0 1 1
1→ 0 0 0
1→ 0 0 1
Fig.4 Fig. 5 1→ 0 1 0
T Flip-flop 1→ 0 1 1
Truth Table
The flip-flop is a single input version of the JK flip-flop .As shown below; the T flip-flop is obtained
from a JK type if both inputs are tied together. The designation T shows ability of flip-flop to toggle.
Regardless of the present state of the flip-flop, it assumes the complement state when the clock pulse
occurs while input T is logic1

CP
Q T Q(t +1)
Transition
1→ 0 0
1→ 0 1
1→ 0 0
1→ 0 1
Fig. 6 Fig. 7
T Flip-Flop Logic diagram & Truth table

(Logic 1 = +5V & Logic 0= GND)

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 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Procedure:
1. Connect +5V and ground to their indicated position on DB11 experiment board from external DC
power supply or from DC power block of Digital Lab ST2611.
2. Switch on the power supply.
3. Connect inputs 0, 0, 0 to S, R, CP pins of R-S flip-flop.
4. Measure output Q (Present state).
5. Connect input 1 to CP.
6. Measure output Q. It is next state Q (t + l) for input 0, 0.
7. Repeat above steps for remaining inputs. (Before transition of clock pulse from 0 to 1, output is
present state and after transition output is next state)
8. Connect 1, 0 to pins SD and CD of D flip-flop to clear the output Q.
9. Connect 1, 1 to pins SD and CD of D flip-flop.
10. Connect inputs as per Truth Table for D flip-flop and prove Truth Table.
11. Connect output Q to Input D of D Flip-flop.
12. Connect a TIL clock pulse of 2 KHz to CP input.
13. Observe output Q on Osci1loscope. It win be 1 KHz.
14. Connect 1, 0 to pins SD and CD of JK flip-flop to clear the Output Q.
15. Connect inputs as per Truth Table of JK Flip Flop and prove it.
16. Connect input 1, 1 to J, K pins of JK flip-flop and 1, 1 to SD, CD.
17. Connect a TIL clock pulse of 2 KHz to CP input.
18. Observe output Q on Oscilloscope. It will be 1 KHz.
19. Repeat above steps to prove Truth Table for T flip-flop.

Note: Indeterminate state of RS flip-flop is determined in JK Flip-flop but problem of toggling occur
which is useful for making divide by 2 circuits.

Conclusion:
----------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------

Assignment Questions:
1. Design of S-R flip flop using NOR gates only.
2. Design of S-R flip flop using NAND gates only.
3. Design of D flip flop using NAND gates only.
4. Conversions of S-R flip flop into a D flip flop.
5. Implementations of J-K flip flop using NAND gates only.
6. Design J-K flip flop using S-R flip flop.
7. Implementations of T flip flop using NAND gates only.
8. Design of T flip flop using J-K flip flop.
9. Implementations of S-R flip flop using D flip flop.
10. Implementations of S-R flip flop using J-K flip flop.
11. Explain R-S & J-K flip flop?
12. What is D & T flip flop

[ DIGITAL LOGIC AND DESIGN ] 18

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Date: - / / ---------
Enrolment no.:-………………. Signature of Professor
EXPERIMENT-07
.

AIM: To study the following circuit and verify their Truth Table:
1. 4 To 1 Line Multiplexer.
Apparatus required:
1. Digital board DB10.
2. DC Power Supply +5 V from external source or ST2611 Digital lab.
3. Oscilloscope, Digital Multimeter or Digital Lab ST2611.

Theory:
Multiplexing means transmitting a large number of information units over a smaller number of channels
or lines. A digital multiplexer is a combinational circuit that selects binary information from one of
many input lines and directs it to a single output line. The selection of a particular input line is controlled
by a set of selection lines. There are 2n input lines and n selection lines whose bit combinations
determine which input is selected.
A 4 to 1 Line Multiplexer is shown in fig.1. Each of the four input lines, D0 to D3 is applied to one input
of an AND gate. Selection lines S1, S0 are decoded to select a particular AND gate. When S1, S0 = 10.
The AND gate associated with input D2 has two of its inputs equal to 1 and third input connected to D2.
The other three AND gates have at least one input equal to 0, which makes their output equal to 0. The
OR-gate output is now equal to the value of D2, thus providing a path from the selected input to the
output. A multiplexer is also called a data selector, since it selects one of many inputs and steers the
binary information to the output line. Whenever any input is selected which is in form of clock pulse all
other inputs should be at zero level i.e. logic 0.

A Demultiplexer is a circuit that receives information on a single line and transmits this information on
one of 2n possible output lines. The selection of a specific output line is controlled by the bit values of n
selection lines. 1 to 4 Line Demultiplexer is shown in fig. 2 the single input variable D has a path to all
four outputs, but the input information is directed to only one of the output lines, as specified by the
binary value of the two selection lines S1 and S0. If the selection lines S1, S0 = 1, 0 output D2 will be
same as the input value D, provided D =0 while all other outputs are maintained at 1. For D=1.
All outputs are at high level. Clock pulse given to D input can be obtained at output lines through
selection lines S1 S0.
Table 1a and 2a shows Truth Table for 4 to 1 Line Multiplexer and 1 to 4 line de-multiplexer.

[ DIGITAL LOGIC AND DESIGN ] 19

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Logic diagram & Observation table:

(Logic 1 = +5 V & Logic 0=GND)

D0 Dl D2 D3 S1 S0 Z

1 0 1 0 0 0

1 0 1 0 0 1

1 0 1 1 1 0

1 0 1 0 1 1

Table 1a Fig.1

Procedure:
1. Connect +5 V and ground to their indicated position on DB10 from external DC power supply or
from DC power block of Digital Lab ST2611.
2. Switch ON the power supply.
3. Connect inputs D0-D3 as per Truth Table1a to 4 to 1 line multiplexer. Circuit as shown in fig. 1.
4. Observe output, Z on Multimeter or on LED display of Digital Lab ST2611 and prove Truth Table.
5. Repeat step 3 and 4 for Table 1b. Observe results on Oscilloscope.
6. Connect input D as per Truth Table 2a to 1 to 4 Line Demultiplexer circuit as shown in fig. 2.
7. Observe output D0-D3 on Multimeter or on LED display of Digital Lab ST2611 and prove Truth
Table.
8. Repeat steps 2 & 3 for Table 2b and observe output on Oscilloscope.

Conclusion:
------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------

Assignment Questions:

1. Design of 3 to 8 line demultiplexer using basic logic gates.

2. Realize of 1 to 8 line demultiplexer using two 1 to 4 line multiplexers.
3. Implement of 1 to 4 line demultiplexer using k map.
4. Design of 1 to 16 line demultiplexer using basic logic gates.
5. Draw 1 to 64 demultiplexer tree using 1 to 16 demultiplexer.
6. Explain De-Multiplexer using 1 x 4 patterns?
7. What do you mean by Multiplexer?

[ DIGITAL LOGIC AND DESIGN ] 20

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Date: - / / ---------
Enrolment no.:-………………. Signature of Professor
EXPERIMENT-08
.

AIM: To study the following circuit and verify their Truth Table:
1. 1 To 4 Line De-Multiplexer.
Apparatus required:
4. Digital board DB10.
5. DC Power Supply +5 V from external source or ST2611 Digital lab.
6. Oscilloscope, Digital Multimeter or Digital Lab ST2611.

Theory:
Multiplexing means transmitting a large number of information units over a smaller number of channels
or lines. A digital multiplexer is a combinational circuit that selects binary information from one of
many input lines and directs it to a single output line. The selection of a particular input line is controlled
by a set of selection lines. There are 2n input lines and n selection lines whose bit combinations
determine which input is selected.
A 4 to 1 Line Multiplexer is shown in fig.1. Each of the four input lines, D0 to D3 is applied to one input
of an AND gate. Selection lines S1, S0 are decoded to select a particular AND gate. When S1, S0 = 10.
The AND gate associated with input D2 has two of its inputs equal to 1 and third input connected to D2.
The other three AND gates have at least one input equal to 0, which makes their output equal to 0. The
OR-gate output is now equal to the value of D2, thus providing a path from the selected input to the
output. A multiplexer is also called a data selector, since it selects one of many inputs and steers the
binary information to the output line. Whenever any input is selected which is in form of clock pulse all
other inputs should be at zero level i.e. logic 0.

A Demultiplexer is a circuit that receives information on a single line and transmits this information on
one of 2n possible output lines. The selection of a specific output line is controlled by the bit values of n
selection lines. 1 to 4 Line Demultiplexer is shown in fig. 2 the single input variable D has a path to all
four outputs, but the input information is directed to only one of the output lines, as specified by the
binary value of the two selection lines S1 and S0. If the selection lines S1, S0 = 1, 0 output D2 will be
same as the input value D, provided D =0 while all other outputs are maintained at 1. For D=1.
All outputs are at high level. Clock pulse given to D input can be obtained at output lines through
selection lines S1 S0.
Table 1a and 2a shows Truth Table for 4 to 1 Line Multiplexer and 1 to 4 line de-multiplexer.

[ DIGITAL LOGIC AND DESIGN ] 21

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Logic diagram & Observation table:

(Logic 1 = +5 V & Logic 0=GND)

D S1 S0 D0 D1 D2 D3

0 0 0

0 0 1

0 1 0

0 1 1

Fig. 2 Table 2a

Conclusion:
------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------

Assignment Questions:
1. Implement the three variables function F(A,B,C)=∑(0,2,4,7) with multiplexer.
2. Realize the following function using multiplexer F(A,B,C)=∑(1,3,5,6).
3. Implement the following function with a multiplexer F(A,B,C,D)=∑(0,1,3,4,8,9,15).
4. Implement BCD to Seven Segment Decoder with multiplexers.
5. Design of 4 to 1 line multiplexer using basic logic gates.

[ DIGITAL LOGIC AND DESIGN ] 22

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Date: - / / ---------
Enrolment no.:-………………. Signature of Professor
EXPERIMENT-09
.

AIM:To study the following circuit and verify their truth table.
1. 8 to 3 line Encoder circuit.
Apparatus required:

1. Digital board DB09.

2. DC Power Supply +5 V from external source or ST2611 Digital lab.
3. Digital Multimeter or Digital Lab ST2611.

Theory:
Discrete quantities of information are represented in digital systems with binary codes. 2n distinct
elements can be represented by a binary code of n bits. An encoder has 2n input lines and n output lines.
The output lines generate the binary code for the 2n input variables.

Fig. 1 shows 8 to 3 line encoder. It consists of eight inputs D0-D7, and three outputs X, Y, Z that
generates the corresponding binary number. X is MSB.

It is constructed with OR gates whose inputs can be determined from the truth table 1.
The encoder in fig. 1 assumes that only one input line can be equal to 1 at any time. The circuit has eight
inputs and could have 28 = 256 possible input combinations. Only eight of these combinations have been
considered. The other input combinations are don't-care conditions.
A decoder is a digital function that produces a reverse operation from that of an encoder. A decoder is a
combinational circuit that converts binary information from n input lines to a maximum of 2 n unique
output lines. Fig 2 shows 3 to 8 line decoder. The three inputs X, Y, Z are decoded in to eight outputs
D0-D7, each output representing one of the minterms of the three input variables. The three inverters
provide the complement of the inputs and each one of the eight AND gate generates one of the
minterms. Truth table 2 shows different input combinations for 3 to 8 line decoder.

[ DIGITAL LOGIC AND DESIGN ] 23

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Logic diagram & Observation table:

D0 Dl D2 D3 D4 D5 D6 D7 X Y Z
(Logic 1 = +5 V & Logic 0=GND)
1 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0

0 0 1 0 0 0 0 0

0 0 0 1 0 0 0 0

0 0 0 0 1 0 0 0

0 0 0 0 0 1 0 0

0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 1

Fig. 1 Truth Table 1

Procedure:
1. Connect + 5 V and ground to their indicated position on DB09 from external DC power supply or
from DC power block of Digital Lab ST2611.
2. Connect inputs D0-D7 as per Truth Table 1 to 8 to 3 line Encoder circuit as shown in fig. 1.
3. Switch on the power supply.
4. Observe output X, Y, Z on multimeter or on LED display of Digital Lab ST2611 and prove Truth
Table.
5. Connect inputs X, Y, Z as per truth table 2 to 3 to 8 line Decoder circuit of fig. 2.
6. Observe output D0-D7 on multimeter or on LED display of Digital Lab ST2611 and prove Truth
Table.
7. Repeat above steps for remaining input.

Conclusion:
------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------

Assignment Questions:
1. Design of 2 to 4 line decoder using basic logic gates only.
2. Design of 3 to 8 line decoder using basic logic gates only.
3. Implement the following Boolean function using a 3 to 8 decoder and external gates

[ DIGITAL LOGIC AND DESIGN ] 24

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

4. 4. F(A,B,C)=∑m(2,4,5,7).
5. Design priority encoder using k map.
6. Implementation of Octal to Binary Encoder using basic gates.
7. Implement the following function using 4 to 16 line decoder F=∑m(1,2,4,7,8,11,12,13).

[ DIGITAL LOGIC AND DESIGN ] 25

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Date: - / / ---------
Enrolment no.:-………………. Signature of Professor
EXPERIMENT-10
.

AIM:To study the following circuit and verify their truth table.
1. 3 to 8 line Decoder circuit.

Apparatus required:

5. Digital board DB09.

6. DC Power Supply +5 V from external source or ST2611 Digital lab.
7. Digital Multimeter or Digital Lab ST2611.

Theory:
Discrete quantities of information are represented in digital systems with binary codes. 2n distinct
elements can be represented by a binary code of n bits. An encoder has 2n input lines and n output lines.
The output lines generate the binary code for the 2n input variables.

Fig. 1 shows 8 to 3 line encoder. It consists of eight inputs D0-D7, and three outputs X, Y, Z that
generates the corresponding binary number. X is MSB.

It is constructed with OR gates whose inputs can be determined from the truth table 1.
The encoder in fig. 1 assumes that only one input line can be equal to 1 at any time. The circuit has eight
inputs and could have 28 = 256 possible input combinations. Only eight of these combinations have been
considered. The other input combinations are don't-care conditions.
A decoder is a digital function that produces a reverse operation from that of an encoder. A decoder is a
combinational circuit that converts binary information from n input lines to a maximum of 2 n unique
output lines. Fig 2 shows 3 to 8 line decoder. The three inputs X, Y, Z are decoded in to eight outputs
D0-D7, each output representing one of the minterms of the three input variables. The three inverters
provide the complement of the inputs and each one of the eight AND gate generates one of the
minterms. Truth table 2 shows different input combinations for 3 to 8 line decoder.

[ DIGITAL LOGIC AND DESIGN ] 26

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

Logic diagram & Observation table:

(Logic 1 = +5 V & Logic 0=GND)

X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1
Fig. 2 Truth Table 2
Procedure:
1. Connect + 5 V and ground to their indicated position on DB09 from external DC power supply
or from DC power block of Digital Lab ST2611.
2. Connect inputs D0-D7 as per Truth Table 1 to 8 to 3 line Encoder circuit as shown in fig. 1.
3. Switch on the power supply.
4. Observe output X, Y, Z on multimeter or on LED display of Digital Lab ST2611 and prove
Truth Table.
5. Connect inputs X, Y, Z as per truth table 2 to 3 to 8 line Decoder circuit of fig. 2.
6. Observe output D0-D7 on multimeter or on LED display of Digital Lab ST2611 and prove Truth
Table.
7. Repeat above steps for remaining input.

Conclusion:
------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
Assignment Questions:
1. Design of 2 to 4 line decoder using basic logic gates only.
2. Design of 3 to 8 line decoder using basic logic gates only.
3. Implement the following Boolean function using a 3 to 8 decoder and external gates
4. F(A,B,C)=∑m(2,4,5,7).
5. Design priority encoder using k map.
6. Implementation of Octal to Binary Encoder using basic gates.
7. Implement the following function using 4 to 16 line decoder F=∑m(1,2,4,7,8,11,12,13).
8. A combinational circuit is defined by the following Boolean functions. Design circuit

[ DIGITAL LOGIC AND DESIGN ] 27

 DEPARTMENT OF INSTITUTE OF ADVANCE COMPUTING

with a decoder and external gates.

9. Design a parity generator using the basic gates to produce digital words with odd parity.
10. Assume the input to be three bit binary words.

[ DIGITAL LOGIC AND DESIGN ] 28