TITLE CARD

Quarter 2/Week 4-5

Catherine C. Lising
Porac Model Community High School
Guide Card

Hello! I am teacher Electronica. Join

me in exploring the electronic timing
circuit.

What are you going to learn after

the lesson?
Discuss the operation of an
electronic timing circuit
Counters *Registers *Memories

L et me introduce to you the operation of an electronic

Counters
timing circuit
Registers Memories

Counters, Registers and Memories

In general counters, registers and memories are vastly used in
the design of digital systems. Counters are functional for generating
timing variables to sequence and control operations in the digital
system. Registers are used to load and store binary information
when the clock pulse of the flip-flop circuit is enabled. Memories
are important for storage of programs and data.
 L et us check
you got!
what

Direction: Choose the letter of the correct answer and write it on your
answer sheet.
✔ 1.) A counter is fundamentally a _________ sequential circuit that pro-
ceeds through the predetermined sequence of states only when input
pulses are applied to it.
a. register c. flipflop
b. memory unit d. arithmetic logic unit
✔ 2. ) Match the following sequential Circuits with associated functions
1. Counter -------- A. Storage of Program & data in a digital computer
2. Register -------- B. Generation of timing variables to sequence the
digital system operations
3. Memory --------- C. Design of Sequential Circuits
Codes:
a. 1-A , 2-B , 3-C c. 1-C , 2-A , 3-B
b. 1-C , 2-B , 3-A d. 1-B , 2-C , 3-A
✔ 3.) The terminal count of a modulus-11 binary counter is
a. 1010 b. 1000 c. 1001 d. 1100
4.) A BCD counter is a
✔
a. binary counter c. decade counter
b. Full-modulus counter d. divide by-10 counter

✔ 5.)A counter circuit is usually constructed of ____________

a. A number of latches connected in cascade form
b. A number of NAND gates connected in cascade form
c. A number of flip-flops connected in cascade
d. A number of NOR gates connected in cascade form

✔
6. The main difference between a register and a counter is __________.
a. A register has no specific sequence of states
b. A counter has no specific sequence of states
c. A register has capability to store one bit of information but counter
has n-bit
d. A register counts data
✔
7. A flip flop stores __________
a. 10 bit of information c. 2 bit of information
b. 1 bit of information d. 3-bit information
✔ 8. A modulus-12 ring counter requires a minimum of __________.
a. 10 FF b. 12 FF c. 6 FF d. 2 FF

✔ 9. The process of transferring binary data to a register.

a. coding b. decoding c. loading d. shifting
10. A register is used to
✔
a. Store data c. Provide pulse
b. Count data d. Shift data

L et’s us do some review!

In our previous topic we discussed concepts involving digital circuits.

A digital circuit, also called a logic circuit, carries out a logical
operation. Three elemental circuits—AND, OR, and NOT—can be
combined to build any desired logical operation. Logic circuits are
expressed using logical expressions and circuit symbols. A truth table
indicates what the circuit’s output will be for all combination of
inputs.

Do the task below and move

with me on the Learning Station.
This will equip you with
knowledge and skills that you will
use along the way.

Direction: Rearrange the

jumbled letters to reveal
the hidden word.

1. isgererts - These are used to load and store

binary information when the clock pulse of the flip-flop
circuit is enabled.
2. ertsuocn - Sequential circuits that count the number of pulses given to
the input terminal.
3. sieemmor - Digital systems that store data either temporarily or for a
long term.
 Learning Station 1: A Quick Way to Learn About Counters

Counters

A digital device with a predefined state output based on the

clock pulse and application. The output of the counter can be used
to count the number of pulses. Generally, counters consist of a flip-
flop arrangement which can be synchronous counter or asynchro-
nous counter. In synchronous counter, only one clock i/p is given to
all flip-flops, whereas in asynchronous counter, the o/p of the flip
flop is the clock signal from the nearby one.
Types of Counters:
 Asynchronous Counters
 Synchronous Counters
 Asynchronous Decade Counters
 Synchronous Decade Counters
 Asynchronous Up-Down Counters
 Synchronous Up-Down Counters

Asynchronous Counters
The exterior clock is connected to
the clock i/p of the FF0 (first flip-
flop) only. So, this FF changes the
state at the decreasing edge of
every clock pulse, but FF1 changes
only when activated by the
decreasing edge of the Q o/p of
FF0. Because of the integral propa-
gation delay through a FF, the
change of the i/p clock pulse and
a change of the Q o/p of FF0 can
never occur at precisely the same
time. So, the FF’s cannot be
Diagram of a 2-bit asynchronous counter
activated concurrently, generating
an asynchronous operation.

Note that for ease, the changes of Q0,Q1 & CLK in the above
diagram are shown as concurrent, even though this is an
asynchronous counter. Actually, there is a small delay
between the Q0, Q1 and CLK changes.
Note that for ease, the changes of Q0,Q1 & CLK in the above diagram
are shown as concurrent, even though this is an asynchronous counter.
Actually, there is a small delay between the Q0, Q1 and CLK changes.
The circuit diagram of the two bit ripple counter includes four different
states ,each one consisting with a count value. Likewise, a counter with
n FFs can have 2N states. The number of states in a counter is called as
its mod number. Therefore a two-bit counter is a mod-4 counter.

Asynchronous Decade Counters

Counters with states less than 2n. These are designed to have the
no. of states in their series. These are called shortened sequences
which are accomplished by driving the counter to recycle before
going through all of its states. A common modulus for counters with
shortened sequence is 10. A counter with 10-states in its series is called
a decade counter.

Asynchronous decade counter circuit diagram Sequence of the decade counter

When the counter counts to ten, then all the FFs will be cleared. Notice
that only Q1&Q3 both are used to decode the count of 10, that is
called partial decoding. At the same time one of the other states from
0-9 have both Q1&Q3 will be high. The series of the decade counter
table is given above.
Asynchronous Up–Down Counters
The below circuit is a three bit up & down counter, that counts UP or
DOWN based on the control signal status. When the UP i/p is at 1 & the
DOWN i/p is at 0, the NAND gate between FF0 & FF1 will gate the non-
inverted o/p (Q) of flip flop (FF0) into the clock i/p of flip flop (FF1). Like-
wise, the non-inverted o/p of Flip Flop1 will be gated through the other
NAND gate into the clock i/p of flip-flop2. Therefore the counter will
count up.

Asynchronous Up-Down Counter Circuit Diagram

Once the control i/p (UP) is at 0 & DOWN is
at 1, the inverted o/ps of flip-flop0 (FF0)
and flip-flop1 (FF) are gated into the clock
i/ps of FF1 & FF2 separately. If the FFs are
initially changed to 0’s, then the counter
will go through the below series as i/p
pulses are applied. Notice that an
asynchronous up-down counter is slower
than an UP counter/down counter
because of an extra propagation delay
introduced by the NAND gates.

Synchronous Counters
In this type of counters, the CLK i/ps of all the FFs are connected
together and are activated by the i/p pulses. So, all the FFs change
states instantaneously. The circuit diagram below is a three bit
synchronous counter. The inputs J and K of flip-flop0 are connected to
HIGH. Flip-flop 1 has its J &K i/ps connected to the o/p of flip-flop0
(FF0), and the inputs J & K of flip-flop2 (FF2) are connected to the o/p
of an AND gate that is fed by the o/ps of flip-flop0 and flip-flop1. When
the both the outputs of FF0 & FF1 are HIGH. The positive edge of the
fourth CLK pulse will cause FF2 to alter its state because of the AND
gate.
The series of the three bit counter table is given below. The
major advantage of these counters is that there is no increasing time
delay due to all FFs are
activated in parallel. Thus, the
max operating frequency of
this synchronous counter will
be considerably higher than
for the equivalent ripple
counter.

Synchronous Counters Circuit Diagram

CLK Pulses of the Synchronous Counters

Synchronous Decade Counters
Synchronous counter counts from 0-9 similar to asynchronous counter
and then again recycles zero. This process is done by driving the 1010
states back to the 0000 state. This is termed as truncated sequence,
that can be designed by the below circuit.

Synchronous Decade Counter Circuit Diagram

Synchronous Decade Counter Circuit Diagram
From the series on the right table, we
can observe that
• Q0 ties on each and every CLK
pulse
• Q1 alters on the next clock pulse
every time when Q0=1 & Q3=0.
• Q2 alters on the next clock pulse
every time when Q0=Q1=1.
• Q3 alters on the next CLK pulse
each and every time when Q0=1,
Q1=1 & Q2=1 (count 7), or when
Sequence of the Synchronous Decade Counter
Q0=1 & Q3=1 (count 9).
The above characteristics are employed with the AND gate or OR
gate. The logic diagram of this is shown in the above diagram.
Synchronous Up-Down Counters
A three bit synchronous Up-Down counter, tabular form and series are
given below. This type of counter has an up-down control i/p similar to
asynchronous up-down counter, that is used to control the counter’s
direction through a certain series

The series of the table shows

• Q0 ties on each CLK pulse for both up &
down series
 • When Q0=1 for the up series, then the state of the Q1 changes on
the next CLK pulse.
• When Q0=0 for the down series, then the state of the Q1 changes
on the next CLK pulse.
• When Q0=Q1=1 for the up series, then the state of the Q2 changes
on the next CLK pulse.
When Q0=Q1=0 for the down series, then the state of the Q2 changes
on the next CLK pulse.
The above characteristics are employed with the AND gate, OR
gate and NOT gate. The logic diagram of this is shown in the above
diagram.

Station
2: REGISTER

Register
Registers are binary storage elements that consist of flip-flops and gates.
The flip-flops in a register can either be JK or D flip-flops. The number of
flip-flops used in a register depends on the bits to be stored. If two bits
are to be stored then two flip-flops are used. Thus, each flip-flop is
capable of storing only single bit. Though the flip-flop stores the data, it
is the logic gate that determines the manner in which the data is
transferred into the register. The process of transferring binary data to a
register is termed as loading.

Classification of registers
1. Depending on the input and output
a. SISO (serial input-serial output)
b. SIPO (serial input-parallel output)
c. PISO (parallel input– serial output)
d. PIPO (parallel input– parallel output)
2. Depending on application
a. Shift register
b. Storage register
SISO Shift Register Storing “1111” D Flip flop truth table

CLK D Qn+1
0 x Qn

1 0 0

1 1 1

Do you want to know the

difference between SISO and
SIPO? Just continue your journey
and find out.

SIPO Shift Register

It is similar to a serial in serial out (SISO) register the

only difference being the manner by which the output is
taken out of the register. The data is entered serially one bit/
pulse and all the 4-bit data is loaded into the register.
 SISO Shift Register

Data Loaded
Shift/Load 0 DA DB DC DD

1 1 0 1

Data Shifted
Shift/Load 1 Clock Pulse QA QB QC QD(Data Output)
0 0 0 0 0
1 1 1 0 1
2 0 1 1 0
3 0 0 1 1
4 0 0 0 1

PIPO Shift Register

 Station 3
MEMORY

Memory

A device used to stores program or data on a temporary or

permanent basis for use in digital electronic device . It stores binary
information in groups of bits called words.

ROM
ROM is used for the storing programs that are permanent resident in the computer
and for the tables of constant that do not change in value once the production of
the computer is completed.

 In read only memory (ROM) ,

data are permanently stored by
the manufacturer or user and
data can be read later and the
stored data are not changed
when circuit is of.
  In read and write memory
or random access memory
data can be stored
(written) into the memory
as well as read out.

Time is up! I think you are already geared up.

So…..get your pen and paper in
4…….3……..2……..1…...move!

Can you recognize me?

Write the word counter if the description is about
counter on the space provided before each
number do the same register and memory.

✔
Memory
____________________1. I store data temporarily or permanently.
✔ Register
____________________2. I am a binary storage elements that consist
of flip-flops and gates.
✔
____________________3.
Counter I may be synchronous or asynchronous.
✔
____________________4.
Register I can be a SISO, SIPO ,PISO or PIPO.

✔ ____________________5.
Memory I stores binary information in groups of bits
 From the learning stations you already learned that
counters maybe Asynchronous Counters, Synchronous
Counters, Asynchronous Decade Counters, Synchronous
Decade Counters, Asynchronous Up-Down Counters
Synchronous Up-Down Counters. In asynchronous the flip
flops are not clocked simultaneously while in synchronous
the flip flops are clocked simultaneously. In registers the
data are stored or shift. Furthermore, the input and output
may be both in series or in parallel or series and parallel.
In the case of the memory it may store permanent or
temporary data.

The bit sequence 0010 is serially entered (right-most

bit first) into a 4-bit parallel out shift register that is initially clear. De-
termine the Q outputs after two clock pulses using the hint below.
Can you crack it?

4 1 2 3 0 4 1 3 2 4 0 3
1 number is correct and 2 numbers are correct 1 number is correct and
placed in the wrong and placed in the wrong placed in the right spot
spot. spot.

5 6 2 7 1 0 2 7
Nothing is correct 2 numbers are correct
and placed in the right
spot.
 Using your pen and paper answer the following questions by
choosing the letter of the correct answer.
1. Assume that a 4-bit serial in/serial out shift register is initially clear.
We wish to store the nibble 1100. What will be the 4-bit pattern af-
ter the second clock pulse? (Right-most bit first.)
a. 0011 b. 0000 c. 1111 d. 1100
2. A modulus-16 counter must have ________.
a. 2FF b. 4 FF c. 6 FF d. 10 FF
3. How many flip-flops are required to make a MOD-32 binary
counter?
a. 4FF b. 5 FF c. 6 FF d. 7 FF
4. The terminal count of a modulus-11 binary counter is ________.
a. 0011 b. 0100 c. 1010 d. 1100
5. RAM stands for _________________________.
a. Random Access Memory
b. Read Access Memory
c. Random Assess Memory
d. Random Asset Memory

Direction: Answer the following at your own risk. Use your pen and
your paper.
1. How many different states does a 3-bit asynchronous counter
have? 8
2. A MOD-16 ripple counter is holding the count 10012. What will
the count be after 31 clock pulses? 15536

5 flip flops 3. Using four cascaded counters with a total of 16 bits, how
many states must be deleted to achieve a modulus of 50,000?
4. The group of bits 11001 is serially shifted (right-most bit first) into
a 5-bit parallel output shift register with an initial state 01110.
After three clock pulses, the register contains ________.
00101

5. A serial in/parallel out, 4-bit shift register initially contains all 1s.
The data nibble 0111 is waiting to enter. After four clock
pulses, the register contains ________.
0111
Do the task below.

Draw a diagram of a four-bit asynchronous up counter CLK pulses or wave form.

Complete the table below showing the binary state sequence for BCD
decade counter.

CLK Pulse Q3 Q2 Q1 Q0

Initially 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 0

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 (Recycles) 0 0 0 0

Reflection

Three (3) things I learned from the lesson.

1. 2. 3.

Two (2) interesting facts.

1 2.

One (1) question I still have

1
 I. Chose the letter of the correct answer.
✔
1. A counter circuit is usually constructed of ____________
a. A number of latches connected in cascade form
b. A number of NAND gates connected in cascade form
c. A number of flip-flops connected in cascade
d. A number of NOR gates connected in cascade form

✔ 2. Assume a LOW logic level is placed n the shift/load input of

774195 shift register. The output will change___________.
a. immediately c. on the next clock leading edge
b. if the clock is also low d. depending on the J and K inputs

✔ 3. A type of shift register in which the Q or Q output of one stage is

not connected to the input of the next stage is ________.
A. PISO b. SIPO c. SISO d. PIPO
✔ 4. Match the following sequential Circuits with associated functions
1. Counter -------- A. Storage of Program & data in a digital comput-
er
2. Register -------- B. Generation of timing variables to sequence the
digital system operations
3. Memory --------- C. Design of Sequential Circuits
Codes:
a. 1-A , 2-B , 3-C c. 1-C , 2-A , 3-B
b. 1-B , 2-C , 3-A d. 1-C , 2-B , 3-A
✔
5. The terminal of count of a mod 12 binary-counter is?
a. 1001 b. 1011 c. 1101 d. 1111
II. Answer the following question properly. Show your solution.

✔ 1. How many different states does a 4-bit asynchronous counter

have? 16
✔
2. Using four cascaded counters with a total of 18 bits, how many
states must be deleted to achieve a modulus of 50,000? 212144
 https://www.electronics-tutorials.ws/counter/mod-counters.html

https://www.oreilly.com/library/view/digital-electronics-principles/9780470032145/15-
chapter11.html

https://www.google.com/search?
q=teacher+icon&source=lmns&bih=672&biw=1349&safe=active&hl=fil&ved=2ahUKEwid5oeP6
fjpAhUSTSsKHSJYAXQQ_AUoAHoECAEQAA

https://www.youtube.com/user/nesoacademy

Pre-Assessment Activity Card Activity 1 Guided Activity 1

1. Register 1. registers 1. Memory 1.) 1000
2. D 2. counters 2. Register
3. A 3. memories 3. Counter
4. C 4. Register
5. C 5. Memory
6. A
7. B Assessment 1 Assessment 2
8. B 1. b 1. 8
9. C 2. b 2. 15536
10. A 3. b 3. 5 flip flops
4. c 4. 00101
5. a 5. 0111
Guided Activity 2

Independent Activity 2
Independent Activity 1

Assessment Card
Part I Part II
1. C 4. B 1. 16
2. C 5. B 2. 212144
3. D