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Tutorial 2

The document contains a series of exercises related to combinational logic in computer architecture, including Boolean functions, truth tables, and logic circuit designs. It covers various topics such as multiplexors, adders, encoders, decoders, and overflow detection in binary addition. Additionally, it includes practical design problems for combinational systems and logical equations for controlling devices.

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0% found this document useful (0 votes)
14 views

Tutorial 2

The document contains a series of exercises related to combinational logic in computer architecture, including Boolean functions, truth tables, and logic circuit designs. It covers various topics such as multiplexors, adders, encoders, decoders, and overflow detection in binary addition. Additionally, it includes practical design problems for combinational systems and logical equations for controlling devices.

Uploaded by

yanndjoko1
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 6

COMPUTER ARCHITECTURE

TUTORIAL 2: COMBINATIONAL LOGIC


EXERCISE 1:
1. How many Boolean functions can be defined on n input variables?
2. Consider the function:
̅̅̅̅ ). 𝐵̅
Y = (𝐴𝐵) + (𝐴𝐶
(a) Draw a combinational logic circuit that implements this function.
(b) Draw a truth table for this function.
(c) Write a sum-of-products representation of Y.
(d) Write a product-of-sums representation of Y.
3. Write Y = 𝐴 + (𝐵. ̅ 𝐶)
(a) as a sum-of-products where each product depends on all three variables A; B; C.
(b) as a product-of-sums where each sum depends on all three variables A; B; C.
4. Write a sum-of-products representation of the following

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
5. Write Y = (𝐴 + 𝐵̅ + 𝐶̅ ). (𝐴̅ + 𝐵 + 𝐶̅ ) as a sum-of-products.
6. Write a sum-of-products representation of the output Y of the following circuit, in
terms of the input variables A, B, C. The four gates below are NAND, XOR, OR, and
AND.
Explain how this circuit could be considered as a “read only memory”.

7. Draw a combinational logic circuit of an eight-input multiplexor where the inputs


(D7; D6; D5; D4; D3; D2; D1; D0)
are each one-bit variables. Label the values of inputs and outputs of each gate of the
circuit, assuming the eight inputs have the values (1; 0; 0; 1; 1; 1; 0; 0) respectively,
and assuming D1 is selected. [Do not draw the decoder circuit which is part of the

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COMPUTER ARCHITECTURE

multiplexor. Instead, merely label the inputs and outputs of this decoder as part of
the multiplexor.]
8. Consider the low order four bits of the adder/subtractor circuit shown below. Label
all wires (inputs, outputs) in the circuit by their value (0 or 1), assuming the circuit
is computing A - B where A = 98 and B = -25. [Do not draw the entire circuit. Only
consider the four lowest order bits for this question.]

9. For the circuit in the previous question, give the values of (S3, S2, S1, S0) in the case
that:
(a) A = -25; B = -39; Binvert = 1
(b) A = 25; B = 39; Binvert = 0

10. Draw a combinational logic circuit of a four input multiplexor where the inputs (X3;
X2; X1; X0) are each one bit variables. Label the values of inputs and outputs of each
gate of the circuit, assuming the four inputs have the values (X3; X2; X1; X0) = (1; 0; 0;
1) and assuming X1 is selected. [Do not draw the decoder circuit which is part of the
multiplexor.],
11. An example of an encoder that you should be familiar with is an output device (an
LCD) that displays a digit from f0; 1; :::; 8; 9g. The digit is defined by \turning on" a
subset of the following line segments. For example, when all seven of the line
segments are on, the output digit is 8, whereas when all lines except L2 are turned
on, the output digit is 0.
Suppose that a user chooses a digit by pressing one of ten buttons. Construct a truth
table from which you could build a combinational circuit. (Don’t build the circuit.
Just build the truth table.)

12. If we add two signed numbers using our n-bit adder circuit, then the result might
give an error in the following sense: it could happen that we add two positive
numbers and the result is a negative number, or we add two negative numbers and

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COMPUTER ARCHITECTURE

the result is a positive number, or we subtract a positive number from a negative


number and the result is positive, or we subtract a negative number from a positive
number and the result is negative. In all these cases, the error occurs because the
adder defines addition on a circle, not on the (infinite) set of integers. For example,
suppose n = 8 and consider adding 64 + 64, i.e. 64 = 010000002 in binary.
The result we wish is 128; however, if the result (100000002) is treated as signed
then it is interpreted as -128 (not 128).
Such errors are called overflow. We would like to detect such errors automatically.
Define a binary variable overflow which takes the value 1 when an overflow (error)
occurs and 0 when no overflow occurs (no error). This overflow variable depends
on the four variables Binvert, An-1, Bn-1 and Cn-1.
Fill in the truth table below, showing how overflow depends on the four variables
Binvert, An-1, Bn-1; Sn-1. (Binvert says whether we are doing addition or subtraction.)
Hint: Consider the cases of addition and subtraction separately.

EXERCISE 2:
1. Define combinational logic.
2. Write the design procedure for combinational circuits?
3. What is Half adder?
4. Draw the logic diagram of half adder using NAND gate.
5. What is Full adder? Draw the truth table of full adder.
6. Draw the Logic diagram of full adder.
7. What is Half subtractor?
8. Draw Full adder using Two half adder.
9. What is Full subtractor? Write the truth table of full subtractor.
10. Draw Full subtractor using two half subtractor.
11. What is Parallel Binary Adder (Ripple Carry Adder)?
12. Draw the logic diagram for four bit binary parallel adder.
13. What is 1’s complement of a number?
14. What is 2’s complement of a number?
15. How Subtraction of binary numbers perform using 2’s complement addition?
16. Given the two binary numbers X = 1010100 and Y = 1000011, perform the
subtraction
(a) X - Y and (b) Y - X by using 2’s complements.
17. Draw the logic diagram of Parallel Binary Subtractor.
18. Draw 1:8 Demux using two 1:4 demux.
19. Draw the logic diagram of 2’s complement adder/subtractor.
20. What is Magnitude Comparator?
21. Design a 1-bit Magnitude Comparator.
22. What is Decoder? What are binary decoders?

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COMPUTER ARCHITECTURE

23. Design a 3 to 8 decoder with 2 to 4 decoder.


24. What is Encoder?
25. What is Priority Encoder?
26. Define Multiplexer (MUX) (or) Data Selector.
27. What is De-multiplexer?
28. What is Parity?
29. What is Parity Checker / Generator?
30. What is even parity and odd parity?
31. Give the applications of Demultiplexer.
32. Mention the uses of Demultiplexer.
33. Write the truth table of 2-to-4-line decoder and draw its logic diagram.
EXERCISE 3:
From the statement of the problem, we address the truth table which gives us the value of the
output for each combination of the input variables. The latter are classified according to the binary
code. The expression of the output is directly deduced from the truth table, where the output
function(s) is (are) expressed in the first canonical form. The next step involves simplifying the
result before creating the logic diagram.
1. Design a combinational logic system that performs addition (or subtraction) of two bits, x
and y, and the carry (or borrow) R, based on the state of a control signal M:
• M=0, the circuit performs addition.
• M=1, the circuit performs subtraction.
The outputs of the system are:
• The sum or difference defined by S
• The carry or borrow defined by R1
EXERCISE 4:
Parts of model A and B are stored in reservoirs RA and RB, respectively; must arrive grouped on
a line L. To achieve this, three relays, M, N, and P, are used. Relays M and N respectively bring
parts A and B in front of the cylinder P, which then pushes the assembly on the line L. Contacts
a, b, and c are actuated at the end of the stroke of each cylinder (as shown in the device below).
The operating cycle is as follows:
Closing of a switch I.
1. Advance of M
2. Advance of N
3. Retraction of M
4. Advance of P
5. Retraction of N
6. Retraction of P; and the cycle begins again.
Design such a system.

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COMPUTER ARCHITECTURE

EXERCISE 5:
1. Two binary numbers A and B are each represented using two bits: A1 A0 for A and B1
B0 for B.
Provide a synthesis of a combinational system designed to determine whether: A=B;
A<B, or A>B.
a) Solve this problem considering the system as a 4-input combinational system with 3
outputs S1, S2, and S3.
b) Solve the same problem by determining S1, S2, and S3 from the result of the
subtraction: A-B
2. A reservoir is supplied by two valves, V1 and V2.
There are three levels: Safety (s), Low (l), and High (h).
When the level is below (s), both valves V1 and V2 are opened.
When the level is between (s) and (l), only valve V1 is opened.
When the level is between (l) and (h), only valve V2 is opened.
When the level is detected by (h), both valves are closed.

QUESTION:
Determine the logical equations for opening the two valves, V1 and V2, according to the
level detected by the 3 sensors (s), (b), and (h).
Note: When the level is detected by a sensor, its state is = 1.
3. A beverage dispenser allows delivering to the consumer:

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COMPUTER ARCHITECTURE

- Water
- Grenadine mixed with water
- Mint mixed with water
But it must not allow obtaining:
- Pure grenadine
- Pure mint
- Both grenadine and mint.
The front panel of the dispenser has 3 buttons:
- W (water)
- G (grenadine)
- M (mint)
1) Determine the equation for controlling the opening of the distributor valve.
2) Deduce the corresponding logic diagram.
4. We are interested in an intersection between a main road and a secondary road, for which
we give the operational principle as well as an extract from the functional specifications.
Presence sensors for cars are placed along lanes a and b for the main road, and lanes c
and d for the secondary road. The outputs of these sensors are set to 1 when cars are
detected.

✓ Traffic light F1 is green when there are cars in a and b at the same time.
✓ Traffic light F1 is green when there are cars on either lane a or b and there are no
cars on lanes c or d.
✓ Traffic light F2 is green when there are cars on both lanes c and d, and there are
no cars on lanes a or b.
✓ Traffic light F2 is green when there are cars on either lane c or d, and there are
neither in a nor in b.
✓ Traffic light F1 is green when there are no cars at all.
The variable corresponding to a traffic light is set to 1 when the light is green.
a. Create the truth table that allows translating this problem, with inputs being a,
b, c, and d, and outputs being F1 and F2.
b. Determine the logical equation expressions for F1 and F2 in the form of sum
of products.
c. Graphically simplify the expressions of F1 and F2

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