Advanced Electronics

Week 5

DR. Ahmed EL-Shafeey

 Sequential Statements

The process statement:

Process statement is a concurrent statement but it consist of sequential statement:
example : IF , LOOP , CASE , WAIT , ……………………….
 1. IF Statement

entity nand_2 is
port ( a : in STD_LOGIC; -- NAND gate input 1
b : in STD_LOGIC; -- NAND gate input 2
c : out STD_LOGIC -- NAND gate output );
end nand_2;

architecture Behavioral of nand_2 is

variable temp : bit; -- signal (magnitude and delay) but variable (magnitude only)
begin
p1 : process (a,b) -- to be sequential
begin
temp := not ( a and b ) ; -- for variable := and for signal <=
if ( temp = ´1´ ) then c <= temp after 6 ns;
else c <= temp after 5 ns; -- temp equal zero
end if
end process p1;
end Behavioral;
 2. LOOP Statement

p1 : process (a) -- a is variable

variable int_a : integer;
begin
int_a := a;
for i in 0 to 10 loop
if ( int_a < = 0 ) then
exit;
else int_a = int_a - 1;
Q(i) <= 3.1416 * int_a * int_a ;
end if
end process p1;
 3. CASE Statement

2 to 4 Binary Decoder

A0 A0 A1
A1
entity dec_2_4 is
port ( A : in bit_vector ( 1 downto 0 );
Q : out bit_vector ( 3 downto 0 ) );
end dec_2_4;

architecture Behavioral of dec_2_4 is

begin
p1 : process (A) A0 A0 A1
begin
case A is A1
when ̋ 00 ̋ => Q <= ̋ 1000 ̋ ;
when ̋ 01 ̋ => Q <= ̋ 0100 ̋ ;
when ̋ 10 ̋ => Q <= ̋ 0010 ̋ ;
when ̋ 11 ̋ => Q <= ̋ 0001 ̋ ;
end case;
end process p1;
end Behavioral;
 4. WAIT Statement

1. Wait for time

wait for 10 ns; -- wait for another code

2. Wait until
wait until (x*50 >500); -- wait for certain condition

3. Wait on signal
wait on a,b ; -- wait until a or b changes

4. Multiple wait
wait on a,b until interrupt = 1 for 10 ns; -- combination between 1,2,3
XOR gate in VHDL
AND gate in VHDL
OR gate in VHDL

a
or_out
b
 Design of RS Flip-Flop

R S Q Q’ R
0 0 No change Q
RS_FF
0 1 1 0
Q’
1 0 0 1 S
1 1 Undefined

entity RS_FF is architecture behave_RS of RS_FF is

port (
set , reset : in bit; begin
Q , Qb : inout bit Q <= not ( Qb or reset);
); Qb <= not (Q or set);
end RS_FF ;
end behave_RS;
‫البناء‬
‫التوصيف‬
 Another architecture for RS Flip_Flop

The two internal gates architecture struct_RS of RS_FF is

of the same kind with
two input component nor2
port (
a, b : in bit ;
c : out bit
Define the
);
components
end component ; In the same order (a,b,c)

begin
u1 : nor2 port map (reset, Qb, Q);
u2 : nor2 port map (set, Q, Qb);

end struct_RS;
 Design of a 4-bit shift register

Output
Z1 Z2 Z3
Z0
Q0 Q1 Q2 Q3
Z4

D Q
0 0
1 1
 entity reg is
port (
Input , clk , reset : in bit;
Output : out bit
);
end reg ;
architecture shift_reg of reg is
component dff
port (
d, clk, reset : in bit ; dff0 : dff port map (z(0), clk, rest, z(1));
Q : out bit dff1 : dff port map (z(1), clk, rest, z(2));
); dff2 : dff port map (z(2), clk, rest, z(3));
end component ; dff3 : dff port map (z(3), clk, rest, z(4));

signal Z : std_log_vector (0 to 4);

begin
z(0) <= Input;
G1 : for i in 0 to 3 generate
dffi : dff port map (z(i), clk, rest, z(i+1)); Can be replaced with
end generate;
Output <= z(4);
end shift_reg ;
Design of a single bit Full Adder

A
S
B F.A
C_OUT
C_IN
 VHDL architecture behavior for Full Adder
entity FA1 is
port (
A , B , C_IN : in bit;
S, C_OUT : out bit
);
end FA1 ;
architecture behave_FA1 of FA1 is
begin
S <= A xor B xor C_IN;
C_OUT <= (A and B) or (C_IN and (A xor B));
end behave_FA1 ;
Using karnaugh map:

S = A  B  C_IN

C_OUT = AB + C_IN (A  B)
VHDL architecture structural for Full Adder
X1
architecture struct_FA of FA1 is
component xor
port ( C_IN
a, b : in bit ; X2
c : out bit
); C_OUT
end component ;
component and
port ( X3
a, b : in bit ;
c : out bit
); begin
end component ; u1 : xor port map (A, B, X1);
component or u2 : xor port map (X1, C_IN, S);
port ( u3 : and port map (C_IN, X1, X2);
a, b : in bit ; u4 : and port map (A, B, X3);
c : out bit u5 : or port map (X2, X3, C_OUT);
); end struct_FA ;
end component ;

signal X1, X2, X3 : bit ;

HALF-ADDER behavior in VHDL

a
sum
H.F
carry_out
b
HALF-ADDER structure in VHDL
Full-adder using half-adders and any gate in VHDL

sum s1 sum
a a a sum

b b carry_out b carry_out
s3
carry_in carry_out
s2
4-bit binary adder in VHDL
 Delay model in VHDL

The delay models are:

1. Internal delay

2. Transport delay
Internal delay :
If b is the output signal and a is the input signal

𝑏 <= a after 2 ns; a b

Input output
5 ns 5 ns

0 5 2 7
𝑏 <= a after 10 ns;

Input output
5 ns
No signal

0 5
There is no output signal (zero output) if input signal is less than internal delay
Transport delay :
If b is the output signal and a is the input signal

a b
𝑏 <= a after 2 ns;
Input output
5 ns 5 ns

0 5 2 7

𝑏 <= a after 10 ns;

Input output
5 ns 5 ns

0 5 10 15