BTech_Semester_III_Computer Architecture
BTech_Semester_III_Computer Architecture
Course Introduction
This course provides detail of computer system’s functional components, their characteristics,
performance and interactions including system bus, different types of memory and CPU. This
course also covers the architectural issues such as instruction set program and data types. The
course emphasizes performance and cost analysis, instruction set design, pipelining, memory
technology, memory hierarchy, virtual memory management, and I/O systems
Course Objective:
1. To understand the structure, function and characteristics of computer systems.
2. To understand the design of the various functional units and components of digital computers. To
identify the elements of modern instructions sets and explain their impact on processor design.
3. To explain the function of each element of a memory hierarchy, identify and compare different
methods for computer I/O.
4. To compare simple computer architectures and organizations based on established performance
metrics.
Competencies
The course content should be taught and implemented with the aim to develop different types of
skills so that students are able to acquire following competencies:
1. Apply computer architecture theory to solve the basic functional computer problem.
2. Show and assemble basic computer components.
3. Ability to integrate into working groups involved in analysis and design tasks
Course Learning Outcome:
After completing the course, the student shall be able to :
CO1 Understanding
Identify and explain the basic structure and functional units of a digital
computer
CO2 Understanding
Identify the role and working of various functional units of a computer for
execution of instruction
CO3 Design
Design processing unit using the concepts of ALU and control logic
design.
CO4 Design
Design interfacing of memory and I/O modules with CPU
Course Syllabus:
3
Assembly Language Programming 7
Introduction, Machine Language, Assembly Language Programming:
Arithmetic and logic operations, looping constructs, Subroutines, I-O
Programming.
4 Microprogrammed Control Organization: 3
Control Memory, Address sequencing, Micro program example, Design of
Control Unit
5
Central Processing Unit 5
7 Computer Arithmetic 4
Introduction, Addition and subtraction, Multiplication Algorithms (Booth
Multiplication Algorithm), Division Algorithms, Floating Point Arithmetic
operations,
8 Input-Output Organization 5
Input-Output Interface, Asynchronous Data Transfer, Modes of Transfer,
Priority Interrupt, DMA, Input-Output Processor (IOP), CPU IOP
Communication, Serial communication.
9 Memory Organization 5
Memory Hierarchy, Main Memory, Auxiliary Memory, Associative
Memory, Cache Memory, Virtual Memory, Introduction to GPU.
Total Hours 45
Textbook: -
1. M. Morris Mano, “Computer System Architecture”, Pearson Education
References:
1. Yale N. Patt, Sanjay J. Patel, “Introduction to Computing Systems” McGraw Hill
2. Hamacher, Vranesic, Zaky, “Computer Organization”, McGraw Hill.
3. Andrew S. Tanenbaum and Todd Austin, “Structured Computer Organization”, Pearson
Education
4. N. D. Jotwani, “Computer system organization”, McGraw Hill
5. R.S.Gaonkar, “Microprocessor Architecture, Programming and Applications with 8085A”,
Penram International
6. Douglas Hall, Microprocessors and Interfacing, TMH
TEDx Videos:
Sr Link details Description
No
TD1 https://www.ted.com/talks/kanawat_se How computer memory works. Kanawat
nanan_how_computer_memory_work Senanan In many ways, our memories make us
s?language=en who we are, helping us remember our past, learn
and retain skills, and plan for the future. And for
the computers that often act as extensions of
ourselves, memory plays much the same role.
Other Videos:
O1. https://www.youtube.com/watch?v=bfPV4x
-HrUI
New Golden Age for Computer New Golden
Architecture: Domain-Specific Age for
Hardware/Software Co-Design, Computer
Enhanced Security, Open Architecture
Instruction Sets, and Agile Chip
Development Speaker: John
Hennessy, 2017 Turing Award
Recipient / Chairman, Alphabet
O2. This video explains how the https://www.youtube.com/watch?v=3p8kZp Pipelining
pipelining concept is used to T56lQ introduction
implement various tasks.
O4 https://ocw.mit.edu/courses/electrical-
engineering-and-computer-science/6-172-
Assembly Language & Computer performance-engineering-of-software- Assembly
Architecture systems-fall-2018/lecture-videos/lecture-4- Language &
Prof. Leiserson assembly-language-computer-architecture/ Computer
Stages of code from source code to Architecture
compilation to machine code to
hardware interpretation and, finally,
to execution.
O5 https://www.youtube.com/watch?v=cipkW
LPAsKE
Storage and I/O Interface Storage and I/O
Interface
Prof. Jatindra Kumar Deka
Department of Computer Science
and Engineering, IIT Guwahati.
O6 https://www.youtube.com/watch?v=46dfG0
nW3v4
Cache memory, also called CPU CACHE
memory, is random access memory MEMORY
(RAM) that a computer ANIMATION :
microprocessor can access more Computer
quickly than it can access regular Architecture
RAM. This memory is typically Concepts
integrated directly with the CPU
chip or placed on a separate chip
that has a separate bus interconnect
with the CPU
Related MOOCs courses
M1 Computer Organization and Architecture: A Pedagogical Aspect Dr. Arnab Sarkar
IIT Gowahati by NPTEL
https://onlinecourses.nptel.ac.in/noc21_cs37/preview
M2 Computer Organization and Architecture by Vm Kamkoti by IIT Madras by
NPTEL.
https://nptel.ac.in/courses/106/106/106106166/
M3 Computer Architecture by David Wentzlaff. By Coursera
https://www.coursera.org/learn/comparch?action=enroll
Lab Experiments:
Sr No Title of Experiments
P1 Construct the logical Half and full adder
P2 Construct the Logical Diagram for tri state bus buffers circuit using Logisim
P3 Design the computational circuit for status register
P4 Design computational circuit for Basic traffic Signal
P5 Design a 16 to 1 line multiplexer with 8-to-1-line multiplexers and one 2 to 1 line
multiplexers.
P6 Design the computational circuit for 4bit arithmetic circuit
P7 Design the computational circuit for binary to Hexadecimal Conversion using 7 Segment
Display
P8 Construct the Logical Diagram to perform shift operations using Logisim
P9 Write an assembly language program for performing arithmetic operations
P10 Write an assembly language program to perform subroutine
P11 Write an assembly language and factorial of number
P12 Write an assembly language to sum of even numbers
P13 Write a program to calculate the sum of series of number