HSE4A01 –

Logic & Analog

Circuits
Digital meets Analog
 Course Outline
High Speed Digital
Electronics

Power
Background PCB Tracks TX-line Measurement & Delivery
Introduction Links Probing System
(PDS)

TX-line Probe Non-ideal

Analog Circuits
Basics Loading Components

Logic Circuits Tracks as Measurement

Decoupling
& Families TX-lines Errors

Digital Signals PCB

Reflections
(Time & Freq) Stacking

Termination
 Review of Analog Circuits
 Horowitz & Hill – Art of Electronics (2nd Ed.):
⚫ 1.03 Voltage Dividers
⚫ 1.04 Voltage & Current Sources
⚫ 1.05 Thevenin Equivalent Circuit
⚫ 1.07 Sinusoidal Signals
⚫ 1.08 Signal Amplitudes and Decibels
⚫ 1.09 Other Signals
⚫ 1.10 Logic Levels
⚫ 1.12 Capacitors
Review of Analog Circuits (cont.)
 Horowitz & Hill – Art of Electronics (2nd Ed.):
⚫ 1.13 RC Circuits
⚫ 1.14 Differentiators
⚫ 1.15 Integrators
⚫ 1.18 Frequency Analysis of Reactive Circuits
⚫ 1.19 RC Filters
⚫ 1.22 Resonant Circuits
 Voltage Divider
 Horowitz & Hill: Chapter 1.03

Z2
Z1 vout = vin
+ Z1 + Z 2

vin
+
If Z1  Z 2 then vout  vin
−
Z2 vout
otherwise vout  vin
−
 Source Impedance
 Concept & Examples of source impedance
⚫ RF Circuits
⚫ All PSU’s
⚫ Regulation & Trafos
⚫ Power systems
⚫ House wiring
 Thévenin Equivalent
 Horowitz & Hill: Chapter 1.05

+ + vout Z eq = ZTh
+ − + +
− Z eq
vTh vout
− −
−

Open Circuit : vTh = vout

vTh
Short Circuit : I =
Z Th
Thévenin
 Signals - Sinusoidal
 RMS of a Sinusoid
 2 Only valid for sinus
 Physical meaning
⚫ power transferred
⚫ Comparison with DC
 Decibels
 Reason for (orders of magnitude)
 Uses:
⚫ Gain (Transfer function)
⚫ Power levels
⚫ Amplitudes
 Other Signals
 RMS of v(t):

1 T 2
VRMS = 
T 0
v (t ) dt
 Capacitance
 Time Domain
⚫ Formula
⚫ Graphic Representation
Capacitance (RC)
 Capacitance
 Frequency Domain
⚫ Formula
⚫ Graphic Representation
Example: Decoupling Capacitors
= Ideal capacitor 1 nF:
ZC () SMD ceramic
0 V - +ve plane
10
10 nF
5 SMD:
2 Polyester
1 Ceramic
0,5 100 pF
0,2 SMD
0,1 100 nF SMD ceramic
0,05 ceramic:
12 mm tracks
No tracks

0,1 0,3 1 3 10 30 100 300 1 000 MHz

 Digital Signal & RC Circuits
R

C ?

 Understand (J & G Chpt 1.6):

⚫ Effect of RC circuit on logic signals
⚫ Measurement of C by using time delay
Digital Signal & RC Circuits
Low Pass Filter
LT-Spice Simulation
Low f Input
High f Input
Low Pass Filter – Bode Plot
Parallel Resonance
Series Resonance
Logic Circuits
Getting Signal from A to B
Logic
Gate 2

Logic
Track
Gate 1

PCB
 Signal Integrity
 SI is the ability of high frequency digital
electronics to operate reliably and efficiently
(with integrity)

 Without SI:
⚫ Unreliable operation of digital electronics
⚫ High power consumption and demand on
Power Delivery System (PDS)
⚫ High Electromagnetic Interference (EMI)
 SI Time Simulation
8 1.50E-01

7 Probe V 1 1.00E-05
Probe V 2 1.04E-05
Probe I 1 DC 1.00E-01
6

5
5.00E-02
Driver and Gate Voltage (V)

Line Current (mA)

4

3 0.00E+00

-5.00E-02
1

0
-1.00E-01

-1

-2 -1.50E-01
0.0E+00 5.0E-09 1.0E-08 1.5E-08 2.0E-08 2.5E-08 3.0E-08 3.5E-08 4.0E-08 4.5E-08 5.0E-08
Time (sec)
CMOS AND Gate
TTL NAND Gate
CMOS Output Model
Logic Families
Logic Thresholds (Hysteresis)

From Texas Instrument Application Note: SZZA036B

Logic Threshold (Hysteresis)
?

From Texas Instrument Application Note: SZZA036B

Logic Gates - Thresholds
 Example: Time Delay Circuit

DGND

 This is a “Time Delay” Logic Circuit

Time Delay Circuit
HSE4A01 –
Logic Signals
Time vs. Frequency Domain
Fourier Analysis
Frequency Spectrum of a Pulse
Spectrum of a Pulsed Periodic
Signal
 BW – Rise & Fall Time
90%
1
BW=
π tedge
10% 0.5
Johnson & Graham: Fknee =
T10% −90%

t edge
 EMI Scan – 12MHz Clock
ITC SERVICES
RE02 NAVY AND AIR FORCE INTERNAL EMC-30 SETTINGS SPECS
Date : 11/21/03 Time : 13:40:56.85 Detector Peak 1) SAAB RE102 Zone SICO.
Technician : Hans Test Equip. : CCS 130 MK IV Bandwidth Per Band 2) SAAB RE102 Zone ICO.
Test Method : MIL STD 462 Test Number : 1 Dwell 20 msec.
Equipment : Sensor Loc. : 1m RF Atten. 0 dB
Mode of Op. : power on Sensor Pol. : v/h/c IF Atten. 0 dB DATA FILE : 12MHZ1.D31
Serial No. : Ext. Atten. : 0 dB
Comment : Graph RE1` 12 MHz x-tal
120 ANTENNA
FILES
110 RVA30-2K.A30
100 BIA30-2K.A30
LCA30-2K.A30
90
dBuV/m

80
70
1.
60
50 OTHER
*2. FACTORS
40
Amplitude

30
20
10
0
-10
-20
-30
-40
E-M
-50
10. 100.
2.000 Frequency MHz 797.750
 Choice of Logic Family
 Does fastest, always = best?
Logic Family Rise Time ns Bandwidth
Old CMOS 50 ns 6 MHz
TTL/BiCMOS 10 ns 32 MHz
LS-TTL 6 ns 55 MHz
HC CMOS 4,0 ns 80 MHz
STTL/ABT-TTL/ALS-TTL 3,0 ns 120 MHz
FACT CMOS/FAST TTL 2,0 ns 160 MHz
ECL 10kH 1,0 ns 315 MHz
ECL 100k 0,7 ns 455 MHz
ECLinPS3 0,5 ns 635 MHz
E-LITE ECL 0,25 ns 1200 MHz
GaAs 0,2 ns 1600 MHz
Lightning and ESD Bandwidth
Lightning ESD
 Is typically a sec event  Is typically a nsec event

 Typical BW: 300kHz  Typical BW: 300MHz

 Treat as a Conductive  Treat as a Radiated
Immunity threat Immunity threat
 Low Pass Filter & Bandwidth
Filtered
Unfiltered Signal
Signal
Low Pass
Filter
(LPF)
BW = f-3dB
f f
Signal Signal BW f-3dB
BW decreased

Unfiltered Filtered
Digital Signal Digital Signal
Low Pass
Filter
(LPF)
BW = f-3dB
t t
Fast Rise & Fall Edge time
Time increased
 Bottom Line

 Fast Rise/Fall Time => High Freq Components

 Filtered Signal => Rise/Fall Time of Lowest

Bandwidth (Signal or Filter)
 Textbook References
 Johnson & Graham – High Speed Digital
Design ( A Handbook of Black Magic)
⚫ 1.1. Frequency and Time
• Rise & Fall Time
• Knee Frequency
• Spectral Density of Digital Waveform

 Horowitz & Hill – Art of Electronics (2nd Ed.):

⚫ 1.19 RC Filters