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Lecture 6

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17 views26 pages

Lecture 6

Uploaded by

basusuryadipto803
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Electronics and µ-processors

(EC2L006)

Gate-Level minimization
Learning Objectives
• NAND & NOR implementation

• AND-OR-INVERT implementation

• OR-AND-INVERT implementation

• Exclusive-OR function

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 2


Nand and Nor implementation
• Nand and Nor gates are easier to fabricate with electronic
components and are the basic gates used in all IC digital logic
families.
• Universal gates---any logic circuit can be implemented with it.

• NAND Circuits
• A convenient way to implement a Boolean function with NAND
gates is to obtain the simplified Boolean function in terms of
Boolean operators and then convert the function to NAND logic.

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 3


Logic operations with NAND gates

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 4


Alternate Symbols

Two graphic symbols for a three-input NAND gate

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 5


Two Level Implementation
• The implementation of Boolean functions with NAND gates
requires that the functions be in sum-of-products form.

Three ways to implement F = AB + CD


[Atri Mukhopadhyay] | [SECS] | [EC2L006] 6
Example 20:
• Implement the following function with NAND gates.
F(x, y, z) = Σ(1, 2, 3, 4, 5, 7)

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 7


Multilevel NAND Circuits

• Implement F = (AB′ + A′B) (C + D′)

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 8


NOR implementation
• The NOR operation is the dual of the NAND operation.
• All procedures and rules for NOR logic are the duals of the
corresponding procedures and rules developed for NAND logic.

Logic operations with NOR gates


[Atri Mukhopadhyay] | [SECS] | [EC2L006] 9
Alternate Graphic Symbols for NOR gate

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 10


NOR implementation
• Implement F =(A+B)(C+D)E using NOR gates.

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 11


Multilevel NOR circuits
• Implement F = (AB′ + A′B)(C + D′) with NOR gates.

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 12


Other Two-Level Implementations
• Nondegenerate forms produce an implementation in sum-of-
products form or products-of-sums form.

• AND-OR OR-AND
• NAND-NAND NOR-NOR
• NOR-OR NAND-AND
• OR-AND AND-NOR

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 13


AND-OR-INVERT Implementation

• Implement F = (AB + CD + E)’

• The two forms, NAND-AND and AND-NOR, are equivalent.


Both perform the AND-OR-INVERT function.

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 14


OR-AND-INVERT Implementation

• Implement F = [(A + B)(C + D)E]′

• The OR-NAND and NOR-OR forms perform the OR-AND-


INVERT function.

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 15


Example 21:
• Implement the function in the given K-map using a) AND-
NOR, b) NAND-AND, c) OR-NAND, and d) NOR-OR.

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 16


Solution 21:

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 17


Exclusive-OR Function
• The exclusive-OR function, denoted by symbol , is a logical
operation that performs the following Boolean operation:
x y = xy’+x’y
• The following identities apply to the exclusive-OR operation:
• x⊕0=x
• x 1 = x’
• x x =0
• x x’ = 1
• x y’ = x’ y = (x y)’
• The exclusive-OR operation is both commutative and
associative; that is,
A B=B A
(A B) C=A (B C) = A B C

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 18


Exclusive-OR implementations

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 19


Odd Function
• A function where odd number of variables are equal to 1.

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 20


Logic diagram of odd and even functions
• In general, an n-variable exclusive-OR function is an odd
function defined as the logical sum of the 2n/2 min-terms
whose binary numerical values have an odd number of 1’s.

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 21


Parity Generation and Checking
• A parity bit is an extra bit included with a binary message to
make the number of 1’s either odd or even.

• The message, including parity bit is, is transmitted and then


checked at the receiving end for errors.

• An error is detected if the checked parity does not correspond


with the one transmitted.

• The circuit that generates the parity bit in the transmitter is


called a parity generator. The circuit that checks the parity in
the receiver is called a parity checker.

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 22


Even Parity Generator

• P=x y z
[Atri Mukhopadhyay] | [SECS] | [EC2L006] 23
Even-Parity-Checker Truth Table

• C=x y z P
[Atri Mukhopadhyay] | [SECS] | [EC2L006] 24
Logic diagram of a Parity Generator and Checker

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 25


Other Minimization Methods
• Tabulation Method
• Quine-McCluskey Method

[Atri Mukhopadhyay] | [SECS] | [EC2L006] 26


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