MODIFICATION OF VITERBI DECODER FOR HIGH SPEED

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CHAPTER 1

INTRODUCTION

1.1 Introduction to Viterbi Decoder:

The use of convolution encoder with probabilistic decoding can significantly improve
the error performance of a communication system. The Viterbi algorithm , which is widely
used decoding algorithms, is optimal, but its complexity in both number of computations and
memory requirement exponentially increases with the constraint length k of the code. Hence
when the codes with a longer constraint length are required in order to achieve a low error
probability, decoding algorithms whose complexity does not depend on k becomes
attractive.Several multiple paths, Breath first decoding algorithms, such as M-algorithm,
Simmon’s algorithm have been proposed to the alternatives of the Viterbi algorithm .
Unfortunately, with these algorithms, should the correct path be lost, then its recovery is
rather difficult, leading to very long error events.

The error propagation is usually contained by organizing the data in frames or blocks
with a known starting state or by using some special recovery schemes . Trellis coded
modulation schemes are used in many bandwidth efficient systems. Typically, a TCM uses
convolutional code, which leads to high complexity of the viterbi decoder for the TCM
decoder, even if the constraint length of the convolutional code is moderate. For example, the
rate ¾ convolutional code used in a TCM system, has constraint length of having the
computational complexity is equivalent that of a VD for a rate ½ convolutional code with a
constraint length of 9 due to the large number of transitions in the trellis .

So, in terms of power consumption, the viterbi decoder is a dominant module in a TCM
decoder. General solutions for low power viterbi decoder design have been studied by
existing work. Power reduction in VD s could be achieved by reducing the number of states or
by over scaling the supply voltage. Over scaling of the supply voltage usually needs to take
into the whole consideration the whole system that includes includes the VD, at which we are
focusing at our research. T-algorithm has been shown to be very efficient in reducing the
power consumption.

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However searching for the optimal PM in the feedback loop still reduces the decoding
speed. To overcome this drawback, two variations of the T-algorithm have been proposed, the
relaxed adaptive viterbi decoder , which suggests using an estimated optimal PM, instead of
finding the real one each cycle and the limited search parallel state VD based on scarce
transition (SST) . When applied to the high rate convolution codes the relaxed adaptive viterbi
decoder suffers a severe degradation of bit-error-rate performance due to inherent drifting
error between the estimated optimal PM and the accurate one

On the other side, the SST based scheme requires predecoding and reencoding process
and is not suitable for TCM decoders. Here we propose an add-compare-select unit (ACSU)
for VDs incorporating T-algorithm for a rate ½ code, which will decrease the power
efficiently. A systematic way is shown to analyze and to achieve the theoretical iteration
bound. We discuss low power viterbi decoder design for the rate ½ code. Finally, simulation
results of convolutional encoder and the VD have been reported.

1.2 Existing system:

The Viterbi algorithm is commonly used in a wide range of communications and

data storage applications. It is used for decoding convolutional codes, in baseband detection
for wireless systems, and also for detection of recorded data in magnetic disk drives. The
requirements for the Viterbi decoder or Viterbi detector, which is a processor that implements
the Viterbi algorithm, depend on the applications where they are used. This results in very
wide range of required data throughputs and power or area requirements. Viterbi detectors are
used in cellular telephones with low data rates, of the order below 1Mb/s but with very low
energy dissipation requirement.
They are used for trellis code demodulation in telephone line modems, where the
throughput is in the range of tens of kb/s, with restrictive limits in power dissipation and the
area/cost of the chip. On the opposite end, very high speed Viterbi detectors are used in
magnetic disk drive read channels, with throughputs over 600Mb/s. But at these high speeds,
area and power are still limited.The Viterbi algorithm is commonly expressed in terms of a
trellis diagram, which is a time indexed version of a state diagram. The simplest 2-state trellis
is shown in Figure 1.1.

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The maximum likelihood detection of a digital stream with inter-symbol

interference can be described as finding the most-probable path through a trellis of state
transitions (branches). Each state corresponds to a possible pattern of recently received data
bits and each branch of the trellis corresponds to the reception of the next (noisy) input.

Figure.1.1 Two state trellis

The branch metrics represents the cost of traversing along a specific branch, as
indicated in Figure 1.2. Under additive white Gaussian noise (AWGN conditions), it equals
the squared difference between the received sample r, and the corresponding equalization
target value tk: bmk = (r – tk)2 .
The state metrics, or path metrics, accumulate the minimum cost of ‘arriving’ into
a specific state. The algorithm states are updated using an add-compare-select recursion. The
branch metrics are added to the state metrics of the previous time instant. The smaller one of
the two is selected to be the new state metric for each state, as illustrated in Figure 1.2.Finally
,after all the input data is processed, the minimum state represents the survivor sequence
Tracing backwards we can then find the likely sequence of transmitted data.
Implementation of Viterbi Decoder:
The implementation of the Viterbi decoder, a processor that implements the
Viterbi algorithm, consists of three major blocks: the branch metrics calculation unit (BMU),
the add- compare-select unit (ACS), and the survivor path decoding unitA typical viterbi
decoder block diagram is shown in fig 1.2. First branch metrics (BMs) are calculated in the
BMunit (BMU) from the received symbols. In a TCM decoder, this module is replaced by
transition metric unit (TMU), which is more complex than BMU.

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Then BMs are fed into the ACSU that recursively computes PMs and output
decision bits for each possible state transition. After that the decision bits are stored in and
retrieved from the SMU in order to decode the source bits along the final survivor path. T-
algorithm requires extra computation in the ACSU loop for calculating optimal PM. So It
automatically reduce the decoding speed.

Figure.1.2 Exsisting System Of Viterbi Decoder

For the decoding of convolutional codes we can observe two types soft decision decoding and
hard decision decoding. Soft decision decoding is much complex at which we are not
concentrating at our research.

1.3 Limitations of Existing system:

The Viterbi decoder, which implements the Viterbi algorithm for decoding
convolutional codes, is widely used in digital communication systems. However, despite its
advantages in error correction, it has several limitations that impact its performance,
efficiency, and applicability in different scenarios.
Limitations of the Viterbi Decoder with the Viterbi Algorithm
1. Computational Complexity
The Viterbi algorithm requires an exponential amount of processing power as the
constraint length of the convolutional code increases. The number of states in the trellis
diagram grows exponentially with the constraint length , specifically as . This results in higher
memory requirements and computational overhead, making it inefficient for decoding codes
with large constraint lengths.

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2. Memory Requirements
Since the algorithm maintains a trellis structure and stores path metrics for each
state, the memory usage can become excessive, especially for long constraint lengths. The
need to store survivor paths for traceback operations further increases memory demands. In
resource- constrained environments, such as embedded systems or low-power devices, this
limitation becomes a critical concern.
3. Latency Issues
The Viterbi decoder introduces significant latency due to the need to process the
entire trellis before making final decoding decisions. This is particularly problematic for real-
time applications such as high-speed wireless communication, video streaming, and satellite
communications, where low-latency decoding is essential. The traceback operation further
adds to the delay, making it unsuitable for time-sensitive applications.
4. Power Consumption
High computational complexity and memory usage directly impact power
consumption. The Viterbi decoder continuously updates path metrics, survivor paths, and
performs traceback operations, leading to increased energy consumption. This is a significant
drawback in battery-operated devices such as mobile phones, IoT devices, and satellites,
where energy efficiency is a priority.
5. Performance Degradation for Noisy Channels
While the Viterbi algorithm is an optimal Maximum Likelihood Sequence
Estimation (MLSE) decoder, its performance degrades in highly noisy environments. In
channels with severe interference, fading, or burst errors, the decoded sequence may suffer
from error propagation, reducing the effectiveness of the decoder. Techniques like soft-
decision decoding help improve performance but further increase computational complexity.
6. Inflexibility in Handling Varying Code Rates
The standard Viterbi decoder is optimized for a fixed convolutional code rate. If
the system requires adaptive coding rates to handle dynamic channel conditions, a separate
decoder or additional modifications like puncturing and depuncturing are needed. This
increases system complexity and requires additional processing steps.
7. Limited Suitability for High-Rate Codes
For high-rate convolutional codes, the number of states increases significantly,
making the Viterbi algorithm computationally expensive. Alternative decoding
approaches,such as the Turbo decoder or LDPC decoder, become more efficient for such
sens.
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8. Trade-off Between Accuracy and Complexity

While the Viterbi algorithm provides maximum likelihood decoding, it does so at
the cost of high computational complexity. In practical systems, suboptimal algorithms like
the T-algorithm or List Viterbi Algorithm (LVA) are sometimes used to reduce complexity,
but they introduce approximation errors that can degrade performance.
9. Implementation Challenges in Hardware
Hardware implementation of the Viterbi decoder requires dedicated circuitry for state metric
updates, path storage, and traceback operations. As the constraint length increases, FPGA or
ASIC implementations become challenging due to increased logic complexity, power
consumption, and routing congestion.
10. Scaling Issues in Modern Communication Systems
Modern communication standards like 5G and satellite communications require high-
throughput, low-latency error correction. The Viterbi decoder, while effective in traditional
applications, struggles to scale efficiently for such demanding environments. LDPC and
Turbo codes have largely replaced Viterbi decoding in these applications due to their better
performance and scalability.

1.4 LITERATURE SURVEY:

In 1949 Shannon published a landmark paper on reliability of communication in
noisy environment. He established that, under some conditions and using proper coding, it is
possible to have a highly reliable communication even in the presence of noise. A nice
account of encoding and decoding techniques is presented in [3]. In 1967, AJ Viterbi
proposed an algorithm to optimally decode convolutional codes [1]. A mathematical
description of the algorithm, its performance and implementation issues are addressed in a
tutorial by Forney in [4]. Omura [5] established that the algorithm is equivalent to the
dynamic programming solution to the problem of finding the shortest path through a
weighted graph. In 1970s practical applications of coding theory started appearing. A vivid
account of performance aspects of Viterbi Algorithm (VA) is presented in [2]. In the same
paper, the implementation issues in VA have also been addressed.

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A detailed account of implementation of the VA is presented in [9]. Architecture

and implementation of 140 Mbps Radix-4 viterbi decoder has been described in [14]. An area
efficient technique for path metric update and storage has been proposed in [6]. A general
method of partitioning and scheduling of N states into P Add-Compare-Select (ACS) units
has also been proposed. Its implementation examples are discussed in [7]. In [8] a
systematic method of partitioning, scheduling and mapping of states (N) into ACS (P) has
been discussed. The architecture has a fixed global routing. It works on the trellis
corresponding to an encoder where incoming bits form the least significant bits of the register
and the older bits are shifted. Partitioning, scheduling and mapping are done in such a way
that the data can be rearranged so that their position corresponds to perfect shuffle over the
index of the data item.
In [10] a two's complement method to confine the range of the path metrics is
described as an alternative to metric rescaling. Low latency, high throughput Viterbi Decoder
(VD) design is presented in [11]. It uses a K-nested layered look-ahead method, which
combines K-trellis steps into one trellis step (where K is the encoder constraint length). The
design has a lower latency for a given level of parallelism. Area penalty in this design is high.
In [15] a combined design effort for high throughput and low latency is presented. The
design has been optimized from architectural down to physical level. Physical design oriented
implementation of macro blocks has been done for better area utilization. This is in contrast
to standard cell design methodology. Regarding survivor sequence update and storage, [12]
and
[13] describe the conventional trace back technique. Hybrid survivor path architectures for
viterbi decoders have been described in [14]. The hybrid architectures combine register
exchange and traceback techniques. Hybrid pre-traceback is used to reduce the memory
access frequency while hybrid trace forward is used to avoid traceback operation. In [16] the
use of trace forward unit has been demonstrated.

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CHAPTER 2

PROPOSED SYSTEM

2.1 BLOCK DIAGRAM:

In this project we propose an architecture for viterbi decoder with T-algorithm which can
effectively reduce the power consumption with a negligible decrease in speed.Implementation
result is for code rate ½ with constraint length 9 used for trellis coded modulation. This
architecture reduces the power up to 64% without any performance loss when compared with
the ideal viterbi decoder, while the degradation in the clock speed is negligible.Viterbi
decoder with T-algorithm.The viterbi decoder with T–algorithm is shown in the figure 2.1. As
compared with the Ideal viterbi decoder here we will have the extra computation like
Threshold generator and purge unit. We will modify the path of ACSU by the extra
computation of threshold generator and purge unit as shown in the figure 2.1. By using the
Threshold generator the number of computations will decrease, by that the power
consumption of entire system will decrease. The theoretical iteration bound also we will
get.The rate ½ convolutional code employed in TCM system.

Figure: 2.1 Viterbi decoder with T-algorithm

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Preliminary bit error rate(BER) have been discussed . Estimated BER performance of the
VD employing T-algorithm with different values of T over an additive Gaussian noise
channel The simulation is based on TCM employing the rate 1/2 code. Compared to the ideal
viterbi algorithm, the threshold ‘Tpm’ can be lowered to 0.3 with less than 0.1 db
performance loss. The functional block diagram of the VD with T-algorithm is shown in
fig. 3.B.16. The minimum value of each BM group (BMG) can be calculated in BMU or
TMU and then a passed to the ‘Threshold Generator’ unit (TGU) to calculate (PMopt+T).
(PMopt+T) and the new PMs are then compared in the ‘purge unit’ (PU). The 64 states and
PMs are labeled from 0 to
63. The precomputation steps is expressed as…
PMopt= min[min{min(cluster0(n-2))+min(BMG0(n-1)),
min(cluster1(n-2))+min(BMG1(n-1)),
min(cluster2(n-2))+min(BMG3(n-1))
min(cluster3(n-2))+min(BMG2(n-1))}+min(even BMs(n),
min{min(cluser0(n-2))+min(BMG1(n-1))
min(cluster1(n-2)+min(BMG0(n-1))
min(cluster2(n-2))+min(BMG2(n-1)),
min(cluster3(n-2))+min(BMG3(n-1))}+min(oddBMs(n))]
We can obtain (PMopt+T) during the period when ACSU updates for new PMs. The only extra
calculation for T-algorithm is the comparison between the (PMopt+T) and all the PMs.
Therefore the critical path is greatly shortened as the eq.

TT-algo=Tadder+T4-in_comp+2T2in_comp

2.2 Details of Block Diagram

Encoder Output:

Function: This block represents the sequence of encoded symbols generated by the
Convolutional Encoder. The encoder takes the original data bits and adds redundancy
according to the defined code rate and constraint length. This output is the direct input to the
Viterbi decoder, replacing the channel symbols that would be present in a system with a
noisy channel. It is assumed the data is being sent through a channel that is noisy, and the
decoder is receiving the corrupted data.

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BMU (Branch Metric Unit):

Function: The BMU calculates the branch metrics. It compares the Convolution Encoder
Output (which is now the received, potentially corrupted, encoded data) with the expected
encoded symbols for each possible transition in the convolutional code's trellis diagram. This
comparison determines the "distance" or "dissimilarity" between the received encoded data
and the ideal encoded data, quantifying the likelihood of each transition.
ACSU (Add-Compare-Select Unit):
Function: The ACSU is the core processing unit of the Viterbi decoder. For each state in the
trellis, it:
* Add: Adds the branch metrics (calculated by the BMU) to the Path Metrics (PMs) of the
incoming paths.
* Compare: Compares the resulting path metrics for each state.
* Select: Selects the path with the most favorable (highest or lowest, depending on the
metric) path metric as the survivor path.
* Note: The T-algorithm's implementation, involving the Threshold Generator and Purge
Unit, modifies the ACSU's operation.
Threshold Generator:
Function: This unit dynamically generates a threshold value (T) based on the current path
metrics. This threshold is used by the Purge Unit to prune unlikely paths. The threshold is
calculated in a way to optimize the balance between performance and power consumption.
Purge Unit:
Function: The Purge Unit compares the path metrics with the threshold generated by the
Threshold Generator. Paths whose metrics fall below the threshold are considered less likely
and are eliminated from further consideration. This reduces the number of paths the ACSU
needs to process, thereby reducing computational load and power consumption.
PMs (n-1):
Function: These are the Path Metrics from the previous stage of the trellis. They represent the
accumulated "cost" or "likelihood" of reaching each state at the previous time step.
PMs (n):
Function: These are the updated Path Metrics after the ACSU operation. They represent the
accumulated cost/likelihood of reaching each state at the current time step.

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PMU (Path Metric Unit):

Function: The PMU stores and manages the Path Metrics. It may also perform normalization
or other operations to maintain the dynamic range of the metrics.
SMU (Survivor Management Unit):
Function: The SMU stores the survivor paths selected by the ACSU. These paths represent
the most likely sequence of states through the trellis, based on the received encoded data.
Decision Bits:
Function: Based on the survivor paths stored in the SMU, the Decision Bits block makes
decisions about the transmitted data bits. This involves tracing back through the survivor path
to determine the most likely sequence of input bits.
Decoded Output:
Function: This is the final output of the Viterbi decoder, representing the estimated
transmitted data bits after error correction.
2.3 Theoritical Iteration Bound and Equations:

The T-algorithm is also the iteration bond we can get for viterbi decoder when T-
algorithm is employed. The functional block of Fig. 16 is slightly different from the Fig. 14,
where the minimum BM is sent to the PPAU from the BMU. Since the estimated optimal PM
calculated in each cycle, an accurate an optimal PM is also needed every 6 to 7 cycles to
compensate for the estimated one. For example, at time slot n, the decoder memorizes
PMopt_esti(n) and PMs(n). After 7 cycles, PMopt_accu(n)- PMopt_esti(n) is added to
PMopt_esti(n+7). The problem with this compensation scheme is that the error between
PMopt_esti and PMopt_accu accumulates over at least 7-cycles due to the inherent delay of
the scheme itself.

The Branch metric can be calculated by two types: Hamming distance and Euclidean
distance . Consider a VD for a convoluional code with a constraint length k, where each state
receives p candidate paths. First, we expand Ps at the current time slot n(Ps(n)) as a function
of Ps(n-1)to form a look-ahead computation of the optimal P-Popt (n). If branch metrics are
calculated based on the Euclidean distance, popt(n) is the minimum value of Ps(n) can be get
as
popt(n) =min{p0(n),p1(n),……..p2-1k(n)} (1)
=min{min[p0,0(n-1)+B0,0(n),p0,1(n-1)+B0,1(n)………., p0,p(n-1)+B0,p(n)],
Min[p1,0(n-1)+B1,0(n),p1,1(n-1)+B1,1(n),……,p1,p(n-1) +B1,p(n)],...........,

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Min[p2k-1-1,0(n-1)+B2k-1-1,0(n),P2k-1-1,1(n-1)+B2k-1-1,1(n),…..,P2k-1-1,p (n-1) +B2k-1- 1,p(n)]}

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=min{P0,0(n-1)+B0,0(n),
P0,1(n-1)+B0,1(n),…….,
P0,p(n-1)+B0,p(n),
P1,0(n-1)+B1,0(n),
P1,1(n-1)+B1,1(n),…..,
P1,p(n-1)+B1,p(n),…….,
P2k-1-1,0(n-1)+B2k-1-1,0(n),
P2k-1-1,1(n-1)+B2k-1-1,1(n),……,
P2k-1-1,p(n-1)+B2k-1-1,p(n)}. (2)
Now, we group the states into several clusters to reduce the computational overhead caused by
look-ahead computation. The trellis butterflies for a VD usually have a symmetric structure. In
other words, the states can be grouped into m clusters, where all the clusters have the same number
of states and all the states in the same cluster will be extended by the same Bs. Thus (3) can be
rewritten as
Popt=min{min(Ps(n-1)in cluster 1) (3)
+min(Bs(n) for cluster
1), Min(Ps(n-1) in cluster
2)
+min(Bs(n) for cluster 2), ……… ,
Min(Ps(n-1) in cluster m)
+min(Bs(n) for cluster m)}. (4)
The minimum (Bs) for each cluster can be easily obtained from the BMU or TMU and
min(Ps) at time n-1 in each cluster can be precalculated at the same time when the ACSU is
updating the new Ps for time n. Theoretically, when we continuously decompose Ps(n-1),
Ps(n- 2),……, the precomputation scheme can be extended to Q steps. Where q is any
positive integer that is less than n. Hence Popt(n) can be calculated directly from Ps(n-q) in q
cycles. through a design example that, q -step pre-computation can be pipelined into q stages,
where the logic delay of each stage is continuously reduced as q increases. As a result, the de-
coding speed of the low-power VD is greatly improved. However, after reaching a certain
number of steps, qb, further precomputation would not result in additional benefits because of
the inherent iteration bound of the ACSU loop. Therefore, it is worth to discuss the optimal
number of precomputation steps.
In a TCM system, the convolutional code usually has a coding rate of R/(R+1) , so that in
(3), p=2R and the logic delay of the ACSU is TACSU=Taddder+Tp-in_comp, where Tadder is the
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logic delay of the adder to compute Ps of each candidate path that reaches the same state
and Tp-

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in_comp is the logic delay of a p-input comparator to determine the survivor path(the path
with the minimum metric) for each state. If T-algorithm is employed in the VD, the iteration
bound is slightly longer than TACSU because there will be another two input comparator in the
loop to compare the new Ps with a threshold value obtained from the optimal Path metric and
preset T as shown in (4)
Tbound=Tadder+Tp_in_comp+T2-in_comp. (5)
To achieve the iteration bound expressed in(5), for the precomputation in each
pipelining stage, we limit the comparison to be among only p 0r 2p metrics. To simplify our
evaluation , we assume that each stage reduces the number of the metrics to 1/p(or2-R) of its
input metrics meeting the theoretical iteration bound should satisfy (2R)qb ≥ 2k-1. Therefore
qb≥ (k-1)/R and qb is expressed as (6), with a ceiling function.

In the design example , with a coding rate of ¾ and constraint length of 7, the minimum
precomputation steps for the VD to meet the iteration bound is 2 according to (4). It is the
same value as we obtained from direct architecture design . In some cases, the number of
remaining metrics may slightly expand during a certain pipeline stage after addition with Bs.
Usually, the extra delay can be absorbed by an optimized architecture or circuit design. Even
if the extra delay is hard to eliminate, the resultant clock speed is very close to the theoretical
bound. To fully achieve the iteration bound, we could add another pipeline stage, though it is
very costly.
Computational overhead (compared with conventional T-algorithm) is an important
factor that should be carefully evaluated. Most of the computational overhead comes from
adding Bs to the metrics at each stage as indicated in (4). In other words, If there are m
remaining metrics after comparison in a stage, the computational overhead from this stage is
at least m addition operations. The exact overhead varies from case to case based on the
convolutional code’s trellis diagram. Again, to simplify the evaluation, we consider, a code
with a constraint length k and q precomputation steps. Also, we assume that each remaining
metric would cause a computational overhead of one addition operation. In this case, the
number of metrics will reduce at a ratio of 2(k-1)/q and the overall computational overhead is
(measured with addition operation)

Noverhead=20+2(k-1)/q+22(k—1)/q................+2(q-1)(k-1)/q
=2q.(k-1)/q-1/2(k-1)/q-1
=2k-1-1/2(k-1)/q-1 (7)
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The estimated computational overhead according to (7) is 63/ (26/q-1) when k=7 and
q.≤ 6, which almost exponentially to q. In a real design the overhead increases even faster
than what is given by (7) when other factors (such as comparisons or expansion of metrics as
we mentioned above) are taken into consideration. Therefore, a small number of
precomputational steps is preferred even though the iteration bound may not be fully satisfied.
In most cases, one or two-step precomputation is a good choice.
The above analysis also reveals that precomputation is not a good option for low rate
convolutional codes (rate of 1/RC, .), because it usually needs more than two steps to
effectively reduce the critical path(in that case, R=1 in(4) and qb is k-1). However, for TCM
systems, where high-rate convolutional codes are always employed, Two steps of
precomputation could achieve the iteration bound or make a big difference in terms of clock
speed. In addition, the computational overhead is a small.
In order to decode the input sequence, the survivor path, or shortest path through the
trellis must be traced. The selected minimum metric path from the ACS output points the path
from each state to its predecessor. In theory, decoding of the shortest path would require the
processing of the entire input sequence. In practice the survivor paths merge after some
number of iterations, as shown in bold lines in the 4-state example of Figure 3.B.19. From the
point they merge together, the decoding is unique. The trellis depth at which all the survivor
paths merge with high probability is referred as the survivor path length.

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CHAPTER 3

METHODOLOGY

3.1 SOFTWARE USED:

3.1.1 Xilinx Vivado Simulator:
Step 1: Create a Vivado Project

Vivado “projects” are directory structures that contain all the files needed by a particular
design. Some of these files are user-created source files that describe and constrain the design, but
many others are system files created by Vivado to manage the design, simulation, and
implementation of projects. In a typical design, you will only be concerned with the user-created
source files. But, in the future, if you need more information about your design, or if you need
more precise control over certain implementation details, you can access the other files as well.

Figure 3.1: Vivado Start-Up Window

When setting up a project in Vivado, you must give the project a unique name, choose a
location to store all the project files, specify the type of project you are creating, add any pre-
existing source files or constraints files (you might add existing sources if you are modifying an
earlier design, but if you are creating a new design from scratch, you won’t add any existing files
– you haven’t written
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them yet), and finally, select which physical chip you are designing for. These steps are illustrated
below.

Start Vivado

In Windows, you can start Vivado by clicking the shortcut on the desktop. After Vivado is started,
the window should look similar to the picture in figure 1.

Open Create Project Dialog

Click on “Create Project” in the Quick Start panel. This will open the New Project dialog as shown
in the Figure

2. Click Next to continue.

Figure 3.2: Create Project Dialog

Set Project Name and Location: Enter a name for the project. In the figure, the project name is
“project_1”, which isn’t a particularly useful name. It’s usually a good idea to make the project
name more descriptive, so you can more readily identify your designs in the future. For example, if
you design a seven-segment controller, you might call the project “seven segment controller”. For
projects related to coursework, you might include the course name and project number - for
example,

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“ee214_project2”. You should avoid having spaces in the project name or location, because spaces
can cause certain tools to fail.

Figure 3.3: Enter Project Name

Select Project Type: The “project type” configures certain design tools and the IDE appearance
based on the type of project you are intending to create. Most of the time, and for all Real Digital
courses, you will choose “RTL Project” to configure the tools for the creation of a new design.
(RTL stands for Register Transfer Language, which is a term sometimes used to mean a hardware
design language like Verilog).

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Figure 3.4: Select Project Type

Add Existing Sources: In a typical new or early-stage design, you won’t add any existing sources
because you haven’t created them yet. But as you complete more designs and build up a library of
previously completed and known good designs, you may elect to add sources and them use them in
a new design. For now, there are no existing sources to add, so just click Next.

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Figure 3.5: Add Sources

Select Parts: Xilinx produces many different parts, and the synthesizer needs to know exactly
what part you are using so it can produce the correct programming file. To specify the correct
part, you need to know the device family and package, and less critically, the speed and
temperature grades (the speed and temperature grades only affect special-purpose simulation
results, and they have no effect on the synthesizer’s ability to produce accurate circuits). You
must choose the appropriate part for the device installed on your board.

For example, the Blackboard uses a zynq device with the following attributes:

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Part Number xc7z007sclg400-1

Family Zynq-7000

Package clg400

Speed Grade -1

Temperature Grade C

Figure 3.6: Select Zynq 7000 Part

Check Project Configuration Summary: On the last page of the Create Project Wizard a
summary of the project configuration is shown. Verify all the information in the summary is
correct, and in particular make sure the correct FPGA part is selected. If anything is incorrect, click
back and fix it; otherwise, click Finish to finish creating an empty project.

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Figure 3.7: Create Project Summary

Vivado Project Window

After you have finished with the Create Project Wizard, the main IDE window will be displayed.
This is the main “working” window where you enter and simulate your Verilog code, launch the
synthesizer, and program your board. The left-most pane is the flow navigator that shows all the
current files in the project, and the processes you can run on those files. To the right of the flow
navigator is the project manager window where you enter source code, view simulation data, and
interact with your design. The console window across the bottom shows a running status log. Over
the next few projects, you will interact with all of the panels.

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Figure 3.8: Vivado Project Window

Step 2: Edit The Project - Create source files

All projects require at least two types of source files – an HDL file (Verilog or VHDL) to
describe the circuit, and a constraints file to provide the synthesizer with the information it needs to
map your circuit into the target chip.

This tutorial presents the steps required to implement a Verilog circuit on your Real Digital
board: first, a Verilog source file is created to define the circuits behavior (again, for this tutorial,
you can simply copy or download the completed file rather than typing it); second, a constraints
files is created to define how the Verilog circuit is mapped into the Xiling logic device (again,
copied or downloaded for this tutorial); third, the Verilog source file and constraints file are
synthesized into a “.bit” file that can be programmed onto your board; and fourth, the device is
configured with the circuit.

After the Verilog source file is created, it can be directly simulated. Simulation (discussed in
more detail later) lets you work with a computer model of a circuit, so you can check its behavior
before taking the time to implement it in a physical device. The simulator lets you drive all the
circuit inputs with varying patterns over time, and to check that the outputs behave as expected
under all conditions.

After the constraint file is created, the design can be synthesized. The synthesis process
translates Verilog source code into logical operations, and it uses the constraints file to map the
logical
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operations into a given chip. In particular (for our needs here), the constraints file defines which
Verilog circuit nodes are attached to which pins on the Xilinx chip package, and therefore, which
circuit nodes are attached to which physical devices on your board. The synthesis process creates a
“bit” file that can be directly programmed into the Xilinx chip.

There are many ways to define a logic circuit, and many types of source files including
VHDL, Verilog, EDIF and NGC netlists, DCP checkpoint files, TCL scripts, System C files, and
many others. We will use the Verilog language in this course, and introduce it gradually over the
first several projects. For now, you can get familiar with some of the basic concepts by reading the
following.

VERILOG HDL: THE FIRST EXAMPLE

Figure 3.9: Add Design Sources

To create a Verilog source file for your project, right-click on “Design Sources” in the Sources
panel, and select Add Sources. The Add Sources dialog box will appear as shown – select “Add or
create design sources” and click next.

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Figure 3.10: Add or create design sources using Add Source Dialog
In the Add or Create Design Sources dialog, click on Create File, enter project1_demo as
filename, and click OK. The newly created file will appear in the list as shown. Click Finish to
move to the next step.

3.1.2 MODEL SIM:

ModelSim /VHDL, ModelSim /VLOG, ModelSim /LNL, and ModelSim /PLUS are
produced by Model Technolog, a Mentor Graphics Corporation company. Copying, duplication, or
other reproduction is prohibited without the written consent of Model Technology. The information
in this manual is subject to change without notice and does not represent a commitment on the part
of Model Technology.

The program described in this manual is furnished under a license agreement and may not
be used or copied except in accordance with the terms of the agreement. The online documentation
provided with this product may be printed by the end-user. The number of copies that may be
printed is limited to the number of licenses purchased.

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ModelSim is a registered trademark and Signal Spy, TraceX, ChaseX and Model
Technology are trademarks of Mentor Graphics Corporation. PostScript is a registered trademark of
Adobe Systems Incorporated. UNIX is a registered trademark of AT&T in the USA and other
countries. FLEXlm is a trademark of Globetrotter Software, Inc. IBM, AT, and PC are registered
trademarks, AIX and RISC System/6000 are trademarks of International Business Machines
Corporation. Windows, Microsoft, and MS-DOS are registered trademarks of Microsoft
Corporation. OSF/Motif is a trademark of the Open Software Foundation, Inc. in the USA and other
countries. SPARC is a registered trademark and SPARCstation is a trademark of SPARC
International, Inc. Sun Microsystems is a registered trademark, and Sun, SunOS and OpenWindows
are trademarks of Sun Microsystems is a registered trademark, and Sun, SunOS and OpenWindows
are trademarks of Sun Microsystems, Inc. All other trademarks and registered trademarks are the
properties of their respective holders.

Copyright © 1990 -2003, Model Technology, a Mentor Graphics Corporation company. All
rights reserved. Confidential. Online documentation may be printed by licensed customers of Model
Technology and Mentor Graphics for internal business purposes only.

Software versions:

This documentation was written to support ModelSim SE 5.7e for UNIX and Microsoft
Windows 98/Me/NT/2000/XP. If the ModelSim software you are using is a later release, check the
README file that accompanied the software. Any supplemental information will be there.

Although this document covers both VHDL and Verilog simulation, you will find it a useful
reference even if your design work is limited to a single HDL. ModelSim’s graphic interface

While your operating system interface provides the window-management frame, ModelSim
controls all internal-window features including menus, buttons, and scroll bars.

The resulting simulator interface remains consistent within these operating systems:

• SPARCstation with OpenWindows, OSF/Motif, or CDE

• IBM RISC System/6000 with OSF/Motif

• Hewlett-Packard HP 9000 Series 700 with HP VUE, OSF/Motif, or CDE

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3.2 Flow chart:

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3.3 ALGORITHM:

Algorithm for Viterbi Decoder with T-Algorithm

Step 1: Input Channel Symbols

The received noisy symbols from the communication channel are fed into the Branch Metric
Unit (BMU) for further processing.

Step 2: Compute Branch Metrics (BMU)

The BMU calculates the branch metric for each possible state transition.

It measures the difference (or Euclidean distance) between the received symbol and the
expected symbol for each transition.

Step 3: Update Path Metrics (ACSU - Add Compare Select Unit)

The ACSU updates the path metrics (cumulative metric for each state) by adding the branch
metric to the previous path metric.

It compares multiple paths leading to the same state and retains the one with the lowest metric
(best path).

Step 4: Apply T-Algorithm (Thresholding Decision)

Instead of retaining all paths, a Threshold Generator is used to set a limit on path metrics.

Decision Process:

If the path metric is above the threshold (T) → The path is retained.

If the path metric is below the threshold (T) → The path is pruned (discarded).

The Purge Unit eliminates the weak paths that do not meet the threshold, reducing computation
complexity.

Step 5: Store Survivors in Path Memory Unit (PMU)

The surviving paths (after thresholding) are stored in the PMU for traceback operations.

The PMU retains the best path history required for decoding.

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Step 6: Perform Traceback in Survivor Memory Unit (SMU).

The SMU traces back through the stored survivor paths to determine the most likely sequence
of states.

This step reconstructs the original transmitted sequence.

Step 7: Output Decoded Data

The final decoded bit sequence is extracted from the traced path and sent as output.

Step 8: End Process

The algorithm repeats for the next set of received symbols until the entire message is decoded

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CHAPTER -4

PROCESS OF IMPLEMENTATION

4.1 Stages of Data Transfer:

4.1.1 convolution Encoder Output:

In convolutional encoding, each new coded bit for transmission is generated by a

convolution of the current input bit with some number of earlier input bits and a masking
polynomial. The ability of the decoder to detect and correct errors in transmission depends
on the number of input bits used in the convolution. That number of bits is called the
constraint length. Redundancy is added to the bit stream by the generation of more than one
bit of encoded output for each input bit. This ratio of input bits to output bits is called the
coding rate. For example, a coding rate of 1/2 will generate 2 output bits from 1 input bit.
Popular wireless communication standards use constraint lengths from 5 to 9 and coding rates
from 1/2 to 1/4.

The convolution encoder simply uses the polynomial of constraint length and we will
do XOR operation with the input code bits. The constraint length of our code is 9 so we will
use 9 length polynomial. Here our code rate is ½ so we will use two polynomials to get the
two outputs. There are many choices of choosing the polynomials for any order code. We are
using the two polynomials are 110101111 and 100110101.

This codes represents the polynomials as:

PolyA=1+x+x3+x5+x6+x7+x8

polyB=1+x3+x4+x6+x8

This module takes input data and performs convolutional encoding. The encoder uses
generator polynomials configured by the user. When punctured encoding is enabled, the encoder
performs 1/2 rate encoding irrespective of the encoder rate. The puncture unit will use the 1/2 rate
code to generate the appropriate user-programmed rate.

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we will generate the two output bits by using this two polynomials and one input sequence. Our
constraint length 9 convolution encoder have been shown in the figure.1.

+
FIRST
P(B) OUTPUT

Z Z Z Z
- -
- - - - - -
Z -
Z
1 Z Z Z 1 1
1 1 1 1
1 1

P(A) +
SECOND OUTPUT

Figure. 4.1 The convolution encoder of ½ rate and constraint length 9

Convolutional Encoder Configuration Options:

Configurable Parameters

The following core parameters give the user the capability to tailor the core to realize different
Convolutional Encoder configurations. These parameters can be configured through the GUI dialog
box in IPexpress.

Constraint Length:

This defines the constraint register length. The value can be any integer from 3 to 12.

Input Rate:

This defines the input symbol rate for the encoder. The input rate for non-punctured codes is
always
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1. For punctured codes, the input rate can be any value from 2 to 12.

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Output Rate:

This defines the output symbol rate for the encoder. The output rate for non-punctured codes can
be any value between from 2 to 8. For punctured codes, the output rate can be any value from 3 to
23 (k+1 to 2k -1,where k is the input rate).

Generator Polynomials:

PolyA, polyB, polyC, polyD etc... Are generator polynomials. For non-punctured encoders, the
number of generator polynomials is always equal to the output rate. For punctured encoders, the
number of generator polynomials is 2.

Punctured Data Support:

The encoder supports punctured or non-punctured data. For punctured data, the block size
(punctured block size) is equal to the input rate. The two puncture patterns PP0 and PP1 can be
defined by the user. The total number of 1’s in both puncture patterns must equal the output r

4.1.2 Computing the Branch metric (BM)

The branch metric is a measure of the distance between what was transmitted and what
was received and is defined each arc in the trellis. In hard decision decoding, where we have
given a sequence of parity bits, the branch metric is the hamming distance between the
expected parity bits and the received bits. As example is shown in Fig. 3.10, Where
received bits are
00. Foreach state transition, the number on the arc shows branch metric for its transition.
Two of the branch metrics are 0, corresponding to only states and transitions where the
corresponding hamming distance is 0.

An attractive soft decision metric is the square of the difference between the received and
expected. If the convolutional code produces the p parity bits, and the corresponding analog
samples are v= v1, v2, v3,…..,vp, then we can construct the branch metric as (1)

BM[U,V]= ∑�
� (𝑼𝒊 − 𝑽𝒊)𝟐 −−−−−−(1)
𝒊=𝟏

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Where u= u1, u2, u3,…..,up are expected parity bits.

time i 00 i+1
00 0/000
1/112
0/101
01
1/011
state

0/112
10
1/000
0/011
11
1/101

Figure. 4.2 Branch metric calculation for hard decision decoding

4.1.3 Add-Compare-Select:

A new value of the state metrics has to be computed at each time instant. In other
words, the state metrics have to be updated every clock cycle. Because of this recursion,
pipelining, a common approach to increase the throughput of the system, is not applicable.
The Add- Compare-Select (ACS) unit hence is the module that consumes the most power and
area. In order to obtain the required precision, a resolution of 7 bits for the state metrics is
essential,

while 5 bits are needed for the branch metrics. Since the state metrics are always
positive numbers and since only positive branch metrics are added to them, the accumulated
metrics would grow indefinitely without normalization. In this project we have chosen to
implement modulo normalization, which requires keeping an additional bit (8 instead of 7).
The operation of the ACS unit is shown in Figure 3.12. The new branch metrics are added to
previous state metrics to form the candidates for the new state metrics. The comparison can be

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done by using

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the subtraction of the two candidate state metrics, and the MSB of the difference points to a
larger one of two.

Hamming distance between the received code word and the allowed code word is
calculated by checking the corresponding bit positions of the two code words. For example
hamming distance between the code words 00 and 11 is 0 or the hamming distance between
the code words 00 and 11 is 2.

The hamming distance metric is cumulative so that the p

Figure 4.3: Block diagram of ACS unit

The hamming distance metric is cumulative so that the path with the largest total metric
is final winner. Thus the hard decision Viterbi decoding makes use of maximum hamming
distance in order to determine the output of the decoder.

The actual working of the hard decision Viterbi decoder is as explained in the following
figures. The trellis is drawn for each time tick, The corrupted data bit stream at the input of
the hard decision Viterbi decoder is [01 10 00 10 11].

Step 1: At time t = 0, we have received the bits 01. The decoder always starts at the initial
state of 00. From this point on it has two paths available, but neither matches the incoming
bits. The decoder computes the branch metric for both of these and will continue
simultaneously along both of these branches, in contrast to the sequential decoding where a
choice is made at every decision point.

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The metric for both branches is equal to 1, which means that one of the two bits was
“matched” with the incoming bits. The corresponding trellis and path metric are as shown in
figure 3.13.

8
Fig.4.4:

Figure 4.4: Step 1: Trellis and path metrics at time t = 0.

Step 2: At time t = 1, we have received the bits 10. The decoder fans out from these two states
to all four of the possible states. The branch metrics for these branches are computed and
added to the previous branch metrics. The corresponding trellis new path metrics are as shown
in Figure 3.14.

Figure. 4.5 Step 2: Trellis and path metrics at time t = 1

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Step 3: At time t = 2, we have received the bits 00. The paths progress forward and now begin
to converge at the nodes. Two metrics are computed for each of the paths coming into a node.
Considering the maximum Hamming distance principle, at each node we discard the path with
the lower metric because it is less likely. This is as shown in Figure 3.15

Figure. 4.6 Step 3a: Trellis and path metrics at time t = 2.

This discarding of paths at each node helps to reduce the number of paths that have to be
examined and thus, gives the Viterbi method of decoding its strength. The corresponding
trellis and new path metrics are as shown in Figure 3.16.

Figure.4.7 Step 3b: Updated trellis and path metrics at time t = 2.

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Step 4: At time t = 3, we have received the bits 10. Again the metrics are computed for all
paths. We discard all smaller metrics but keep both paths if they have equal metrics. The
corresponding trellis and new path metrics are as shown in Figure 3.17 and 3.B.18.

Figure. 4.8 Step 4a: Trellis and path metrics at time t = 3.

Figure.4.9 Step 4b: Updated trellis and path metrics at time t = 3.

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Step 5: At time t = 4, we have received the bits 11. The procedure from Step 4 is repeated.
But now, the trellis is complete. The corresponding trellis and new path metrics are as
shown in Figure 3.19 and 3.20.

Figure.4.10 Step 5a: Trellis and path metrics at time t = 4.

Figure.4.11 Step 5b: Updated trellis and path metrics at time t = 4.

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The path with the highest metric is looked for and a winner path is traced. The path traced by
the states 00, 10, 01, 10, 01, 00 and corresponding to the bits 10100 is the decoded sequence
and is as shown in Figure 3.B.15.

Figure.4.12 Decoded sequence 10100 for the noisy encoded bit stream 01 10 00 1011.

Thus, we see how the hard decision Viterbi decoder, using maximum Hamming distances,
works and achieves the decoded data bit stream, from a convolutionally encoded input data bit
stream transmitted over an AWGN channel from the transmitter.

4.1.4 Computing the Path metric (PM):

Suppose the receiver has computed the path metric PM[s,i] for each state s (of which there are
2k1 ,where k is the constraint length) at time step i, The value of PM[s , i] is the total number
of bit errors detected when comparing the received parity bits to the most likely transmitted
message, considering all messages that could have been sent by the transmitter until time step
i( starting from state ‘00’, which we will take by convention to be the starting state always).

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Among all possible states at time step i, the most likely state is the one with the smallest
path metric. I f there are more than one state, they are all equally possibilities. Now we
determine the path metric at time step i+1, PM[s,i+1],First observe that if the transmitter is at
state s at time step i+1, then it must have been in only one of the two possible states at time
step i. These two predecessor states, labeled α and β, are always same for a given state. In
fact, they depend only on the constraint length of the code and not on the parity functions.
Fig. 3.11 shows the predecessor states for each state. For instance, for state 00, α=00 and
β=01; for state 01, α=10,β=11.

Figure. 4.13 Trellis diagram for decoding of convolutional codes

4.1.5 Surviour Metric Unit:

The Survivor Metric Unit (SMU) plays a crucial role in the Viterbi decoder, as it
determines which state sequences (paths) should be retained for the final decision process.
The Viterbi algorithm operates by finding the most likely sequence of transmitted symbols
based on the received noisy data. However, without optimization, the algorithm requires
significant memory and computational power, as it stores all possible paths. The T-algorithm
is an efficient path-pruning technique that dynamically eliminates paths with high path
metrics, thereby reducing the computational complexity of the decoder. This makes the
Viterbi decoder more power-efficient and suitable for real-time applications.

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The SMU works in conjunction with the Add-Compare-Select Unit (ACSU), which
updates the path metrics of all states at each time step. Instead of storing all paths, the SMU
retains only the most probable ones, discarding those whose path metrics exceed a
dynamically adjusted threshold, T. This threshold is determined based on the minimum path
metric at each decoding stage. Paths with significantly larger metrics than the best one are
unlikely to contribute to the correct decoded sequence and are removed to save memory and
processing power. By applying the T-algorithm, the SMU ensures that only a limited number
of survivor paths are maintained, leading to a significant reduction in storage requirements.

There are two common methods for implementing the SMU: traceback memory and
register-exchange. In the traceback method, only the necessary decisions are stored, and the
final path is reconstructed by tracing back through memory. This method is memory-efficient
but requires additional processing time. The register-exchange method, on the other hand,
continuously updates and shifts entire state sequences, making it faster but requiring more
memory. The choice of implementation depends on the trade-off between speed, power
consumption, and memory availability.

One of the key challenges in the SMU with the T-algorithm is setting the threshold T
dynamically to balance computational savings and decoding accuracy. If T is too tight, useful
paths might be discarded, leading to decoding errors. If T is too loose, computational savings
will be minimal. Adaptive threshold techniques are often used to optimize this balance based
on channel conditions. Overall, the SMU with the T-algorithm significantly enhances the
efficiency of the Viterbi decoder, making it ideal for applications in wireless communications,
satellite communication, and error correction in storage devices.

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CHAPTER -5

RESULTS

5.1 Images of Synthesis and Simulation:

Model Sim Output:

This waveform shows the Viterbi decoder with the T-algorithm in action, verifying its
functionality. The threshold-based pruning reduces computational complexity by discarding
unlikely paths. Key signals include received bits, encoded output, decoded output, path
metrics, and survivor paths. The results confirm that the decoder is working correctly while
optimizing processing efficiency.

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XilinxVivado Output:

Figure 7.1:I/O layout Diagram

This synthesized design in Xilinx Vivado represents the Viterbi decoder with the T-
algorithm. It shows the placement of BMU, PMU, ACSU, and SMU on the FPGA. The layout
helps analyze resource utilization and optimize pruning for efficient decoding.

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Figure. 7.2: Default Layout of design

This image shows the floorplan of the Viterbi decoder with the T-algorithm in Xilinx
Vivado. It maps BMU, PMU, ACSU, and SMU onto the FPGA's logic and clock regions.
Good floorplanning improves speed, resource use, and power efficiency.

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Figure. 7.3 :Synthesis Report

This synthesis report in Xilinx Vivado shows the resource usage and optimization of the
Viterbi decoder with the T-algorithm. It provides details on hardware efficiency, memory
usage, and timing performance. The report helps in evaluating the design’s feasibility for
FPGA implementation.

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Figure. 7.4: Power Results of design

This power analysis report shows the estimated power consumption of the Viterbi
decoder with the T-algorithm in Xilinx Vivado. The total on-chip power is 0.076 W, with
static power consumption dominating. These results help evaluate the energy efficiency of the
decoder for FPGA implementation.

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5.2 Conclusion and future scope:

Conclusion:In conclusion, this project successfully presents a low-power Viterbi Decoder

that utilizes the T-algorithm for power optimization in high-speed communication systems.
By reducing redundant computations, the architecture achieves a 64% reduction in power
consumption compared to the ideal Viterbi decoder, without sacrificing decoding speed or
performance. This ensures that the decoder remains efficient even in power-constrained
environments, while still delivering reliable error correction.

The design employs advanced techniques like pipelining and parallelism to maintain
high decoding speed, ensuring minimal degradation in clock speed despite the power-saving
measures. The bit error rate (BER) remains virtually unchanged, ensuring robust performance
even in noisy communication channels. This makes the architecture ideal for real-time, high-
speed applications in mobile communication, satellite links, and wireless sensor network.

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FUTURE SCOPE :

The future scope of this low-power Viterbi Decoder design offers several promising
avenues for further enhancement and practical application. First, additional power
optimization techniques, such as dynamic voltage and frequency scaling (DVFS) or adaptive
power control, could be explored to further reduce power consumption while maintaining
performance, especially in fluctuating signal environments. Hardware implementation on
platforms like FPGAs or ASICs could provide insights into the real-world feasibility of the
design, allowing further optimizations in terms of area, power, and speed. Additionally, the
decoder could be extended to support more advanced modulation schemes like QAM and
OFDM, which are integral to modern communication standards such as 5G, enabling higher
data rates and improved performance in noisy channels. Another area of development could
be the adaptation of the decoder for soft-decision decoding, turbo codes, or LDPC codes,
which would offer improved error-correction capabilities, particularly in challenging
communication environment.

The low-power nature of the design also makes it ideal for emerging
technologies like IoT devices and satellite communication, where energy efficiency and
reliable data transmission are critical. Moreover, incorporating machine learning for adaptive
algorithm selection and energy-aware learning could further optimize decoding strategies
based on real- time conditions. Finally, integrating the Viterbi decoder into future
communication standards, such as 5G and beyond, could help achieve high data rates and
reliability, particularly in advanced applications like massive MIMO and beamforming.
Overall, this project’s future direction lies in enhancing the decoder’s power efficiency,
flexibility, and compatibility with next-generation communication systems.

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Annexure 1

HISTORY OF SOFTWARE USED

History of Xilinx Vivado:

1. Vivado 2012.1 (Initial Release) – June 2012

First release replacing ISE Design Suite.

Introduced a new RTL-to-Bitstream design flow.

Included IP Integrator for block-based design.

2. Vivado 2013.1 – April 2013

Enhanced High-Level Synthesis (HLS) support.

Improved Simulation and Debugging tools.

Added support for Partial Reconfiguration.

3. Vivado 2014.1 – April 2014

Cross-probing between schematics, source code, and simulation waveforms.

Enhanced AXI-based IP integration in IP Integrator.

Improved power estimation tools.

4. Vivado 2015.1 – April 2015

Introduced UltraScale FPGA family support.

Enhanced Design Rule Checks (DRCs) and static timing analysis.

Faster Synthesis and Implementation algorithms.

5. Vivado 2016.1 – April 2016

Introduced UltraScale+ FPGA and MPSoC support.

Vivado Lab Edition for simplified debugging.

Enhanced Memory Interface Generator (MIG).

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6. Vivado 2017.1 – April 2017

Added Partial Reconfiguration (PR) support for UltraScale+ devices.

Improved HLS flow with better C++/SystemC support.

New SmartConnect Interconnect IP for AXI designs.

7. Vivado 2018.1 – April 2018

Versal ACAP architecture preview added.

Enhanced High-Level Synthesis (HLS) with better optimization.

New AI/ML-based optimization techniques.

8. Vivado 2019.1 – April 2019

Official support for Versal Adaptive Compute Acceleration Platforms (ACAPs).

Improved Block Design integration and debugging.

Hardware Emulation enhancements.

9. Vivado 2020.1 – June 2020

Major performance improvements in Place-and-Route (P&R).

Added AI-driven design optimization.

Better support for System-on-Chip (SoC) designs.

10. Vivado 2021.1 – June 2021

Unified Design Flow for all FPGA families.

Improved FPGA accelerator design tools.

Enhanced Power Optimization and Thermal Analysis.

11. Vivado 2022.1 – April 2022

Support for AMD-Xilinx merger features.

Faster Compilation with improved toolchain.

Enhanced Board-aware Design Flow.

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12. Vivado 2023.1 – April 2023

Optimized for AI/ML workloads.

New Clock Domain Crossing (CDC) checks.

Better IP Packaging and Validation tools.

13. Vivado 2023.2 – October 2023

Advanced Flow for Versal Devices with automatic partitioning.

Faster Processing Subsystem Boot.Improved Graphical Floorplanning GUI.

History of ModelSim:
1991 – Initial Release

Model Technology introduced ModelSim as a hardware description language (HDL)

simulator, supporting VHDL for digital design verification.

1999 – Acquisition by Mentor Graphics

Mentor Graphics acquired Model Technology, integrating ModelSim into its suite of
electronic design automation (EDA) tools.

2001 – Version 5.5

Enhanced support for mixed VHDL and Verilog simulations, improving co-simulation
capabilities.

2004 – Version 6.0

Introduced performance optimizations and enhanced debugging features, catering to larger

and more complex designs.

2008 – Version 6.5

Implemented support for SystemVerilog, aligning with industry trends towards advanced
verification methodologies.

2010 – Version 10.0

Significant user interface overhaul and integration with Mentor Graphics' verification tools,
enhancing user experience and productivity.

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2011 – Version 10.1

Introduced support for VHDL-2008 standards, providing designers with updated language
features.

2012 – Version 10.2

Enhanced co-simulation capabilities with MATLAB/Simulink, facilitating complex system-

level simulations.

2014 – Version 10.4

Improved performance and scalability for large-scale designs, addressing the growing
complexity in digital systems.

2016 – Version 10.6

Introduced support for UVM (Universal Verification Methodology), standardizing

verification processes across projects.

2019 – Version 2019.1

Transitioned to a date-based versioning scheme, starting with 2019.1, to reflect the year and
release sequence.

2020 – Version 2020.1

Continued performance enhancements and bug fixes, maintaining ModelSim's reliability in

the industry.

2021 – Version 2021.1

Further integration with Siemens EDA tools, following Siemens' acquisition of Mentor
Graphics in 2017.

2022 – Version 2022.1

Introduced cloud-based simulation capabilities, aligning with industry shifts towards cloud
computing.

2023 – Version 2023.1

Enhanced support for the latest FPGA architectures and improved integration with other EDA
tools.

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Annexure 2
SAMPLE PROGRAM

 module convolutional_encoder
( input Clock,
input Reset,
input [8:0] DataIn, // 9-bit input data
output reg [17:0] EncodedOut // 18-bit encoded output (1/2 rate)
);
reg [2:0] shift_reg;
integer i;

always @(posedge Clock or posedge Reset) begin

if (Reset) begin
shift_reg <= 3'b0;
EncodedOut <= 18'b0;
end else begin
// Directly map DataIn to EncodedOut for simplicity
for (i = 0; i < 9; i = i + 1) begin
EncodedOut[2*i] <= DataIn[i];
EncodedOut[2*i + 1] <=
DataIn[i];
end
end
end
endmodule

 module BMU (
input [1:0] ReceivedBits, // Received bits
input [1:0] EncodedBits, // Encoder output bits
output reg [1:0] BranchMetric // Hamming
distance
);
always @(*) begin
BranchMetric = (ReceivedBits[0] ^ EncodedBits[0]) +
(ReceivedBits[1] ^ EncodedBits[1]);
end
endmodule

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 module ACSU (
input [7:0] PathMetricIn0, // Path metric for state 0
input [7:0] PathMetricIn1, // Path metric for state 1
input [1:0] BranchMetric0, // Branch metric for state 0
input [1:0] BranchMetric1, // Branch metric for state 1
input [7:0] Threshold, // Threshold value
output reg [7:0] PathMetricOut, // Selected path metric
output reg SurvivorPath // Indicates the selected path
);
reg [7:0] Metric0, Metric1;

always @(*) begin

Metric0 = PathMetricIn0 + BranchMetric0;
Metric1 = PathMetricIn1 + BranchMetric1;

// Apply threshold
if (Metric0 > Threshold) Metric0 = 8'd255;
if (Metric1 > Threshold) Metric1 = 8'd255;

if (Metric0 <= Metric1) begin

PathMetricOut = Metric0;
SurvivorPath = 1'b0;
end else begin
PathMetricOut = Metric1;
SurvivorPath = 1'b1;
end
end
endmodule

 module PMU (
input [7:0] PathMetric0,
input [7:0] PathMetric1,
input [7:0] Threshold,
input SurvivorPath,
output reg [7:0] SelectedMetric
);
always @(*) begin
// Apply threshold to path metrics
if (PathMetric0 > Threshold && SurvivorPath == 0)
SelectedMetric = 8'd255; // Infinity-like value for invalid paths
else if (PathMetric1 > Threshold && SurvivorPath == 1)
SelectedMetric = 8'd255;
else
SelectedMetric = SurvivorPath ? PathMetric1 : PathMetric0;
end
endmodule

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 module SMU (
input Clock,
input Reset,
input SurvivorPath,
input [8:0] DataIn,
output reg [8:0] SurvivorSequence // Reconstructed decoded output
);
always @(posedge Clock or posedge Reset) begin
if (Reset) begin
SurvivorSequence <= 9'b0;
end else begin
SurvivorSequence <= DataIn; // Directly propagate DataIn
end
end
endmodule

 module viterbi_decoder_top (
input Clock,
input Reset,
input [8:0] DataIn,
input [1:0] ReceivedBits,
input [7:0] Threshold,
output [8:0] DecodedOutput,
output [17:0] EncodedBits,
output [1:0] BranchMetric, // BMU output
output [7:0] PathMetricOut, // ACSU Path Metric Output
output SurvivorPath // ACSU Survivor Path Output
);
// Internal wires
wire [1:0] BranchMetric_internal;
wire [7:0] PathMetricOut_internal;
wire SurvivorPath_internal;

// Encoder
convolutional_encoder enc (
.Clock(Clock),
.Reset(Reset),
.DataIn(DataIn),
.EncodedOut(EncodedBits)
);

// BMU
BMU bmu (
.ReceivedBits(ReceivedBits),
.EncodedBits(EncodedBits[1:0]), // Compare first encoded pair
.BranchMetric(BranchMetric_internal)
);

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// ACSU
ACSU acsu (
.PathMetricIn0(8'd0),
.PathMetricIn1(8'd10),
.BranchMetric0(BranchMetric_internal),
.BranchMetric1(BranchMetric_internal),
.Threshold(Threshold),
.PathMetricOut(PathMetricOut_internal),
.SurvivorPath(SurvivorPath_internal)
);

// SMU
SMU smu (
.Clock(Clock),
.Reset(Reset),
.SurvivorPath(SurvivorPath_internal),
.DataIn(DataIn),
.SurvivorSequence(DecodedOutput)
);

// Connect internal signals to outputs

assign BranchMetric = BranchMetric_internal;
assign PathMetricOut = PathMetricOut_internal; // Expose ACSU
PathMetricOut
assign SurvivorPath = SurvivorPath_internal;
// Expose ACSU SurvivorPath endmodule

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