KTO KARATAY UNIVERSITY

FACULTY OF ENGINEERING AND NATURAL SCIENCES

MECHATRONICS ENGINEERING
GRADUATİON PROJECT REPORT
xxxxxxxxx-MUSTAFA USTA

JAMMER SYSTEM WITH FPGA

KTO Karatay University
Faculty of Engineering and Natural Sciences
Mechatronics Engineering
Graduation Project Report

Mustafa USTA
Bachelor's Graduation Project

Bachelor Graduation Project

Project Advisor: Assistant Professor Emre OFLAZ

KONYA
DECEMBER 2024
 SUMMARY

Mustafa USTA
JAMMER SYSTEM WITH FPGA
Bachelor Project
Konya, 2025

This project investigates FPGA-based digital systems, algorithms, and RF (Radio

Frequency) technologies, integrating them into an innovative signal jamming project.
Utilizing the Nexys A7 FPGA board, a system capable of disrupting wireless
communication signals in specific frequency bands was developed.
The primary goal is to understand FPGA architecture, digital signal processing
techniques, and RF systems through direct implementation. The research includes
analyzing FPGA's hardware programming, designing a signal jamming circuit, and
applying algorithms to target Bluetooth, Wi-Fi, GSM, and radio frequencies.
The methodology involves adaptive frequency selection, advanced digital signal
simulations, and efficient control algorithms on FPGA. The system is designed for
effective operation across various frequency bands, emphasizing flexibility and
modularity.
This study showcases the capabilities of FPGA in advanced engineering projects,
providing a learning platform for RF and digital signal processing innovations and
highlighting FPGA's role in future technological advancements.

Keywords
FPGA, signal jamming, rf technologies, digital signal processing, spectrum analysis,
algorithm design, hardware design language

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 TABLE OF CONTENT

SUMMARY .................................................................................................................................. ii
TABLE OF CONTENTS ............................................................................................................ iiii
LIST OF TABLES ....................................................................................................................... iv
LIST OF FIGURES ..................................................................................................................... iv
LIST OF ABBREVIATIIONS..................................................................................................... vi
1. INTRODUCTION .................................................................................................................... 1
2. JAMMER WITH FPGA ........................................................................................................... 3
2.1. System Overview .............................................................................................................. 4
2.1.1. Purpose and Importance of the System..................................................................... 4
2.1.2. System Operation Algorithm .................................................................................... 5
2.1.3. System Components and Architecture ...................................................................... 7
2.2. FPGA Technology ............................................................................................................ 9
2.2.1. What is FPGA, What are its Advantages and Disadvantages? ............................... 10
2.2.2. FPGA Coding Languages and Hardware Design Language Types ........................ 10
2.2.3. The Role of FPGA in the Project and the FPGA Board Used ................................ 13
2.3. RF Components and Signal Processing .......................................................................... 21
2.3.1. RF Fundamentals and Spectrum ............................................................................. 22
2.3.2. Voltage Controlled Oscillator ................................................................................. 22
2.3.3. Phase-Locked Loop (PLL) ..................................................................................... 24
2.3.4. Digital-to-Analog Converter (DAC) ....................................................................... 25
2.3.5. Modulation Techniques .......................................................................................... 26
2.4. Jammer Technology ........................................................................................................ 28
2.4.1. What is Jammer ?.................................................................................................... 28
2.4.2. Jammer Types ......................................................................................................... 29
2.4.3. Jammer Algorithm Used in the Project................................................................... 31
2.5. System Integration and Communications ....................................................................... 32
2.6. Project Time Management .............................................................................................. 36
2.7. Project Cost Management ............................................................................................... 37
3. CONCLUSION ....................................................................................................................... 38
4. TABLES AND FIGURES ...................................................................................................... 40
4.1. Tables .............................................................................................................................. 40
4.2. Figures ............................................................................................................................ 42
REFERENCES ........................................................................................................................... 48

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 LIST OF TABLES

Table 1. FPGA comparison ............................................................................................. 40

Table 2. FPGA specification .......................................................................................... 40
Table 3. Communication protocol comparison .............................................................. 41
Table 4. Frequency values of different technologies ...................................................... 41
Table 5. Project cost breakdown ..................................................................................... 41

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 LIST OF FIGURES

Figure 1. System flowchart ............................................................................................. 42

Figure 2. FPGA internal structure ................................................................................... 42
Figure 3. Logic block structure ....................................................................................... 42
Figure 4. Card used in the project ................................................................................... 43
Figure 5. VHDL code of the lfsr equation ...................................................................... 43
Figure 6. Circuit diagram of the LFSR function ............................................................. 43
Figure 7. Schematic of the I2C protocol ......................................................................... 43
Figure 8. Read function of the protocol .......................................................................... 44
Figure 9. Write function of the protocol ......................................................................... 44
Figure 10. Operating frequencies of communication technologies .............................. 45
Figure 11. VCO voltage-frequency graph ....................................................................... 45
Figure 12. PLL internal schematic .................................................................................. 45
Figure 13. Graphs of signals applied to the PLL ............................................................ 45
Figure 14. Bit and resolution graph................................................................................. 45
Figure 15. LFSR simulation output graph....................................................................... 46
Figure 16. AM modulation graph ................................................................................... 46
Figure 17. AM modulation bandwidth ............................................................................ 46
Figure 18. FM modulation graph .................................................................................... 46
Figure 19. What is a jammer system ............................................................................... 46
Figure 20. Gantt chart ..................................................................................................... 47
Figure 21. Cost distrubition pie chart .............................................................................. 47

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 LIST OF ABBREVIATIONS

Abbreviation Description
ADC Analog-to-Digital Converter
ACK Acknowledgment Process
AM Amplitude Modulation
ASIC Application-Specific Integrated Circuit
DSP Digital Signal Processing
FPGA Field-Programmable Gate Array
FM Frequency Modulation
GSM Global System for Mobile Communications
HLS High-Level Synthesis
HMI Human-Machine Interface
I2C Inter-Integrated Circuit
LFSR Linear Feedback Shift Register
LO Local Oscillator
NACK Negative Acknowledgment Process
PLL Phase-Locked Loop
RF Radio Frequency
RTL Register Transfer Level
VCO Voltage-Controlled Oscillator
VHDL VHSIC Hardware Description Language

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1. INTRODUCTION

This research project aims to delve deeper into FPGA (Field Programmable Gate Array)
technology and use the knowledge gained to develop an innovative, functional and
portable system for the integration of digital signal processing (DSP) and radio frequency
(RF) systems. The study process started by exploring the wide possibilities offered by
FPGAs, followed by extensive investigations on signal processing techniques and jammer
systems.

Subject and Coverage

The focus of the project is to blend digital signal processing and RF technologies through
the design of an FPGA-based jammer system, and to systematically transfer the technical
knowledge and methodologies acquired in the process. The project starts from the basic
principles of FPGA and progresses to application development on FPGA platforms using
VHDL programming language. In addition, an in-depth knowledge of the mechanisms of
RF systems has been acquired.

Importance and Unique Value

The significance of the work lies in the fact that the superior digital signal processing
capability of FPGAs is considered as an ideal development platform, especially for
jammer systems. Combining RF and FPGA technologies offers an innovative perspective
by bringing together different disciplines. While traditional approaches usually produce
large and stationary systems, the portable system design preferred in this project adds a
distinct uniqueness to the work.

Objectives
Main objectives of the project can be listed as follows:
• In-depth study of the FPGA ecosystem and its applications.
• Understand the basics of FPGA programming by assimilating the VHDL language.
• To gain expertise in jammer systems and digital signal processing techniques.
• To create an original signal processing flow diagram using the acquired knowledge.
• To develop signal mixing algorithms by conducting detailed research on RF systems.

Method
The research methodology started with a theoretical background in FPGA and VHDL. At
this stage, an extensive literature review on signal processing techniques and RF systems
was carried out. Based on the theoretical knowledge, the following practical steps were
followed:

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 1. FPGA board selection and VHDL training: Setting up development environments
and acquiring basic coding skills.
2. In-depth research on jammer systems and signal processing techniques: Complex
signal generation using LFSR.
3. ADC component selection and ADC-FPGA communication via I2C protocol.
4. Detailed investigation on basic standards and components of RF systems.

Structuring of the Study Chapters and Topics Analyzed

The project report is organized around the following main chapters:
1. FPGA and VHDL Basics: Detailed analysis of FPGA architecture, operating
principles and programming environments.
2. Digital Signal Processing Techniques: Advanced signal processing algorithms
and basic principles of DSP.
3. RF Systems and Applications: RF technologies, modulation techniques (AM,
FM), RF mixers, antenna design, etc.
4. Project Development Process: Phases of the project, technologies used and
evaluation of the outputs.
5. Conclusions and Evaluation: The project's achievements, innovative aspects and
potential future application areas.
This project is shaped as a comprehensive research on the integration of FPGA and
jammer systems with digital signal processing and RF technologies. The study offers
engineering students and researchers the opportunity to gain in-depth knowledge and
develop practical applications in these areas.

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2. JAMMER WITH FPGA

FPGA (Field-Programmable Gate Array) is a highly effective solution for systems that
require flexibility and high speed in hardware-based applications. The most important
advantage of FPGAs is their high parallelism and data processing capacity. Each
hardware component can operate in parallel, which is ideal for applications where
multiple signals need to be processed simultaneously. This enables complex digital signal
processing tasks to be performed at high speed and low latency. FPGAs can perform
operations such as signal modulation, filtering, timing, and data analysis much more
efficiently than software-based systems.

Jammer systems are devices that temporarily prevent communication systems from
functioning by jamming wireless communication signals in the target frequency bands.
The function of these systems is to jam signals in the frequency ranges of various
communication technologies (such as Bluetooth, Wi-Fi, GSM), causing transmission to
fail. Jammers are complex systems that require powerful signal processing algorithms,
precise frequency control and fast response time.

The FPGA has the capacity to handle this complexity of jammer systems. The FPGA
platform can perform all signal processing operations in parallel and integrate complex
digital algorithms as well as RF technologies. Thanks to the flexibility offered by FPGAs,
new algorithms and components that can be adapted to jammer systems can be
implemented quickly.

In the project, the jammer system developed using FPGA increased the efficiency of the
system by running digital signal processing (DSP) algorithms at the hardware level.
While the FPGA performs tasks such as signal mixing, frequency analysis, modulation
techniques and filtering, its integration with RF components enables effective jamming
at targeted frequencies. This integration successfully combines the signal processing
power of the FPGA platform with RF technologies, enabling the design of a high-
performance and flexible jammer system.

The potential application areas of the developed FPGA-based jammer system cover
almost all electronic devices and wireless communication technologies used today. This
wide range includes cell phones, Wi-Fi networks, Bluetooth devices, GPS systems, drone
control systems and even IoT (Internet of Things) devices. Our system has the capacity
to perform signal jamming and blocking functions in every area where these technologies
are used. It offers an effective solution especially in security-critical areas, in
environments where sensitive information needs to be protected, or where wireless
communication needs to be restricted in certain areas.

In conclusion, the parallel processing capability and flexibility of the FPGA has greatly
increased the applicability and efficiency of jammer technology. The integration of FPGA
and jammer systems provides the necessary hardware-based solutions to perform
complex signal processing operations quickly and accurately. This project demonstrates
a powerful and flexible system that addresses a wide range of applications in today's
world of modern electronic devices and wireless communication technologies.

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 2.1. System Overview

In this project, an FPGA-based jammer system has been developed, and digital signal
processing algorithms have been integrated with RF (Radio Frequency) technologies. The
system performs jamming of transmitted signals in certain frequency bands for wireless
communication technologies. The main purpose of the developed system is to provide a
high performance, fast and reliable solution for jammer applications.

At the core of the jammer system is an FPGA-based digital control mechanism. FPGA is
preferred because of its capacity to perform signal processing algorithms at high speed.
In this system, the FPGA plays critical roles from the generation of the digital signal,
determination of the target frequencies, modulation of the signals and coordination with
RF components.
The overall structure of the project consists of the following components:
• Signal Processing Unit: Algorithms running on the FPGA hardware undertake the task
of generating and modulating jammer signals. These algorithms include frequency
analysis, LFSR (Linear Feedback Shift Register) based random signal generation and
phase control.
• RF Components: The system is supported by an RF module consisting of components
such as a Voltage Controlled Oscillator (VCO), Phase Locked Loop (PLL), and filtering
units. These components provide signal amplification to the RF band and frequency
selectivity.
• Communication and Integration: The communication between the FPGA and RF
components is provided using the I2C protocol. This protocol allows the system to
perform precise control and dynamic adjustments.
• Control and Display Unit: System parameters and operations can be monitored and
managed via control software and digital displays.
• In the design of the system, easy extensibility and modularity were prioritized. Thanks
to the flexibility of the FPGA, new algorithms can be added for different jammer
applications and the existing infrastructure can be easily updated.
The project design was tested and optimized during the implementation process, thus
achieving a successful result on both theoretical and practical level.
This overview summarizes the main components and functionality of the system. In the
following sections, each component and function will be discussed in more detail.

2.1.1. Purpose and Importance of the System

This project aims to develop an in-depth understanding of both digital signal processing
and RF technologies by designing an FPGA-based jammer system. The aim of the
system is not only limited to fulfill a jamming function, but also to demonstrate that
hardware-based digital systems can be effectively integrated into wireless
communication systems. In this context, the project provides a platform to test advanced
engineering skills on a real system.

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The use of FPGAs adds an innovative dimension to the project. The flexible hardware
architecture of FPGAs offers the capacity to run complex jamming algorithms on
multiple frequencies simultaneously. This enables multitasking in RF systems with
parallel processing capability. Considering the dynamic nature of jammer systems, the
FPGA's reconfigurable and reprogrammable features make this technology highly
suitable for optimizing system performance and enabling rapid adaptation to future
development needs.

The importance of the project is not only limited to the application of the advantages
provided by FPGA technology. It also offers the ability to analyze and control the
behavior of RF components through digital signal processing algorithms. This makes it
possible to address critical issues more effectively such as frequency management,
spectrum analysis and jamming in communication systems.

As a result, this project brings together two main disciplines: FPGA-based hardware
design and RF systems. The integration of these two disciplines represents an important
step towards developing the next generation jammer systems. The system has a flexible
and modular architecture that can be used both in academia and industry. Therefore, the
project aims not only to increase technical know-how but also to provide a basis for
future designs.

2.1.2. System Operation Algorithm

The system consists of two main parts: FPGA and PCB. The FPGA provides only signal
generation (LFSR) and system control, while the PCB handles signal processing and RF-
based operations. The system works according to the following sequence:

1) FPGA (Control and Signal Generation)

a) LFSR (Linear Feedback Shift Register):

The LFSR in the FPGA generates a random (pseudo-noise) signal. This signal is
transmitted in digital form to the PCB.
b) Control Mechanism:
The control mechanism on the FPGA controls the modules on the PCB. In this
control process the following parameters are set:
c) VCO1 (Amplitude Modulation Frequency Setting)
The vco used here is used to set the frequency band.
d) VCO2 (RF Mixer Carrier Frequency Adjustment)
The main purpose of the vco here is to adjust the operating frequency.
e) Digital Attenuator Settings
To adjust the operating range of the system, we need to adjust the signal strength.
The control of this process is also done with the RF amplifier, and its control is
provided by the fpga.

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 f) Antenna Selection
The user selects the antenna by interacting with the switches on the controller to activate
the preferred antenna.

2) PCB (Signal Processing and RF Operations)

The pseudo-noise signal provided by the FPGA is processed in various modules on
the PCB. These processes take place as follows respectively:
a) DAC (Digital-to-Analog Converter):
The LFSR output generated by the FPGA is converted to analog form by DAC on
the PCB.
b) Amplitude Modulation (AM):
The analog signal provided by the DAC is subjected to amplitude modulation. During
this process, the frequency signal generated by VCO1 is connected to the modulator
input.
Objective: To be able to target different frequency bands by controlling the amplitude
of the output signal.
c) RF Mixer:
The modulated signal is sent to the RF mixer module as an information signal. The
RF mixer combines this signal with the carrier frequency signal generated by the
VCO2.
Conclusion: The output is a complex signal whose frequency band and transport
frequency can be adjusted.
d) RF Amplifier:
The signal from the RF mixer is of low amplitude and is amplified to the specified
power level by the RF amplifier.
e) Digital Attenuator:
The signal at the amplifier output is adjusted to the appropriate energy level by
attenuating it with a digital attenuator if necessary. The user can select the strength
of the output signal.
f) Antenna:
The post-processed signal is broadcast via the antenna type specified by the user. The
antenna options targeted to be added to the system are:
(1) Directional Antenna (Pinpoint Propagation)
(2) Omnidirectional Antenna (Equal Propagation in All Directions)

All the systems mentioned above will be explained in detail in other topics.
The flow diagram of the working mechanism of the system is shown in Figure 1 in the
appendix section in the image below.

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2.1.3. System Components and Architecture

The system consists of two basic structures: FPGA module and PCB (Circuit Board). The
FPGA manages the control and signal generation part of the system, while various RF
and analog operations are performed on the PCB. The cooperation between these two
structures ensures highly efficient and precise operation of the system. The components
and general architecture of the system are described below:

1) FPGA Components and Tasks

The FPGA is the central control unit that forms the brain of the system. Its main tasks
are:
• LFSR (Linear Feedback Shift Register):
The LFSR running inside the FPGA generates a pseudo-noise (random) signal.
This signal is a 12-bit data stream and is generated in digital form. The FPGA
sends this digital signal over the I2C protocol to the DAC module, which converts
it into analog form.
• I2C Communication:
The I2C protocol is used to securely transfer the 12-bit signal generated by the
LFSR to the DAC. Here, communication is only performed between the FPGA
and the DAC.
• Control Mechanism:
The FPGA controls the modules on the PCB through direct connections (pins).
The task of controlling the basic components of the system is as follows:
o VCO1 (Amplitude Modulation Frequency): The FPGA prepares the input signal
required for modulation by determining the VCO1 frequency band.
o VCO2 (RF Carrier Frequency): The FPGA sets the carrier frequency for the
mixer circuit.
o Digital Attenuator: The FPGA controls the signal strength required to attenuate
the signal from the RF amplifier.
o Antenna Selection: The FPGA selects the appropriate antenna according to user
preferences and activates the circuit.

2) PCB (Circuit Board) Components and Functions

The PCB is the main circuit platform where digital signals from the FPGA are processed
and converted into RF-based analog operations. Listed below are the components and
their functions:

• DAC (Digital-to-Analog Converter):

The 12-bit digital signal coming from the FPGA is converted to an analog signal
by the DAC module on the PCB. This conversion forms the basis for the
amplitude modulation of the system.

• Amplitude Modulator:
The analog signal generated by the DAC is subjected to amplitude modulation.

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 • VCO:
The frequency provided by it is given as input to the modulator circuit,
allowing operation in different bands.
• RF Mixer:
The modulated signal is mixed with the carrier frequency provided by the
VCO2 in the mixer circuit. This produces a complex signal that is carried into
the target frequency range.

• RF Amplifier:
The low amplitude signal from the mixer is amplified to a specified power
level by an RF amplifier. This process ensures that the signal is effectively
transmitted to the antenna.
• Digital Attenuator:
The signal at the RF amplifier output is attenuated and reduced to specified
energy levels with the help of a digital attenuator. This attenuation process is
controlled via FPGA.
• Antenna:
The output signal is transmitted through the antenna. The system is designed
to work with two different antenna types:
o Directional Antenna: Allows to direct the signal in a specific
direction.
o Omnidirectional Antenna: Radiates the signal equally in all
directions.
• VCO: With the VCOs used in the system, the frequency and bandwidth of the
signal can be adjusted and easily controlled by the controller.

• Frequency Multiplier: With the frequency multiplier circuits to be used in the

system, especially after the VCOs, it enables the system to operate at high
frequency levels (GHz level) that the VCOs cannot reach. Although the
frequency resolution decreases slightly in this section, the use of frequency
multiplier circuits does not pose a problem for the system since it will work
within a certain frequency band and we can precisely adjust the VCOs
(typical resolutions of VCOs usually vary between 12-16 bits).

3) General Architecture of the System

The system works with fluid communication and task sharing between the FPGA and
PCB. The FPGA takes care of control and signal generation, while the PCB modules are
responsible for transporting the signals to the RF band. The following items summarize
the general flow of the system:

i. The pseudo-noise signal generated by the FPGA with LFSR is sent to the DAC via
I2C protocol and converted to analog form.

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 ii. The analog signal on the PCB is modulated, transported in the RF mixer and amplified
with the help of an amplifier.
iii. The processed signal is transferred to the antenna and broadcast.
iv. The system provides flexible control by making antenna selection, frequency settings
and signal power settings via FPGA.

2.2. FPGA Technologies

FPGA (Field-Programmable Gate Array) is a programmable hardware technology used

for the design and development of electronic systems. FPGAs offer a reprogrammable
infrastructure at the hardware level to perform user-specific functions. This makes them
a highly flexible and powerful solution for different applications.

History and Development:

FPGA technology first emerged in the 1980s and has evolved in line with the rapidly
growing needs in the industry. The first FPGAs, produced by pioneering companies such
as Xilinx (AMD) and Altera (INTEL), were developed to provide a more flexible
alternative to fixed-function ASIC (Application-Specific Integrated Circuit) designs. In
the 1990s and beyond, as processing speeds increased and the density of logic gates
increased, FPGAs began to be used in more complex applications.

Why Use?
FPGAs are widely used in many industries for the following primary reasons:
• Hardware Flexibility: FPGA offers rapid prototyping, testing and reconfiguration
thanks to its software-controllable hardware architecture.
• Parallel Processing Capability: The FPGA can perform multiple operations at the same
time thanks to its parallel logic cells, providing high efficiency.

Fields of Application:
FPGA is particularly prominent in various fields such as communication systems, image
processing, military and space technologies, medical electronics, digital signal processing
(DSP), artificial intelligence and machine learning accelerators.
Detailed advantages and disadvantages of this technology will be discussed in the next
section.

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2.2.1. What is FPGA, What are its Advantages and Disadvantages?

FPGA stands for Field Programmable Gate Array and is a hardware technology that
enables dynamic reprogramming of electronic circuits. FPGAs are equipped with
thousands of programmable logic blocks and reconfigurable interconnection resources
that connect them together.

FPGAs provide users with a customized computing platform, enabling customization at

both the software and hardware level. Unlike fixed hardware such as an ASIC
(Application-Specific Integrated Circuit) or microcontroller, FPGAs are completely
flexible and can be reprogrammed many times by the user.

Figure 2 shows the basic components of an FPGA. Logic blocks perform the basic
functions of the circuit, while interconnect resources enable these blocks to communicate
with each other. Peripheral I/O cells (Input/Output Cells) manage the connection of the
FPGA to the outside world. In Figure 3, the connections of flip flops, mux and register
structures, which are the elements in the slice structure in the FPGA, are shown in detail.
Figure 2 and Figure 3 images can be found in the appendices section of the report.

Advantages and Disadvantages:

In Table 1, the advantages and limitations of FPGA technology are examined in detail.
As can be seen in the table, FPGAs come to the forefront with their ease of use compared
to other boards. Tables can be found in the appendices of the report.

2.2.2. FPGA Coding Languages and Hardware Design Language Types

1) FPGA Coding Languages

FPGAs are programmed with special coding languages that are used to describe and
operate the hardware. These coding languages are different from traditional software
development languages because they are designed to describe the hardware (e.g., logic
gates, flip-flops, and timing).

The languages most used in the hardware identification process are:

• Verilog:
Popular for its simple structure and syntax, especially notable for its shorter code.
• VHDL (VHSIC Hardware Description Language):
Provides stricter rules and modularity, ideal for complex systems.
• System Verilog:
Extended version of Verilog; supports modern design techniques.
• Chisel:
Used for open-source and high-level hardware definition.
• High-Level Synthesis (HLS):
Enables FPGA design with languages such as C and C++.

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These languages provide flexibility in logic design and offer solutions to suit the
requirements of different projects.

2) Hardware Description Language Types

FPGA coding languages are classified into the following types of hardware design
languages:

➢ RTL (Register Transfer Level):

The most widely used design type for FPGA.
Defines how to connect logic blocks and how to transfer data in the system.
Both Verilog and VHDL are used for such designs.

➢ Behavioral Design:
It describes the high-level behavior of the system.
It models the input-output relationship of the hardware but does not provide exact timing
information.
Usually performed using HLS tools.

➢ Structural Design:
It defines the system at the gate and flip-flop level.
It is a more detailed and low-level design approach.

➢ Dataflow Design:
Focus on data transfer and process pipelines.
Common in high-performance digital signal processing (DSP) projects.

2.2.2.1. What is VHDL Language?

❖ VHDL (VHSIC Hardware Description Language) is a hardware description

language developed as part of the Very High-Speed Integrated Circuit project. It
was introduced by the US Department of Defense in the 1980s and has been
standardized for the design, verification, and simulation of hardware systems.
Defined as the IEEE 1076 standard, VHDL is used for digital circuit design and
allows a system to be described at both behavioral and structural levels.

❖ Features of VHDL:

• Hierarchical Structure Support: VHDL provides an ideal environment for

creating modular and hierarchical designs.

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 • Rich Data Types: Supports a wide range of data types, including numbers,
arrays, strings, and special data types.
• Platform Independence: The design can be easily ported to different platforms
such as an FPGA or ASIC.
• Timing Modeling: Suitable for timing analysis and verification.
• Code Portability: Well-structured code can be reused in other projects,

❖ Structure of VHDL:
VHDL handles hardware design through three main constructs:
A. Entity
• Defines the input-output ports of the hardware module.
B. Architecture
• Defines the functional structure of Entity.
• It may be Structural, behavioral, or dataflow.
C. Configuration
• Allows us to choose between different architectures (not widely used).

Advantages of VHDL:
i. Modular and Reusable Code: Developed designs can be easily used in other projects.
ii. Detailed Timing Control: Suitable for clock frequency and timing analysis.
iii. Industry Standard: It has a large user community and documentation.
iv. Behavioral Simulation of Hardware: Design verification can be done before building
real circuits.

Disadvantages of VHDL:
i. Learning Curve: The syntax is complex and detailed.
ii. Long Code: Requires longer coding compared to Verilog.
iii. Complexity: Too detailed and complex for small projects.

Usage Areas of VHDL:

• Digital circuit design such as FPGA and ASIC.
• Development of digital processors and control systems.
• Design of on-chip data buses and communication protocols.
• Security and verification studies.

In conclusion, VHDL is a widely used language in the field of digital hardware design
due to its flexibility and capabilities. It facilitates design processes with its modular and
hierarchical structure, especially in large-scale, complex projects.

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2.2.3. The Role of FPGA in the Project and the FPGA Board Used

• Role of FPGA:
The leading role of the FPGA (Field-Programmable Gate Array) used in the project is to
perform high-speed signal processing and control processes of the entire system
simultaneously. Jammer systems need to target signals in different frequency bands while
simultaneously coordinating various control mechanisms. This is where FPGA
technology offers an ideal solution.

To explain the role of FPGA in the project in detail:

▪ Signal Processing
The Jammer system used in the project requires exceedingly high processing power to
effectively process the targeted signals. The FPGA's built-in DSP (Digital Signal
Processing) slices allow us to perform signal processing operations quickly and
accurately.
Parallel processing capability allows multiple signals to be processed simultaneously.
This is especially critical for a Jammer system targeting multiple frequencies.

▪ System Control
❖ The integrated logic cells of the FPGA provide control of the hardware and
peripherals on the board. Precise management of inputs and outputs is essential for
complex systems.
❖ The control of the buttons, switches and sensors used in my project is managed by
FPGA to increase the reliability of the system.
▪ High Working Frequency
The 100 MHz+ processing frequency of the Nexys A7-100T board provides a great
advantage, especially in responding to rapidly changing signals.
The dynamic frequency management feature of the FPGA makes it possible to target
devices operating in different frequency bands (e.g., Wi-Fi, Bluetooth, GSM).

▪ Low Latency
The hardware-based operating principle of the FPGA allows operations to be completed
with much lower latency than software-based solutions. This is an important feature to
perform critical operations such as signal degradation in a timely manner.

▪ Versatility
Thanks to its programmability, the FPGA can be adapted to the algorithms needed in the
system. This can respond to the different needs of the project, both for signal processing
methods and control mechanisms.
Helps me to quickly adapt to different scenarios during development phases.

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• Advantages of FPGA Usage:

The use of FPGA in the project provided the following advantages:

a. Single Controller Solution: The FPGA's ability to perform signal processing and
control tasks simultaneously eliminated the need for an external processor or
controller.
b. Hardware and Software Integration: RAM, sensors and input-output units on the board
are all easily integrated with the FPGA, reducing the complexity of the system.
c. Flexibility: Thanks to the programmable structure of the FPGA, the design can be
easily updated at different stages of the project and in case of changing needs.

• Characteristics of the FPGA Board Used:

Nexys A7-100T board was used in the project. The prominent technical features of the
board are shown in Table 2 in detail.

The reason the Nexys A7-100T board was specifically selected for the project:

1) Availability in Turkey
The accessibility of the FPGA to students in Turkey at affordable prices is an
important advantage.

2) Input-Output Port Diversity

Having various GPIO pins and supporting all input-output operations that may be
needed in the project.

3) Existence of Internal Units

Built-in components such as switches, buttons and seven segment displays reduce
the need for additional hardware.

4) Internal Sensors and Output Units

Facilitates making project-specific modifications in the application development
process.

The visual of the card preferred in the project is given in Figure 4.

14
As you can see, there are many input and output pins, various sensors, display, and
notification LEDs on the board. Thanks to such reasons, the Nexys A7-100T board is a
suitable choice for learning and practicing cards.

2.2.3.1. LFSR Implementation

• What is LFSR and why was it used?

LFSR Linear Feedback Shift Register is a structure that generates a pseudo-random

number according to a given sequence based on a given polynomial using an ordered
sequence of shift registers and XOR connections between these registers. In my project,
I decided to use LFSR to generate the complex signals required for the Jammer system.
The reason for this is that counter devices, especially military technology devices, can
detect and filter signals that are not complex enough as fixed signals. In order to prevent
such devices, it is obvious that the complexity of the signal generation should be
increased.

• Justification for 12 Bit LFSR Selection

Within the scope of the project, a maximum bandwidth of 1070 MHz is used. In order to
generate a signal of sufficient complexity in this bandwidth, a 12-bit LFSR structure was
chosen. Reasons for the choice:

1) 𝑥12 = 4096 different values, which is quite sufficient in terms of the signal complexity
of the system.
2) Although it is possible to work with a larger bit size on the FPGA side, my choice
was limited to twelve bits due to the difficulties in finding an affordable and high bit
count DAC (Digital to Analog Converter) in Turkey.

• Effect of DAC Selection on LFSR Design

Although the maximum operating frequency of the DAC used in the project is 3.4 MHz,
the system was tested at a frequency of 400 kHz. Higher DAC bit levels can increase the
ability to generate complex signals. However, since twelve bits is an adequate solution

15
and considering the bit level and frequency constraints supported by the DAC, a special
polynomial of degree 𝑥12 was used in the project.

The polynomial chosen is critical for LFSR to work properly. The polynomials that
generate the most complex and pseudo-random signals are specially defined in the Galois
field.
The special 12-bit LFSR polynomial used in this project is shown as “𝑥12 + 𝑥11 + 𝑥10 +
𝑥 4 + 1”. Figure 5 shows the code equivalent of the polynomial in VHDL in FPA.

This polynomial produces a maximum-length sequence, and it becomes possible to obtain

all intermediate combinations between each sequential state. This increases the capacity
of the LFSR to generate pseudo-random signals.

• Register and XOR Structure in LFSR

The following structures were used in the LFSR design:

1. Register:

o Twelve registers are available.

o Each register holds a one-bit state and is shifted to the next cycle.

2. XOR Gate:

o XOR over the specified coefficients of the polynomial to obtain a pseudo-random

output sequence.

This structure creates polynomial-based sequences, allowing the signal to be both

simultaneous and complex. Figure 6 shows the electrical schematic of the polynomial
used in the system.

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2.2.3.2. I2C Protocol and Use of MCP4725 DAC Module
In the project, the MCP4725 DAC module was used to generate analog signals from
digital data. Low power consumption, high resolution and I2C protocol communication
made this module an ideal solution for the project. The I2C protocol was preferred for
data transfer between the FPGA and the DAC because the communication method of the
MCP4725 is based on this protocol.

1) Technical Specifications of MCP4725 DAC Module:

The main features related to the use of the MCP4725 module in the project are:

▪ Resolution: 12-bit, precision analog signal generation.

▪ Communication Protocol: I2C, easy and stable communication.
▪ EEPROM: Permanent value storage.
▪ Voltage Output: Precision analog voltage output.
▪ Physical Integration: Easy integration into the project thanks to compact dimensions.
▪ In the project, the slave address of the MCP4725 is set to 1100000 (7 bits) by
connecting the A0 pin on the module to the GND line.

2) I2C Protocol Overview:

Inter-Integrated Circuit is a two-line protocol for short-distance, low-speed

communication between hardware. It uses two basic lines:

o SDA (Serial Data Line): Data line.

o SCL (Serial Clock Line): Clock line.

Main Features of I2C:

▪ Master-Slave Structure: Master device controls communication, sends data to slave

devices.
▪ Addressing: Each slave device has an address. For the MCP4725 module the slave
address is “1100000”.
▪ 8 Bit Data Frame: The I2C protocol transmits data in 8-bit packets. Since the
MCP4725 receives 12-bit data, the data is split into two parts.

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▪ Clock Synchronization: The clock frequency is defined as 400 kHz on the FPGA and
designed as a generic structure.
A block diagram of the basic Master Slave structure is shown in Figure 7.

Justification for Use of the I2C Protocol:

In the project, this protocol was preferred because the MCP4725 DAC module works
with the I2C protocol. Furthermore, stable communication between devices operating
at high data rate and frequency often requires communication protocols. The I2C
protocol was an ideal choice for stable, organized, and low pin usage communication
between digital devices.

Advantages of I2C:

❖ Reduced Pin Count: Only two lines are used.

❖ Multiple Device Support: Multiple slave devices can be connected to the same
data line.
❖ Bidirectional Communication: Two-way data flow is possible.
❖ Dynamic Addressing: Slave devices can be easily organized.
❖ Wide Speed Range: 100 kHz to 3.4 MHz speed options.

Disadvantages of I2C:

❖ Limited Speed: Slower compared to protocols like SPI.

❖ Cable Load: Capacity limits of the line can affect communication quality.
❖ Limited Number of Devices: Maximum 128 devices can be connected due to 7-
bit addressing.

• ACK/NACK Roles and Data Transmission

In the I2C protocol, the ACK (Acknowledge) and NACK (Not Acknowledge)
signals serve the purpose of verification in data transmission between master and
slave devices. After each 8-bit data transfer, the receiving device acknowledges the
successful data reception with an ACK signal. If the data was not received correctly,
a NACK signal is sent.

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 Figure 8 shows the basic master-to-slave reading graph and Figure 9 shows the
basic master-to-slave write signal graph with a detailed example. Please refer to the
figure for details.

3) I2C Usage in the Project:

In the project, the I2C protocol for communication between the FPGA and
MCP4725 DAC module was implemented using VHDL. For this purpose, an I2C
master module was designed and embedded in the FPGA. The module sent 12-bit
digital data to the MCP4725 by setting the slave address. The data on the SDA and
SCL lines were tested and verified with an oscilloscope. It was observed that the
MCP4725 module works reliably depending on the data coming from the FPGA.

4) Signal Analysis and Frequency Selection:

In the project, data transmission was realized with a clock frequency of 400 kHz.
This speed ensures stable communication in low-speed applications. The possibility
of switching to higher data rates (e.g., 1 MHz or 3.4 MHz) was evaluated at a later
stage.

• Comparison of I2C and Alternative Protocols

In the world, can, i2c, spi, and uart protocols are used for communication and
communication and a comparison of communication protocols is made in Table 3.

2.2.3.3. Control Mechanism

1) General Description and HMI System

The control mechanism on the system consists of an HMI (Human-Machine Interface)

and a control panel that allows the user to easily manage the system. Through the HMI,
the user can monitor all parameters of the system and make the desired adjustments. In
addition, the user will be provided with the following information:

• Battery Power: Current capacity and status of the system battery.

• Antenna Type: Specifications and type of antenna used.

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 • Emitted Signal Type: Analog or digital modulation information.
• Frequency: Broadcast frequency range.
• Signal Strength: Output power of the broadcast signal.
• System Temperature: Temperature status of FPGA and peripheral components.
• Battery Voltage: Instant information about battery voltage.

The parameters set by the user will be implemented through the algorithm and physical
components (e.g., VCOs, antenna, and attenuator) created in the FPGA.

2) Control Algorithm

The control algorithm will be structured using parallel processes to include combinatorial
and sequential operations of the system. This algorithm:

• Processing the user's selected adjustments and transferring them to the relevant units,

• Optimize outputs by checking them with feedback data,

• Designed to continuously improve system efficiency.

3) Feedback Mechanism and Closed Loop Control

The system will operate with a closed-loop feedback control mechanism. Thanks to
the feedback mechanism:

• Output data is continuously monitored.

• Current values (e.g. out. power, antenna efficiency) are compared with targeted values.

• The system detects any deviations and makes corrections.

• These processes are visualized to the user through indicators on the HMI.

Example:

If the system output power is targeted at 3W but only 2.8W is detected at the antenna
output, the system detects this difference. By changing the settings of the required
components (e.g. VCO or amplifier), the output power is optimized and maximum
efficiency is achieved.

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 The user can see this correction process on the HMI screen as current data and
efficiency percentage.

4) Current Situation and Activities Carried Out

Work is currently underway on the basic functions of the system.

The studies carried out are listed below.

✓ LFSR (Linear Feedback Shift Register): Integrated in the FPGA for random number
generation and regulating data flow.

✓ DAC Communication: The digital-to-analog conversion process works successfully

and the data received from the FPGA is converted to analog signals via DAC units.
This represents an important step to support the feedback and control process on the
HMI.

2.3. RF Components and Signal Processing

RF (Radio Frequency) technologies cover the generation, transmission, and detection of

radio waves in the electromagnetic spectrum. These systems play an important role in
modern communications, radar, medical applications, space technologies, military
systems, and many other fields. RF signal processing is the set of processes and
technologies required to modulate, filter, amplify and accurately receive or transmit these
waves.

Signal processing in RF systems is based on the following basic components:

i. Analog and Digital Operations: While signals are processed in analog media, digital
conversions and calculations are more frequently used in modern technologies.
ii. Precision and Stability: High accuracy RF systems require complex control algorithms
and quality hardware to minimize signal distortion and meet spectral requirements.

RF components and signal processing techniques will play a critical role to increase the
sensitivity of the system used in this project, reduce unwanted interference and maximize
efficiency. In the following sub-headings, these systems will be discussed in detail and
their roles within the scope of the project will be analyzed.

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2.3.1. RF Fundamentals and Spectrum

1) RF Fundamentals

Radio frequency (RF) refers to the generation, transmission, and reception of

electromagnetic waves in a specific frequency range. RF signals generally cover the
frequency range between 3 kHz and 300 GHz and are the cornerstone of wireless
communications. These technologies are used in many different applications such as
Bluetooth, Wi-Fi, GSM, radio, and TV broadcasting.

The operating principles of RF systems allow the signal to be modulated on a specific

carrier frequency to transmit the desired information and to be decoded back by the
receiver. In this process, the stability of the frequency, the power level of the signal and
its immunity to interference are of great importance.

2) Spectrum

The electromagnetic spectrum is defined in a table that organizes the use of radio
frequency signals into frequency ranges. Specific frequency ranges are assigned for each
technology, and it is critical to ensure that these frequencies are used effectively and
without interference. The spectrum table shown in Table 4 shows in detail the frequency
ranges of both the technologies the system works with and the technologies it wants to
block. In addition, Figure 10 visualizes the frequencies given in Table 4 on the spectrum
for ease of understanding.

2.3.2. Voltage Controlled Oscillator

A Voltage Controlled Oscillator (VCO) is an electronic circuit in which the output

frequency can be varied by the control voltage applied to its input. VCOs are often used
in the generation of RF signals and as a key component in frequency switching
applications.

The operating principle of the VCO allows the oscillation frequency to rise and fall
depending on the control voltage. This offers flexibility in dynamic frequency
management and modulation techniques. VCOs are commonly used in amplitude

22
modulation (AM), frequency modulation (FM) and phase modulation (PM) systems, as
well as in complex RF signal processing circuits.

1) Using VCO in the Project

This project uses two different VCOs, each serving a different purpose:

a. VCO Used for Local Oscillator of Amplitude Modulation:

Mission: Adjusts the bandwidth of the signal in the system by controlling the amplitude
of the complex signal.

How it works: The amplitude of a complex signal varies through this VCO.

When the amplitude-modified signal is fed into the input of the RF mixer, the mixer
reflects this amplitude change as a bandwidth change.

This gives the system a modulation capability that is both more flexible and adaptable to
different bandwidths.

b. VCO Used for Local Oscillator Input of RF Mixer:

Task: To shift the bandwidth-shifted information signal to the frequency of the carrier
signal.

How it works: Working as a local oscillator, this VCO provides a carrier signal to the
mixer input.

The frequency of the signal is changed according to this carrier.

In addition, the frequency variation provided by the VCO allows the system to generate
complex signals that can vary in bandwidth and frequency simultaneously.

2) Advantages of Using VCO

Thanks to the two VCOs used in the project:

• Frequency and bandwidth control of a complex signal processing system becomes

fully dynamic.

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• In the signal processing process, the user can adapt both the carrier frequency and the
bandwidth of the signal according to the needs.
• It can be used for a wide range of applications, making the project versatile and
flexible.

The “Voltage versus Frequency” graph used to illustrate the operating characteristics of
the VCO describes the relationship between the control voltage and the generated
frequency. The graph is shown in Figure 11.

2.3.3. Phase Locked Loop (PLL)

A Phase-Locked Loop (PLL) is a feedback control system that regulates the output
signal by adapting to the phase of a reference signal. PLLs are often used in applications
that require signal matching and synchronization. This circuit is typically designed to
control an oscillator and eliminate the mismatch between phases.

PLLs consist of three basic components:

1. Phase Detector: Measures the phase difference between two signals.

2. Voltage Controlled Oscillator (VCO): Controlled by the error signal from the
phase detector and can change the frequency to adjust the output signal.
3. Filtering and Control Circuit: Processes the error signal from the phase detector,
filters noise and ensures system stability.

A. PLL Uses and Characteristics

PLLs are particularly ideal for the following situations, as they can be used in
combination with VCOs and offer a versatile control mechanism:

• Frequency Equalization and Stabilization: Ensures stable signal generation by

suppressing noise.
• Phase Equalization: Minimizes the phase difference between two signals.
• Harmonic Harmonization: Allows oscillators to be harmonized depending on the
reference frequency.

B. Use of PLL in the Project and Future Perspective

PLL is not used in this project at this stage. However, PLL integration is planned as a
solution mechanism for possible phase mismatches that may be encountered during the
use of VCOs. After completion of the project:

24
 • If phase mismatch or stability problems arise in the system, the use of PLL will
be considered to eliminate these problems.
• In order to provide phase equalization and stabilization, the PLL circuit can be
considered in the development phase of the project.

C. PLL and VCO Relationship

Since the PLL is integrated with the VCO circuit, when phase mismatches are detected,
the frequency of the VCO is controlled by the PLL and pulled to the correct reference
frequency. This guarantees harmonious and stable operation of the system. The VCOs
in the PLL function as the key element of phase locking. In Figure 12, the internal
structure of a PLL circuit and the vco-pll connection are explained in detail. Figure 13
shows the graphs of the applied signals.

2.3.4. Digital-to-Analog Converter (DAC)

A Digital-to-Analog Converter is a device that converts a digitally encoded signal into an

analog signal. Frequently used in digital systems, this component plays a critical role,
especially in signal processing applications. Working in the reverse of the ADC (Analog-
to-Digital Converter), the DAC brings digital information-based control mechanisms into
the physical world.

A. Basic Purpose and Circuit

The main purpose of a DAC is to convert digital data into a measurable analog signal,
such as voltage or current. A typical DAC circuit includes:
• Digital input data
• Reference voltage
• Output signal processing components.

B. Use in the Project

In this project, the complex digital signals generated in the Linear Feedback Shift Register
(LFSR) circuit are converted to analog signals by sending them to a 12-bit DAC. The
tasks of the DAC are:
• Enables the representation of a digital signal in an analog form.
• Makes the generated signals usable with RF components and other modules.

C. Operating characteristics of the DAC:

i. Operating frequencies: 400 kHz and 3.4 MHz are available in two options.
➢ 400 kHz: Suitable for more stable and low-speed operations.
➢ 3.4 MHz: Used in applications requiring faster data processing and wide bandwidth.

25
 ii. It works synchronously with the LFSR circuit.
iii. Data is transferred with the I²C protocol. This protocol provides reliable data
communication with low pin count.

D. DAC Basic Operating Principle

The DAC converts each bit of the digital signal into voltage or current using a specific
weighting. This conversion usually involves the following steps:
1. Receiving digital data as input.
2. Calculating the analog equivalent using Binary Weighted or R-2R Ladder type
circuits.
3. Generation of a smooth analog signal as output.

E. Advantages Gained by Using DAC in the Project

• Analog Signal Generation: Enables the conversion of complex digital signals into
a form that can be used in physical systems.
• Compatible Frequency Options: Offers flexibility according to system needs with
different operating frequencies.
• Speed and Stability: Thanks to the I²C protocol, a fast and stable data flow is
provided without data loss.

2.3.5. Modulation Techniques

Modulation is the process of encoding a low-frequency information signal by changing

the characteristics of a given carrier signal. This process ensures that the signal is portable
and can be transmitted on different channels without interference. Two main types of
modulation are commonly used in communication systems: amplitude modulation and
frequency modulation.

2.3.5.1. Amplitude modulation (AM)

Amplitude modulation is a method in which the amplitude of the carrier signal varies
according to the information signal. This technique is particularly suitable for transmitting
low frequency information signals over long distances.

A. Working Principle
The amplitude of the carrier signal is increased or decreased according to the amplitude
of the information signal. This results in a modulated signal that carries the information
signal and can be easily transmitted and received. Figure 16 shows the amplitude
modulation process in terms of signals with graphs.

B. Advantages
o It has a simple and easy to implement structure.
o Requires less complex circuit design.

26
 C. Disadvantages
o Sensitive to noise.
o Low efficiency: energy is wasted on the carrier.

D. Use in the Project

Amplitude modulation is used in the signal processing part of this project. Its main
purpose in the project is to create a frequency range by increasing the information signal
to the desired frequency level. Figure 17 shows a visualization of bandwidths according
to amplitude modulation. The bandwidth will change as a result of amplitude modulation.

Application Details
❖ Achieving Frequency Range: The modulation process can change the frequency
range of the information signal, and this range can be customized for different
technologies.
❖ Adjustable Bandwidth: Bandwidth control is achieved by changing the amplitudes
of complex information signals.
❖ Conclusion: This process carries the bandwidth of the complex signal and allows
for a more flexible signal with tunable characteristics.

2.3.5.2. Frequency modulation (FM)

Frequency modulation is a modulation method in which the frequency of the carrier signal
is varied according to the amplitude of the information signal. This technique is used for
high-quality and noise-resistant transmission.

A. Working Principle
The frequency of the carrier signal is increased or decreased depending on the
amplitude of the information signal. The modulated frequency variations carry the
characteristics of the information signal. Figure 18 shows the input and output signal
graphs of the frequency modulation process.

B. Advantages
Resistant to noise and distortion.
Provides higher sound quality.

C. Disadvantages
Requires wider bandwidth.
More complex to implement and decode than amplitude modulation.

27
2.4. Jammer Technology

Jammer technology refers to systems used to neutralize signals operating in a specific

frequency range. Jammers, which today have a wide range of applications in
communication, security, and military fields, are generally designed to prevent or
neutralize unwanted communication by jamming radio frequency signals. The basic
principle is to create a stronger interference signal in the frequency range of the target
signal and to block and interrupt the communication between the transceiver and the
receiver.

These technologies are carefully controlled both for defense purposes and because they
pose a risk of misuse. Jammer systems have an important role to provide control over a
signal spectrum and prevent unwanted interference.

2.4.1. What is a Jammer?

A jammer is a device or system that targets and neutralizes signals operating in a specific
frequency range. Basically, a jammer works by generating an interference signal at the
frequency of the target signal to interrupt communication between the transmitter and
receiver. This interference signal prevents the receiving device from detecting or
processing the original signal. The working logic of the technology is visualized in
Figure 19.

A. Working Principle of Jammer

Jammers are designed primarily to understand the targeted signal and to operate in the
same or close frequency range as that signal. The main operating principle is as follows:
i. The spectrum of the target signal is determined and analyzed.
ii. An interference signal is generated in this spectrum.
iii. The interference signal propagates stronger than the transmitter signal.
iv. Since the receiving device detects this strong interfering signal, it cannot process
the information signal containing the actual data and the communication is
interrupted.

B. Jammer Usage Areas

Jammer devices can be used for many different purposes in both civilian and military
fields:
• Defense Use: It can be used in military operations to intercept enemy
communications or to block signal traffic in a specific area for security purposes.
• Civilian Use: Low power jammers can often be used to block cell phone signals
in specific areas (e.g., cinemas, theaters, etc.).
• Security and Protection: Used to prevent unauthorized drone use in government
and private sector facilities or to control communications traffic in sensitive areas.

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C. Advantages and Disadvantages of Jammer Technology
Jammers, like other technologies, have some advantages and disadvantages.

1) Advantages:
a) Provides an effective solution to eliminate security threats.
b) Useful for regulating communication traffic in sensitive areas.
c) It operates at high frequencies, so it can neutralize many devices at the same time.

2) Disadvantages:
a) It creates serious security vulnerabilities and ethical problems when used illegally.
b) Side effects can disrupt not only the target signal but also innocent signals in the
same frequency band.
c) Operating enormously powerful devices can damage other electronic equipment
or have been observed to trigger communication errors.

2.4.2. Jammer Types

Jammers are classified into various categories according to the type of signals they target,
the frequency ranges they use and the breadth of the effects they provide. Below are the
common jammer types and their features in detail.

I. Frequency Based Jammer Types

In this category, jammers are classified according to the frequency ranges in which they
target signal interference:

1) Wideband Jammer
• Description: Generates interference signals over a wide frequency range.
• Advantages:
o It can block multiple signals at the same time.
o It has a simple and effective structure.
• Disadvantages:
o Energy consumption is high.
o Low precision frequency targeting capability.

2) Narrowband Jammer
• Definition: It targets only a specific frequency range.
• Advantages:
o It can operate with lower power consumption.
o Highly effective at neutralizing certain types of signals.
• Disadvantages:
o It has a more limited footprint than broadband devices.

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 3) Frequency Sweep Jammer
• Description: It targets multiple signal types by scanning the frequency range at a
specific speed.
• Advantages:
o Provides continuous wide area signal blocking.
• Disadvantages:
o Requires a more complex design for high frequency scan rates.

II. Jammer Types According to Application Areas

In this section, jammers are classified according to the technologies they block.

1) Cell Phone Jammer

• Definition: Targeting mobile communication frequencies such as GSM, 3G, 4G,
5G and blocking such communications.
• Uses: Controlling communication in places like movie theaters, meeting rooms
and locked security zones.

2) Wi-Fi/Bluetooth Jammer
• Description: Designed to block wireless connection technologies (Wi-Fi,
Bluetooth).
• Use Cases: Sensitive meetings, ensuring data security, preventing unauthorized
data transfer.

3) GPS Jammer
• Description: Disrupts Global Positioning Systems (GPS) signals, preventing
devices from being located.
• Areas of Use: Military operations, vehicle security against theft.

4) Drone Jammer
• Description: Disables drones' control signals and GPS data.
• Areas of Use: Protection of private property, airspace security.

5) Military Jammer
• Description: Targeting enemy communications networks and radar systems.
• Areas of Use: Electronic warfare, secure military operations.

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III. Types of Jammers According to Signal Propagation Method

1) Spot Jammer
• Definition: It focuses on a specific frequency point and blocks a single signal.
• Advantages:
o Efficient and energy-efficient operation.
• Disadvantages:
o Narrow targeting capacity.

2) Barrage Jammer
• Definition: It blocks multiple signals simultaneously over a wide frequency range.
• Advantages:
o Can create far-reaching initiatives.
• Disadvantages:
o Less efficient for target signals.

3) Pulse Jammer
• Definition: Disrupts signal communication by generating short pulses at the target
frequency.
• Advantages:
o High energy efficiency.
• Disadvantages:
o Only effective in certain applications.

2.4.3. Jammer Algorithm Used in the Project

The jammer algorithm of the project is based on the generation, processing, and efficient
distribution of a complex signal into a specific bandwidth. The combination of advanced
processing components (VCO, DAC, RF mixer) provides signal generation and
interference that meets the project requirements. Thanks to the flexibility in bandwidth
and frequency variability, the algorithm can be customized for different communication
technologies.
a. Complex Signal Generation
b. Digital Signal Processing and Conversion
c. Frequency Band Allocation
d. Continuous Distribution and Targeting
The algorithm can be examined under sub-headings such as.

31
2.5. System Integration and Communication

In this section, general information on the integration and communication processes of

the system will be presented, and a roadmap for future work is presented for the
operations that have not yet been conducted. This topic will be discussed in detail in the
following stages.

2.5.1.1. Integration of FPGA and RF Components

I. System Integration Plans

In the general integration stages of the system, the following operations are aimed at being
realized:

A) VCO and PLL Control:

o The 2 PLLs or VCOs to be used in the system will be integrated and controlled
by digital circuits.
o Through these control mechanisms, frequency settings will be realized flexibly.
B) Digital Attenuator Control:
o Digital attenuator circuits are planned to be designed and controlled in order to
precisely regulate the output power of the system.

C) Control of Antennas:
o A control circuit will be installed to regulate the physical parameters of the
antennas such as directivity and bandwidth.

D) PCB Design:
o A PCB board will be designed to include all components of the system.
o On the PCB, control elements and other electronic circuit components will be
integrated to provide an integrated structure of the system.

E) Power Circuit Design:

o An integrated power circuit will be designed to meet the energy needs of the
system.
o This circuit will be responsible for providing the voltage and current required by
other components.

F) Connection and Control Mechanism:

o No communication protocol (e.g., PWM, PDM) will be used on the system and
control operations will be performed by direct voltage application.
o FPGA connection will be established through physical connectors or pins, thus
ensuring coordination of all components.

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 II. Communication System
The communication section will be detailed under a separate sub-heading. However,
in general, the following processes will be addressed in the communication plan:

➢ All components work in harmony with the FPGA.

➢ Accurate transmission of control and supervision signals.
➢ Prevention of delays or data loss in communication circuits.
With the completion of these integration and communication stages, it is aimed that
the system will operate efficiently and completely.

2.5.1.2. I2C Protocol and DAC Communication

In this section, the communication process between the FPGA and the DAC using the
I2C protocol is detailed. The communication of the DAC, which plays a fundamental role
in the analog signal processing of the system, over I2C is a critical stage of system
integration.

➢ FPGA and DAC Communication via I2C Protocol

The I2C protocol is a two-wire communication mechanism and is used in this project for
the transmission of 12-bit digital signals between the FPGA (master device) and the DAC
(slave device). In this process:

a) DAC Addressing:
• By setting the addressing pin on the DAC, the 7-bit slave address is defined as
1100000.
• This address is controlled by the FPGA so that the transmitted signal is directed
to the correct slave device.

b) Frequency Selection:
There are three different operating frequencies determined by DAC:
• 100 kHz
• 400 kHz
• 3.4 MHz

Considering the system requirements and operating conditions, the frequency of 100 kHz
is considered to be insufficient. For this reason, frequencies between 400 kHz and 3.4
MHz are being evaluated among the available options and testing processes are ongoing.
The choice of frequency will be determined by the stability of the DAC and its
compatibility with the FPGA, which will directly affect the system performance.

33
 c) Conversion of Digital Signals to Analog Signals:
The digital signals from the FPGA are transmitted to the DAC via the I2C protocol.
The DAC converts this 12-bit digital data into an analog signal.
The data converted to analog signal is ready to be used in the system for other operations.

➢ Ongoing Work
At this stage, the testing process is not complete, and the following issues are being
worked on:

1) Frequency Selection Decision

Performance evaluation of 400 kHz and 3.4 MHz operating frequencies in
accordance with the system requirements is ongoing.
The impact of both frequencies on system stability and data transfer rate is being
analyzed.

2) Compatibility Tests
➢ Addressing and communication tests are performed to ensure accurate and
reliable data transfer between DAC and FPGA.
➢ It is aimed at optimizing signal quality and analog output stability.

3) Subsequent Operations

After the analog signal is obtained, the integration tests required for its use in other
processing units will be performed.

Note: The final decision on the communication parameters of the DAC and FPGA
will be determined based on the test results and the optimal values for the system
performance will be selected. This part will be detailed in the following stages.

2.5.1.3. VCO and PLL Control

In this section, the predictions and plans on the control mechanisms and frequency
management of the two VCOs to be used in the system are discussed. Although no active
work has been carried out at this stage, the basic approach, and plans on how the process
will be managed are explained.

I. VCO Control Mechanism

Control Voltage Adjustment:
• Using the maximum 3.3V output provided through the FPGA, the input voltage
required by the VCOs is set.

34
 • Depending on the control voltage, the width of the frequency band and the
technologies will be moved to operating frequencies.

Using Two VCOs:

Two separate VCOs will be used in the system and these VCOs will be capable of
operating at GHz levels:
• The first VCO will be involved in frequency bandwidth management.
• The second VCO will be used to carry the carrier signals of the technologies to
the frequency level.

II. Challenges and Prospects

A) Providing a Suitable VCO to Operate at GHz Levels:

The project foresees challenges in procuring suitable VCOs to operate at the GHz
level.
Alternative strategies are being considered to address this:
i. Frequency Multiplexer Usage:
• Frequency multipliers or frequency doubler circuits can be added to the VCO
output to increase the frequency by a certain ratio.
ii. Adjustable Frequency Multipliers:
• The design and use of a customized frequency multiplier circuit in the
frequency range of interest can ensure the flexibility of frequency adjustment.

III. Future Plans

A) Improvement of Frequency Management Mechanism:

• Design and simulation studies of the control voltage adjustment mechanism and
VCO frequency band control circuit will be carried out.

B) Frequency Multiplier Survey:

• Frequency doublers suitable for the project will be researched, procured or a
customized circuit design will be made if necessary.

C) Performance and Integration Test:

• The integration of VCOs with PLL will be tested, and all necessary optimizations
will be provided for stable operation of the system.

35
2.6. Project Time Management

This project was carried out progressively over a 14-week academic term. Each week,
specific tasks were assigned, and the project was divided into phases to ensure
structured progress.

▪ Weeks 1-2: Course and project selection were completed. The project topic was
determined, and preliminary research began.

▪ Week 3: A preliminary report was prepared, project approval procedures were

completed, and the project was officially confirmed.

▪ Weeks 4-5: General system research was conducted, the project concept was refined,
the system outline was created, a roadmap was established, and an estimated cost
analysis was performed. Additionally, the FPGA board was selected and ordered.
Simultaneously, basic FPGA training began.

▪ Weeks 6-7: The first phase of FPGA training was completed. The FPGA environment
was explored, and basic applications were implemented.

▪ Week 8: No work was conducted due to exam week.

▪ Week 9: Advanced FPGA programming techniques were learned, including

concurrent processes and hierarchical programming, which were essential for the
project.

▪ Week 10: Introduction to RF systems took place. Research was conducted on

oscillators, RF mixers, and modulation techniques. MATLAB was used for system
simulations. Various experiments were carried out to verify the feasibility of the
proposed system.

▪ Weeks 11-12: The system integration phase began. The fundamental working
principles of the entire system were established, and necessary testing and simulations
were performed. The required components were identified, and suitable parts were
sourced from local suppliers. Potential compatibility issues in practical applications
were examined and addressed.

▪ Weeks 13-14: The first physical implementation phase was initiated. The LFSR system
was successfully implemented on the FPGA. The DAC component, ordered in Week
12, arrived in Week 13. Since the FPGA needed to communicate with the DAC via the
I2C protocol, work was conducted on implementing I2C communication in VHDL.
Basic communication codes were developed, but full integration and successful
communication were not entirely completed.

▪ Week 15: The project documentation, report writing, and presentation preparation
were completed.

36
This time management approach ensured systematic progress throughout the project
while addressing encountered challenges with appropriate solutions. The Gantt chart
illustrating the project's time management is shown in Figure 20.

2.7. Project Cost Management

The costs for this project were incurred at various points between September and
December 2024. The expenses were distributed as follows:

▪ FPGA Board: 12,570 TL, accounting for 73% of the total cost.
▪ 12-bit DAC Module: 390 TL, representing 2.3% of the total cost.
▪ VCO Modules: Two units, each cost 346 TL, totaling 692 TL.
and contributed 4% to the budget.
▪ RF Mixer IC: One unit at 322 TL, making up 1.9% of the cost.
▪ RF Signal Generator: One unit at 880 TL, covering 5.1% of the budget.
▪ PCB Production: 1,200 TL, comprising 7% of the total expenses.
▪ Enclosure Manufacturing: 350 TL, accounting for 2% of the cost.
▪ Additional Materials: 800 TL, corresponding to 4.7% of the budget.

The total estimated cost of the project is 17,204 TL. However, within the 15-week
period, only the FPGA board, the 12-bit DAC module, and half of the additional
material costs (400 TL) were purchased, summing up to 13,360 TL, which corresponds
to 77.75% of the total budget.

The project cost breakdown is detailed in Table 5, while a pie chart illustrating the cost
distribution is presented in Figure 21.

37
3. CONCLUSION

This project is an original work that aims to develop an innovative solution for the
defense industry by combining two engineering disciplines. The project aims to analyze
FPGA and RF technologies in depth and transform this knowledge into a practical
project. The small number of jammer systems developed using FPGA in literature
makes this project more unique. In this context, the methods and techniques used in the
project offer an innovative structure that combines both digital and analog solutions.
This project has not only provided technical innovations, but also an important
contribution in terms of engineering approach.

During the project, many different methods were used to combine FPGA and RF
systems. From communication protocols to frequency multiplier circuits, digital signal
processing and frequency handling, a range of engineering techniques have been
followed. These methodologies have been a huge learning curve, not only theoretically
but also. In addition, obstacles encountered at the start of the project, such as production
difficulties, component availability constraints and cost issues, necessitated the need to
develop an engineering perspective and provide innovative solutions. During these
challenging and sometimes costly processes, important technical solutions were
developed to keep the project moving forward by working on alternative components
and new designs.

During the implementation of various RF methodologies, many factors have emerged

that need to be considered, especially the compatibility and interaction of FPGA and RF
systems. In addition to learning the basic principles of FPGA operation, the challenges
of integrating digital signal processing methods and RF operations into a real project
have been successfully overcome. In-depth studies on technical issues such as system
integration, system compatibility with communication protocols and signal processing
were carried out, and the knowledge gained in this process significantly strengthened
engineering skills. At this point, developing a strategic approach to problems and
providing solutions formed the basis of the successes achieved in the project.

An important feature that distinguishes the project from similar studies in technical
terms is the FPGA-based solution and the structure that combines digital-analog
components. While some jammer systems in the literature use signal generation or
modulation methods with completely analog circuits, this project offers a new way by
adopting a digital FPGA-based approach. This makes the project unique in terms of RF
circuits and frequency processing methods. System design with FPGA brings not only
compatibility with existing analog solutions, but also the construction of a more flexible
and modern structure.

As the project continued, after the successful completion of the first phase, the LFSR-
based signal generation system and the 12-bit DAC output system, the second phase, the
communication processes between the FPGA and the DAC, progressed rapidly. This is
a critical step before moving on to RF signal processing. In this process, MATLAB-
based simulation studies are carried out in parallel, focusing on determining the correct
RF topology and signal processing methods. Optimization of the control algorithm to be
integrated into the LFSR system to be developed on the FPGA is also planned at this

38
stage. As the RF system becomes clearer, it is aimed to control this system and make it
more efficient.

In the following stages, PCB design will be made in line with the results obtained from
the simulations and the final production process will begin. Finally, the integration of
the entire system will be ensured by designing the power circuit and the physical shell,
and all tests included in the project will be successfully carried out and reporting
procedures will be completed. This process, beyond being a phase that ends the project,
allows the information obtained to be presented as a more comprehensive solution.

One of the biggest challenges encountered during the project was the complexity of
ensuring the compatibility of the technologies. It was obvious that the combination of
FPGA and RF technologies required careful consideration of the sensitive details of
both areas. In particular, we tried to ensure that the system developed on the FPGA and
the RF circuits are correctly matched and that the systems work in harmony with each
other. To achieve this goal, different tests and protocols were applied to ensure that all
components worked together efficiently. This process demonstrates the importance of
not only technical skills in engineering design, but also the importance of a systemic
approach.

As the project progresses, optimizations will be made on both the hardware and
software side with the aim of building a user-friendly structure. The optimizations made
on the FPGA have enabled significant improvements to increase the efficiency of the
system. On the other hand, novel methods in RF signal processing will revolutionize the
signal generation and modulation techniques of the system. The combination of these
two areas has enabled a more effective utilization of the power of technologies and has
increased the applicability and effectiveness of the project and is expected to increase.

As a result, this project has evolved from being based solely on academic knowledge to
a structure that offers solutions to real world problems and can serve the end user. This
demonstrates the importance of adopting an interdisciplinary approach in the
engineering design process. Following the completion of the project, it is anticipated
that the results obtained will be inspiring not only in this field, but also for other
projects in the defense industry.

39
4. TABLES AND FIGURES

4.1. Tables

Table 1. PGA comparison table

Advantages Disadvantages
1. Flexibility: FPGAs can be 1. High Cost: Cost per unit is high
repeatedly programmed and compared to a single production design
customized. such as an ASIC.

2. Rapid Prototyping: FPGA is ideal

for testing and developing complex 2. High Power Consumption:
systems. Generally, it consumes more energy
compared to ASICs.
3. Parallel Processing Capability: 3. Complexity: FPGA coding and
Different processing units can run design process is more difficult than
simultaneously. ASIC or microcontroller design.

4. Updateability: New features can 4. Performance Limitations: FPGA is

be added through software updates generally not as fast as ASIC.
in the field.

5. Wide Application: Widely used 5. Cooling Requirement: May require

in image processing, digital signal additional cooling methods for more
processing (DSP), complex processes.
telecommunications.

6. Low Production Cost: Cost- 6. Requires Training: Developers may

effective for small or medium-scale take time to learn FPGA technology.
production.

Table 2. PGA feature table

Product
A7-100T
Variant
Nexys-7 Part XC7A100T-1CSG324C
Logic Slices 15,850 (4 6-input LUTs and eight flip flops each)
Block RAM 4,860 Kbits
Clock Tiles 6 (each with PLL)
DSP Slices 240
Internal Clock 450 MHz+
DDR2 Memory 128MiB
Cellular RAM 16MB

40
 Table 3. Communication protocol comparison
Properties I2C SPI UART CAN
Number of
2 4 1 2
Lines
Communication
Max. 3.4 MHz Max. 60 MHz Max. 1.5 Mbps Max. 1 Mbps
Speed
Addressing + - - +
Distance Short Short-Medium Long Medium-Long
Fast data Vehicle
Area of Use Sensors Series devices
transfer networks

Table 4. Frequency values of different technologies

Start End Medium
Frequency
Technology Frequency Frequency Frequency
Range (MHz)
(MHz) (MHz) (MHz)
Wi-Fi (2.4GHz) 2400 2483.5 83.5 2441.75
Wi-Fi (5GHz) 5150 5850 700 5500
Bluetooth 2402 2480 78 2441
Radio (FM) 87.5 108 20.5 97.75
Radio (AM) 535 1605 1070 1070
GSM (900 MHz) 890 915 25 902.5
GSM (900 MHz) 935 960 25 947.5
GSM (1800 MHz) 1710 1785 75 1747.5
GSM (1800 MHz) 1805 1880 75 1842.5
GSM (1900 MHz) 1850 1910 60 1880
GSM (1900 MHz) 1930 1990 60 1960

Table 5. Project cost breakdown table

Price Cumulative Ratio
Part Name Quantity
Price
1 FPGA 1 ₺12.570,00 ₺12.570,00 73,1%
2 DAC Module 12 BIT 1 ₺390,00 ₺390,00 2,3%
3 VCO Module Dual 2 ₺346,00 ₺692,00 4,0%
4 RF Mixer IC 1 ₺322,00 ₺322,00 1,9%
5 RF Signal Generator 1 ₺880,00 ₺880,00 5,1%
6 PCB Board Production 1 ₺1.200,00 ₺1.200,00 7,0%
7 Carrier Box Production 1 ₺350,00 ₺350,00 2,0%
8 Extra Materials 1 ₺800,00 ₺800,00 4,7%
₺17.204,00 100,0%

41
4.2. Figures

Figure 1 Flowchart of the system

Figure 2 FPGA internal structure Figure 3 Logic block structure

42
Figure 4 Card used in the project (Nexys A7-100T)

Figure 5 VHDL code of the LFSR equation

Figure 6 Circuit diagram of the LFSR function

Figure 7 I2C protocol scheme

43
Figure 8 Read function of the protocol

Figure 9 Write function of the protocol

44
 Figure 10 Operating frequencies of communication technologies

Figure 12 PLL internal schematic

Figure 11 VCO voltage-frequency graph

Figure 13 Graphs of signals applied to Figure 14 Bit and resolution graph

the PLL

45
 Figure 15 LFSR simulation output graph

Figure 16 AM modulation graph Figure 17 AM modulation bandwidth

Figure 19 What is a jammer system

Figure 18 FM modulation graph

46
 Figure 20 GANNT chart of project

Figure 21 Cost distribution chart

47
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