RISC-V Reference Data Card v 0.

2
Core Instruction Formats
31:35 24:20 19:15 14:12 11:7 6:0

R-type Funct7 rs2 rs1 Funct3 rd Opcode

I-type imm11:0 rs1 Funct3 rd Opcode
S-type imm11:5 rs2 rs1 Funct3 imm4:0 Opcode
B-type imm12,10:5 rs2 rs1 Funct3 imm4:1,11 Opcode
U-type imm31:12 rd Opcode
J-type imm20,10:1,11,19:12 rd Opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

RV32i Base Integer Instructions (in alphabetical order)

Mnemonic Name FMT Description (in Verilog) Opcode Funct3 Funct7 or imm*
add ADD R R[rd] = R[rs1] + R[rs2] 0110011 (51) 000 (0) 0000000 (0)
addi ADD Immediate I R[rd] = R[rs1] + SignExt(imm) 0010011 (19) 000 (0)
and AND R R[rd] = R[rs1] & R[rs2] 0110011 (51) 111 (7) 0000000 (0)
andi AND Immediate I R[rd] = R[rs1] & SignExt(imm) 0010011 (19) 111 (7)
auipc Add Upper Immediate to PC U R[rd] = PC + (imm << 12) 0010111 (23)
beq Branch if EQual B if(R[rs1] == R[rs2]) PC += SignExt({imm12:1, 1'b0}) 1100011 (99) 000 (0)
bge Branch if Greater or Equal B if(R[rs1] ≥ R[rs2]) PC += SignExt({imm12:1, 1'b0}) 1100011 (99) 101 (5)
bgeu Branch if Greater or Equal Unsigned B if(R[rs1] ≥ R[rs2]) PC += ZeroExt({imm12:1, 1'b0}) 1100011 (99) 111 (7)
blt Branch if Less Than B if(R[rs1] < R[rs2]) PC += SignExt({imm12:1, 1'b0}) 1100011 (99) 100 (4)
bltu Branch if Less Than Unsigned B if(R[rs1] < R[rs2]) PC += ZeroExt({imm12:1, 1'b0}) 1100011 (99) 110 (6)
bne Branch if Not Equal B if(R[rs1] ≠ R[rs2]) PC += SignExt({imm12:1, 1'b0}) 1100011 (99) 001 (1)
ebreak Environment Break I Transfer control to debugger 1110011 (115) 000 (0) 000000000001**
ecall Environment Call I Transfer control to OS 1110011 (115) 000 (0) 000000000000**
jal Jump And Link J R[rd] = PC+4; PC += SignExt({imm20:1, 1'b0}) 1101111 (111)
jalr Jump And Link Reg I R[rd] = PC+4; PC = R[rs1] + SignExt(imm) 1100111 (103) 000 (0)
lb Load Byte I R[rd] = M[R[rs1] + SignExt(imm)]7:0 0000011 (3) 000 (0)
lbu Load Byte Unsigned I R[rd] = M[R[rs1] + ZeroExt(imm)]7:0 0000011 (3) 100 (4)
lh Load Half I R[rd] = M[R[rs1] + SignExt(imm)]15:0 0000011 (3) 001 (1)
lhu Load Half Unsigned I R[rd] = M[R[rs1] + ZeroExt(imm)]15:0 0000011 (3) 101 (5)
lui Load Upper Immediate U R[rd] = imm << 12 0110111 (55)
lw Load Word I R[rd] = M[R[rs1] + SignExt(imm)]31:0 0000011 (3) 010 (2)
or OR R R[rd] = R[rs1] | R[rs2] 0110011 (51) 110 (6) 0000000 (0)
ori OR Immediate I R[rd] = R[rs1] | SignExt(imm) 0010011 (19) 110 (6)
sb Store Byte S M[R[rs1] + SignExt(imm)]7:0 = R[rs2]7:0 0100011 (35) 000 (0)
sh Store Half S M[R[rs1] + SignExt(imm)]15:0 = R[rs2]15:0 0100011 (35) 001 (1)
sll Shift Left Logical R R[rd] = R[rs1] << R[rs2] 0110011 (51) 001 (1) 0000000 (0)
slli Shift Left Logical Immediate I R[rd] = R[rs1] << imm4:0 0010011 (19) 001 (1) 0000000 (0)*
slt Set Less Than R R[rd] = (R[rs1] < R[rs2]) ? 1 : 0 0110011 (51) 010 (2) 0000000 (0)
slti Set Less Than Immediate I R[rd] = (R[rs1] < SignExt(imm)) ? 1 : 0 0010011 (19) 010 (2)
sltiu Set Less Than Immediate Unsigned I R[rd] = (R[rs1] < ZeroExt(imm)) ? 1 : 0 0010011 (19) 011 (3)
sltu Set Less Than Unsigned R R[rd] = (R[rs1] < R[rs2]) ? 1 : 0 0110011 (51) 011 (3) 0000000 (0)
sra Shift Right Arithmetic R R[rd] = R[rs1] >>> R[rs2] 0110011 (51) 101 (5) 0100000 (32)
srai Shift Right Arithmetic Immediate I R[rd] = R[rs1] >> imm4:0 0010011 (19) 101 (5) 0100000 (32)*
srl Shift Right Logical R R[rd] = R[rs1] >> R[rs2] 0110011 (51) 101 (5) 0000000 (0)
srli Shift Right Logical Immediate I R[rd] = R[rs1] >> imm4:0 0010011 (19) 101 (5) 0000000 (0)*
sub SUB R R[rd] = R[rs1] – R[rs2] 0110011 (51) 000 (0) 0100000 (32)
sw Store Word S M[R[rs1] + SignExt(imm)]31:0 = R[rs2]31:0 0100011 (35) 010 (2)
xor XOR R R[rd] = R[rs1] ˆ R[rs2] 0110011 (51) 100 (4) 0000000 (0)
xori XOR Immediate I R[rd] = R[rs1] ˆ SignExt(imm) 0010011 (19) 100 (4)
*
encoded in instr31:25 (imm11:5), the upper 7 bits of the immediate field. **
encoded in instr31:20 (imm11:0), the 12 bits of the immediate field.

RV32m Multiply and Divide Instructions (in alphabetical order)

Mnemonic Name FMT Description (in Verilog) Opcode Funct3 Funct7
div DIVide (signed) R R[rd] = (R[rs1] / R[rs2]) 0110011 (51) 100 (4) 0000001
divu DIVide Unsigned R R[rd] = (R[rs1] / R[rs2]) 0110011 (51) 101 (5) 0000001
mul MULtiply R R[rd] = (R[rs1] * R[rs2]) 0110011 (51) 000 (0) 0000001
rem REMainder (signed) R R[rd] = (R[rs1] % R[rs2]) 0110011 (51) 110 (6) 0000001
remu REMainder Unsigned R R[rd] = (R[rs1] % R[rs2]) 0110011 (51) 111 (7) 0000001
Pseudoinstructions (in alphabetical order)
Pseudoinstruction Name Description (in Verilog) Syntax Base Instruction(s)
beqz Branch if is Equal with Zero if (R[rs1] == 0) PC = label beqz rs1, label beq rs1, x0, label
bgez Branch if Greater or Equan than if (R[rs1] ≥ 0) PC = label bgez rs1, label bge rs1, x0, label
Zero
bgt Branch if Greater Than if (R[rs1] > R[rs2]) PC = label bgt rs1, rs2, label blt rs2, rs1, label
jal x0, label
bgtu Branch if Greater Than, Unsigned if (R[rs1] > R[rs2]) PC = label bgtu rs1, rs2, label bltu rs2, rs1, offset
bgtz Branch if Greater Than Zero if (R[rs1] > 0) PC = label bgtz rs1, label blt x0, rs1, label
ble Branch if Less or Equal if (R[rs1] ≤ R[rs2]) PC = label ble rs1, rs2, label bge rs2, rs1, label
bleu Branch if Less or Equal, if (R[rs1] ≤ R[rs2]) PC = label bleu rs1, rs2, label bgeu rs2, rs1, label
Unsigned
blez Branch if Less or Equan than if (R[rs1] ≤ 0) PC = label blez rs1, label bge x0, rs1, label
Zero
bltz Branch if Less Than Zero if (R[rs1] < 0) PC = label bltz rs1, label blt rs1, x0, label
bnez Branch if nor Equal with Zero if (R[rs1] ≠ 0) PC = label bnez rs1, label bne rs1, x0, label
call CALL nearby function PC = label, ra = PC + 4 call label jal ra, label
call CALL far away function PC = PC + offset, ra = PC + 4 call label auipc ra, offset31:12*
jalr ra, ra, offset11:0
j Jump PC = label j label jal x0, label
jal Jump And Link PC = label, ra = PC + 4 jal label Jal ra, label
jalr Jump And Link Tegister PC = R[rs1], ra = PC + 4 jalr rs1 jalr ra, rs1, 0
jr Jump Register PC = R[rs1] jr rs1 jalr x0, rs1, 0
l{b|h|w} Load Byte/Half/Word R[rd] = [PC + symbol] l{b|h|w} rd, symbol auipc rd, symbol31:12*
l{b|h|w} rd, symbol11:0(rd)
la Load Address of global variable R[rd] = PC + symbol la rd, symbol auipc rd, symbol31:12*
addi rd, rd, symbol11:0
li Load 12-bit Immediate R[rd] = SignExtend(imm11:0) li rd, imm11:0 addi rd, x0, imm11:0
li Load 32-bit Immediate R[rd] = imm31:0 li rd, imm31:0 lui rd, imm31:12*
addi rd, rd, imm11:0
mv MoVe (also called „register copy”) R[rd] = R[rs1] mv rd, rs1 addi rd, rs1, 0
neg NEGate (two’s complement) R[rd] = –R[rs1] neg rd, rs1 sub rd, x0, rs1
nop No OPeration nop addi x0, x0, 0
not NOT (one’s complement) R[rd] = ~R[rs1] not rd, rs1 xori rd, rs1, -1
ret RETurn from function PC = ra ret jalr x0, ra, 0
s{b|h|w} Store Byte/Half/Word [PC + symbol] = R[rs2] s{b|h|w} rs2, symbol, rs1 auipc rs1, symbol31:12*
s{b|h|w} rs2, symbol11:0(rs1)
setz Set if is equal with Zero R[rd] = (R[rs1] == 0) seqz rd, rs1 sltiu rd, rs1, 1
sgtz Set if Greater Than Zero R[rd] = (R[rs1] > 0) sgtz rd, rs1 slt rd, x0, rs1
sltz Set if Less Than Zero R[rd] = (R[rs1] < 0) sltz rd, rs1 slt rd, rs1, x0
snez Set if is Not Equan with Zero R[rd] = (R[rs1] ≠ 0) snez rd, rs1 sltu rd, x0, rs1
*
If bit 11 of the immediate/offset/symbol is 1, the upper immediate is incremented by 1. symbol and offset are the 32-bit PC-relative addresses of a label and
a global variable, respectively.

Register names and numbers Venus Memory Map

Number Name Description Saver
x0 zero constant value of 0 (ZERO) — SP → 0x7FFFFFF0 Stack
x1 ra Return Address Caller 
x2 sp Stack Pointer Callee
x3 gp Global Pointer —
x4 tp Thread Pointer —
x5–x7 t0–t2 Temporary registers Caller
x8 s0 / fp
Saved registers / Frame Pointer Callee 
x9 s1 Saved register Callee 0x10008000 Heap
x10–x11 a0-a1 Function arguments / return Caller
values
x12–x17 a2–a7 Function arguments Caller 0x10000000 Static Data (.data)
x18–x27 s2– Saved registers Callee
s11
x28–x31 t3–t6 Temporary registers Caller PC → 0x00000000 Code (.text)