Introduction

to Digital
Design in
Verilog
Prepared by
Beig Rajibul Hasan &
Md. Asif Hossain Bhuiyan
Lecturer, CSE, BRAC University
 • Attendance (All 6) - 5%
• Class work - 5%
Lab Policy • Lab test - 5%
• Presentation - 10%
• Total - 25%

CSE460 : VLSI Design 2

 • Lab 1 (exp 1) - DSCH2
• Lab 2 (exp 2) - QUARTUS
• Lab 3 (exp 3) - QUARTUS
Lab Policy •
•
Lab 4 (exp 4) - QUARTUS
Lab 5 (exp 5) - QUARTUS
• Lab 6 (exp 6) - MICROWIND2

CSE460 : VLSI Design 3

 • Verilog HDL is a general-purpose hardware
description language which can describe
the digital circuits with C-like syntax.

• Most popular logic synthesis tools support

Verilog HDL Verilog HDL.

• Digital circuits can be described at the RTL

of abstraction which ensures design
portability.

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 Design conception

Design Entry
Schematic
Source Code
Capture
Design
Flowchart Logic
Synthesis

of a Typical a b
Simulation
CAD 0
0
0
1
1
1
1
0

System 1
1
0
1
1
0
0
0
Design
Correct?
No

Yes
Physical
Design

Chip configuration
CSE460 : VLSI Design 5
 • A module is the basic building block of Verilog. A
Basic building module consists of port declaration and Verilog
codes to perform the desired functionality.
block of Verilog
• Ports are means for the Verilog module to
communicate with other modules or interfaces.
Ports can be of 3 types, such as: input, output,
inout.

Input Output
<name> • A typical Verilog module declaration:

module <name> (<ports_list>);

…
// Verilog Codes //
…
endmodule

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Verilog module and ports

Verilog module declaration Logic Synthesis

module encoder_4to2 (x, y, a, b, c, d);

input a, b, c, d; a
output x, y; b x
… encoder_4to2
c y
// Verilog Code //
… d
endmodule

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Basic Syntax and Lexical Conventions
• Documentation in Verilog code
- Documentation can be included in Verilog code by writing comments. A short comment
begins with a double slash ( // ). A long comment spans multiple lines and is contained inside /* and
*/.
module fulladd(s, cout, a, b, cin);
// A full adder verilog module
/*
This module takes three inputs a, b, cin and adds them.
The sum of the inputs are stored in s, the carryout is stored in cout.
*/
input a, b, c;
output s, cout;
// Verilog Code //
endmodule

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Basic Syntax and Lexical Conventions
Identifier Names
• Identifiers are the names of variables and other elements in Verilog code.
• Valid identifier can include any letter and digit as well as “_” and “$” characters. There are two
restrictions too , an identifier must not begin with a digit and it should not be a Verilog keyword.
Furthermore, Verilog is case sensitive.

Identifier name Validity

x1 Valid
x_y Valid
1x Invalid
+y Invalid
x*y Invalid
258 Invalid
ex_$1 Valid
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Basic Syntax and Lexical Conventions
• White space
- White space characters such as SPACE and TAB are ignored by the Verilog compiler.
Although multiple statements can be written in a single line, placing each statement in a single line
and using indentation within blocks of code are good ways to increase readability of the code.

• Number specification
- There are two types of number specifications found in verilog, sized and unsized.
- sized numbers are represented as: <size> ‘<base format> <number>. Supported formats
are:
Base format Illustration
d decimal
b binary
h hexadecimal
o octal
CSE460 : VLSI Design 10
Basic Syntax and Lexical Conventions
- If a number is specified without a base format, it is treated as a decimal number by the
Verilog compiler.
- unsized numbers are specified without a size specification. unsized numbers are assigned
a specific number of bits which is simulator and machine-specific (at least 32 bits).
sized number representation unsized number representation
5’b10001 // This is a 5-bit binary number 1254 // This is a 32-bit decimal number by default
4’hff01 // This is a 4-bit hexadecimal number ‘h21ff // This is a 32-bit hexadecimal number
3’o123 // This is a 3-bit octal number ‘o345 // This is a 32-bit octal number
2’d10 // This is a 2-bit decimal number ‘b1100 // This is a 32-bit binary number

Condition in
• Value Set Value level
Hardware
- Each individual signal/variable in Verilog can be assigned one 0 logic 0 / False
of 4 values: 1 logic 1 / True
x undefined
z high impedance
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How to assign numerical values to the circuit nodes?
❖ Verilog makes use of the reserved keyword assign to easily store numerical values in a variable.
❖ The assign statements are concurrent, meaning that they are executed in parallel.

module in_disp(out, in);

// This module implements a 1-bit buffer

in_disp
input in;
output out;

assign out = in;

endmodule

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 • Vectors
- input or output variables can also be
declared as vectors (multiple bit widths). If bit width is
not specified, the default is scalar (1-bit).
Basic Syntax and - The multibit variables or vectors in general
Lexical Conventions can be declared in Verilog using the syntax:

<data type> <MSB bit index : LSB bit index> <name>

in[0] out[0]

in[1] out[1] module in_disp(out, in);

in[2] out[2] // This module implements a 3-bit buffer

input [2:0]in;
output [2:0]out;

assign out = in;

endmodule
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A simple circuit
and_or

module and_or(x, y, a, b, c, d);

input a, b, c, d;
output x, y;

assign x = a & b;
assign y = c | d;

endmodule

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 example_ckt
Another simple circuit
module example_ckt(f, x1, x2, x3);

input x1, x2, x3;

output f;

wire g, y, h;

assign g = x1 & x2;

assign y = ~x2;
assign h = y & x3; x1 x2 x3 f
assign f = g | h;
0 0 0 0
endmodule 0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
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 • Nets
- Nets represent connections between
hardware elements. Nets are continuously driven
by the outputs of the devices they are connected
to.
- Nets are declared with the keyword
wire. A net is assigned the value z by default.

Basic Syntax and • Registers

Lexical Conventions - In verilog register means a variable that
can hold a value. Unlike net, a register doesn’t
need a driver.
- Registers are declared with the
keyword reg. The default value of a reg data type
is x.
wire a, b; // wire declaration
reg clock; // register declaration

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 • Vectors
- wire or reg type data types can also be
declared as vectors (multiple bit widths). If bit width is
not specified, the default is scalar (1-bit).
- The multibit nets/registers or vectors in
general can be declared in Verilog using the syntax:

Basic Syntax and <data type> <MSB bit index : LSB bit index> <name>

Lexical Conventions module example(a, b);

input b;
output a;
wire [7:0] in1, in2; // 8-bit wire type
variables
reg [0:31] base_clk; // 32-bit reg type
variable
assign a = in1[7] * in2[2];
endmodule
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Verilog Representations of Digital Circuits
Verilog allows designers to describe a digital circuit in several ways. Among them two fundamental
representations are: structural representation and behavioral representation.
• Structural representation
- Structural representation is to use Verilog's gate-level primitives to describe the digital circuit.
Various gate-level primitives are included in Verilog such as: and gate, or gate, not gate, nand gate,
nor gate etc.
• Behavioral representation
- Using gate-level primitives can be tedious while designing larger circuits. Instead, the designers
use more abstract expressions and programming constructs to describe the circuit. This is called the
behavioral representation of the digital circuit.

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 example_ckt
Structural representation
module example_ckt(f,
module example_ckt(f, x1,
x1, x2,
x2, x3);
x3);
input x1,
input x1, x2,
x2, x3;
x3;
output f;
output f;
wire g, y, h;
and(g, x1, x2);
and(g, x2);
not(y, x1, x2);
not(y, x2);
and(h, y, x3);
and(h, y, x3);
or(f,
or(f, g,
g, h);
h); x1 x2 x3 f
endmodule 0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
CSE460 : VLSI Design 1 1 1 1 19
 example_ckt
Behavioral representation

module example_ckt(f, x1, x2, x3);

input x1, x2, x3;
output f;
assign f = (x1 & x2) | (~x2 & x3);
endmodule
x1 x2 x3 f
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
CSE460 : VLSI Design 1 1 1 1 20
 Verilog supports a large number of operators for
carrying out different types of operations.
Verilog operators can be broadly classified into
the following categories:

❑ Bitwise operators
❑ Logical operators
Verilog ❑ Arithmetic operators
Operators ❑ Relational operators
❑ Shift operators
❑ Condition operator

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 Bitwise operators

Operator Operation

~A This will produce 1’s complement of A

-A This will produce 2’s complement of A

Verilog A&B Bitwise AND

Operators A|B Bitwise OR

A^B Bitwise XOR

A^~B / A~^B Bitwise XNOR

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 Logical operators
These operators work on single or multi bit operands
but generate 1 bit result i.e., True or False.

Operator Operation

Verilog !A NOT A(!A) produces “1(True)” only if all bits

of A are 0 else !A gives “0(False)”

Operators A&&B The result of A&&B is “1(True) if both A and

B are nonzero
A|| B A||B gives “1(True)” unless both A and B
are zero.

CSE460 : VLSI Design 23

 Arithmetic operators

Operator Operation
A+B Addition of two single or multibit numbers
Verilog A-B Subtraction of two single or multibit numbers

Operators A*B
A/B
Multiplication of two single or multibit numbers
Division of two single or multibit numbers
A%B This returns the remainder of the integer division A/B

CSE460 : VLSI Design 24

 Relational operators

Operator Operation
A == B 1 (True) if A is equal to B, 0 (False) otherwise
Verilog A != B 1 (True) if A is not equal to B, 0 (False) otherwise

Operators A>B
A<B
1 (True) if A is greater than B, 0 (False) otherwise
1 (True) if A is less than B, 0 (False) otherwise

CSE460 : VLSI Design 25

Verilog Operators

Operator type Symbol Operation performed

Shift right >> Shift right logical (division by 2)

Shift left << Shift left logical (multiplication by 2)

Condition D=A?B:C D is equal to B if A is True, otherwise D is equal to C

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Concurrent Statements
In any HDL, concurrent statement means the code may include a number of statements and each
represent a part of the circuit.
What concurrent means:
Concurrent is used because the statements are considered in parallel and the ordering of statements in
the code doesn’t matter. Most frequently used concurrent statements in Verilog are the continuous
assignments.
module full_add(S, Cout, A, B, Cin);
// This module implements a 1-bit full adder
input A, B, Cin;
output S, Cout;
full_add
assign S = A ^ B ^ Cin;
assign Cout = (A & B) | (Cin & (A ^ B));
endmodule

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Subcircuits in Verilog
• A Verilog module can be included as a subcircuit in another module.
• Both module must be defined in the same file or else Verilog compiler must be told where each module
is located.
• The general form of module instantiation expression is
<module_name> <instance_name> ( <port_name[expressions]>)
• In the above definition
⮚ module_name is the name of the module of the child circuit that is to be included in the parent
circuit.
⮚instance_name can be any legal Verilog identifiers.
⮚port_name basically is the list of ports that specify the connections that will be passed to the
subcircuit.

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4-bit Ripple Carry Adder
stage0 stage1 stage2 stage3

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4-bit Ripple Carry Adder
module fulladd4(S0, S1, S2, S3, Cout, A0, A1, A2, A3, B0, B1, B2, B3, Cin);
input A0, A1, A2, A3, B0, B1, B2, B3, Cin;
output S0, S1, S2, S3, Cout;
wire Cout0, Cout1, Cout2;
fulladd stage0 (S0, Cout0, A0, B0, Cin);
fulladd stage1 (S1, Cout1, A1, B1, Cout0);
fulladd stage2 (S2, Cout2, A2, B2, Cout1);
fulladd stage3 (S3, Cout, A3, B3, Cout2);
endmodule

module fulladd(S, Cout, A, B, Cin);

// This module implements a 1-bit full adder
input A, B, Cin;
output S, Cout;

assign S = A ^ B ^ Cin;
assign Cout = (A & B) | (Cin & (A ^ B));
endmodule

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Text & References

# Title Author(s) Edition

N.H.E. Weste, D. Harris & A.
1. CMOS VLSI Design 4th ed.
Banerjee
Fundamentals of Digital Logic with
2. Stephen Brown & Zvonko Vranesic 2nd/3rd ed.
Verilog Design
Verilog HDL
3. Samir Palnitkar 1st ed.
(A guide to Digital Design and Synthesis)

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Thank You

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