Instruction Set Architecture
Instruction Set Architecture
The Instruction Set Architecture (ISA) is the part of the processor that is visible to the
programmer or compiler writer. The ISA serves as the boundary between software
and hardware. We will briefly describe the instruction sets found in many of the
microprocessors used today. The ISA of a processor can be described using 5
catagories:
in all 3 architectures:
Stack
Accumulator
GPR
Advantages: Makes code generation easy. Data can be stored for long periods in
registers.
Disadvantages: All operands must be named leading to longer instructions.
Earlier CPUs were of the first 2 types but in the last 15 years all CPUs made are GPR
processors. The 2 major reasons are that registers are faster than memory, the more
data that can be kept internally in the CPU the faster the program will run. The other
reason is that registers are easier for a compiler to use.
1. Instructions were of varying length from 1 byte to 6-8 bytes. This causes
problems with the pre-fetching and pipelining of instructions.
2. ALU (Arithmetic Logical Unit) instructions could have operands that were
memory locations. Because the number of cycles it takes to access memory
varies so does the whole instruction. This isn't good for compiler writers,
pipelining and multiple issue.
3. Most ALU instruction had only 2 operands where one of the operands is also
the destination. This means this operand is destroyed during the operation or it
must be saved before somewhere.
Thus in the early 80's the idea of RISC was introduced. The SPARC project was
started at Berkeley and the MIPS project at Stanford. RISC stands for Reduced
Instruction Set Computer. The ISA is composed of instructions that all have exactly
the same size, usually 32 bits. Thus they can be pre-fetched and pipelined
successfully. All ALU instructions have 3 operands which are only registers. The only
memory access is through explicit LOAD/STORE instructions.
Thus A = B + C will be assembled as:
LOAD R1,A
LOAD R2,B
ADD R3,R1,R2
STORE C,R3
The number of registers in RISC is usually 32 or more. The first RISC CPU the MIPS
2000 has 32 GPRs as opposed to 16 in the 68xxx architecture and 8 in the 80x86
architecture. The only disadvantage of RISC is its code size. Usually more
instructions are needed and there is a waste in short instructions (POP, PUSH).
So why are there still CISC CPUs being developed? Why is Intel spending time and
money to manufacture the Pentium II and the Pentium III?
The answer is simple, backward compatibility. The IBM compatible PC is the most
common computer in the world. Intel wanted a CPU that would run all the
applications that are in the hands of more than 100 million users. On the other hand
Motorola which builds the 68xxx series which was used in the Macintosh made the
transition and together with IBM and Apple built the Power PC (PPC) a RISC CPU
which is installed in the new Power Macs. As of now Intel and the PC manufacturers
are making more money but with Microsoft playing in the RISC field as well
(Windows NT runs on Compaq's Alpha) and with the promise of Java the future of
CISC isn't clear at all.
An important lesson that can be learnt here is that superior technology is a factor in
the computer industry, but so are marketing and price as well (if not more).