CSM 2231: Computer Architecture

01: Introduction

Presented By:
Professor Dr. Md. Rakib Hassan
Department of Computer Science and Mathematics
Email: [email protected]
Text Books
 D. A. Patterson and J. L. Hennessy, “Computer Organization & Design, the
Hardware/Software Interface”, 5th Edition, Morgan Kaufman (Elsevier),
2014.
 D. A. Patterson and J. L. Hennessy, " Computer Architecture: A Quantitative
Approach", 6th edition. Morgan Kaufman (Elsevier), 2019.
 D. A. Patterson and J. L. Hennessy, “Computer Organization and Design
ARM Edition”, 1st Edition, Morgan Kaufman (Elsevier), 2016.
 D. A. Patterson and J. L. Hennessy, “Computer Organization and Design
RISC-V Edition”, 2nd Edition, Morgan Kaufman (Elsevier), 2020.
 D. A. Patterson and J. L. Hennessy, “Computer Organization and Design
MIPS Edition”, 6th Edition, Morgan Kaufman (Elsevier), 2020.
 William Stallings, “Computer Organization and Architecture”, 10th Edition,
2015.
 Jim Ledin and Dave Farley, “Modern Computer Architecture and
Organization: Learn x86, ARM, and RISC-V architectures and the design of
smartphones, PCs, and cloud servers”, 2nd Edition, 2022.

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The Concept of a Computer

Application software

Systems software
User
Hardware

Operating system
compiler
assembler
Programs user
writes and runs

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 Software
Compiler Assembler

Application software, MIPS compiler output, MIPS binary machine code:

a program in C: assembly language program:
00000000101000010000000000011000
00000000000110000001100000100001
swap (int v[ ], int k) swap; 10001100011000100000000000000000
{int temp; muli $2, $5, 4 10001100111100100000000000000100
10101100111100100000000000000000
temp = v[k]; add $2, $4, $2 10101100011000100000000000000100
v[k] = v[k+1]; lw $15, 0 ($2) 00000011111000000000000000001000
v[k+1] = temp; lw $16, 4 ($2)
} sw $16, 0 ($2)
sw $15, 4 ($2)
jr $31

• MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction

set computer (RISC) instruction set architectures (ISA)

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The Hardware of a Computer

Input
Control

Datapath Memory
Central Processing
Unit (CPU)
or “processor” Output

5 pieces of hardware

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Instruction Set Architecture (ISA)
A set of assembly language instructions (ISA) provides a link
between software and hardware.
Given an instruction set, software programmers and hardware
engineers work more or less independently.
ISA is designed to extract the most performance out of the
available hardware technology.

Instruction
set
Software Hardware

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ISA
Defines registers
Defines data transfer modes between registers, memory
and I/O
Types of ISA:
oRISC (Reduced Instruction Set Computers)
oCISC (Complex Instruction Set Computers)
oVLIW (Very long instruction word)
oSuperscalar (Method of parallel computing)
Examples:
oIBM370/X86/Pentium/K6 (CISC)
oPowerPC (Superscalar)
oAlpha (Superscalar)
oMIPS (RISC and Superscalar)
oSparc (RISC), UltraSparc (Superscalar)

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Computer Architecture
Architecture:
o System attributes that have a direct impact on the logical execution of a
program
o It is concerned with optimizing the performance of a computer system and
ensuring that it can execute instructions quickly and efficiently

Architecture is visible to a programmer:

o Instruction set
o Data representation
o I/O mechanisms
o Memory addressing

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Computer Organization
Organization:
o Physical details that are transparent to a programmer, such as (Hardware
implementation of an instruction, Control signals, Memory technology
used)
o It refers to the operational units and their interconnections that
implement the architecture specification

Example: System/370 architecture has been used in many IBM

computers, which widely differ in their organization.

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Historic Events
1623, 1642: Wilhelm Schickard (1592-1635, Germany) and
Blaise Pascal (1623-1662, France) built mechanical counters
with carry.
1823-34: Charles Babbage (1971-1871, UK) designed a
difference engine.
http://www.youtube.com/watch?v=0anIyVGeWOI&feature=rel
ated
o Weight: 5 ton; No. of Parts: 8,000; Dimension: 11 ft long, 8 ft high

1941: Conrad Zuse (1910-1995, Germany) built Z3, the first

working programmable computer, built in Germany.

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Z3

Conrad Zuse
Z1 (1938)
Z2 (1939)
Z3 (1941)
∙
∙
∙

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Historic Events
 1942: Vincent Atanasoff (Professor) (1903-
1995, USA) and Clifford Barry (graduate
assistant) (1918-1963, USA) built the first
electronic computer (ABC: Atanasoff Berry
Computer) at Iowa State College.
 1943-44: John Mauchly (Professor) and J.
Presper Eckert (graduate student) built
ENIAC at U. Pennsylvania.
 1944: Howard Aiken (1900-1973, USA) used
“separate data and program memories” in
MARK I – IV computers – Harvard
Architecture.
 1945-52: John von Neumann (1903-1957,
Hungarian-American) proposed a “stored
program computer” EDVAC (Electronic
Discrete Variable Automatic Computer) –
Von Neumann Architecture – use the same
memory for program and data.

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The Atanasoff Story
The First Electronic Computer, the Atanasoff Story, by Alice R.
Burks and Arthur W. Burks, Ann Arbor, Michigan: The
University of Michigan Press, 1991.
The Man Who Invented the Computer: The Biography of John
Atanasoff, Digital Pioneer, by Jane Smiley, 256 pages,
Doubleday, $25.95.

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National Medal of Technology 1990
John Vincent Atanasoff (1903–1995)

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History Continues
 1946-52: Von Neumann built the IAS
(Institute for Advanced Study)
computer at the Institute of
Advanced Studies, Princeton – A
prototype for most future computers.

 1947-50: Eckert-Mauchly Computer

Corp. built UNIVAC I (Universal
Automatic Computer), used in the
1950 census.

 1949: Maurice Wilkes (1913-2010,

UK) built EDSAC (Electronic Delay
Storage Automatic Calculator), the
first stored-program computer.

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First General-Purpose Computer
Electronic Numerical
Integrator and Calculator
(ENIAC) built in World War II
was the first general purpose
computer
o Used for computing artillery firing
tables
o 80 feet long, 8.5 feet high and
several feet wide
o Twenty 10 digit registers, each 2
feet long
o Used 18,000 vacuum tubes
o 5,000 additions/second
© 2004 Morgan Kaufman Publishers
o Weight: 30 tons
o Power consumption: 140kW

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First-Generation Computers
Late 1940s and 1950s
Stored-program computers
Vacuum tubes were used for digital logic elements and
memory
Programmed in assembly language
Used magnetic devices and earlier forms of memories
Examples: IAS, ENIAC, EDVAC, UNIVAC, Mark I, IBM 701

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IAS Computer
Fundamental design approach was the stored program concept
o Attributed to the mathematician John von Neumann
o First publication of the idea was in 1945 for the EDVAC

Design began at the Princeton Institute for Advanced Studies

Completed in 1952
Prototype of all subsequent general-purpose computers

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IAS Structure

CA: Central Arithmetic

CC: Central Control

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The Organization of IAS Computer
Accumulator (AC) Multiplier/Quotient (MQ) Input/

DATAPATH
Output
Equipment
Arithmetic Logic Circuits

Memory Buffer Register (MBR)

Instr. Buffer (IBR) Program Counter (PC) Main

Memory
(M)
Instruction Register (IR) Memory Address Reg. (MAR) 212 x 40 bit
words
Control Control
Circuit Signals CONTROL UNIT

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IAS Computer Machine Language
40-bit word, two machine instructions per word.

Left instruction Right instruction

bit 0 7 8 19 20 27 28 39

8-bit opcode 12-bit memory address

(operand)

Ref: J. P. Hayes, Computer Architecture and Organization, New York:

McGraw-Hill, 1978.

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How IAS Computer Adds Two Numbers
Suppose the numbers are stored in memory locations 100 and
101, and
The sum is to be saved in memory location 102
Instruction Opcode Description
LOAD M(100) 00000001 AC ← M(100)
ADD M(101) 00000101 AC ← AC + M(101)
STOR M(102) 00100001 M(102) ← AC

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IAS Computer Machine Code

00000001 000001100100 00000101 000001100101

Load 100 Add 101

00100001 000001100110 00000000 000000000000

Stor 102 Stop

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Executing the Program
Accumulator (AC) Multiplier/Quotient (MQ) Input/

DATAPATH
Output
Equipment
Arithmetic Logic Circuits

Memory Buffer Register (MBR)

Instr. Buffer (IBR) Program Counter (PC) Main

Memory
(M)
Instruction Register (IR) Memory Address Reg. (MAR) 212 x 40 bit
words
Control Control
Circuit Signals CONTROL UNIT

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IAS Instruction Cycles
The IAS operates by repetitively performing an instruction
cycle.
Each instruction cycle consists of two sub-cycles:
o Fetch
o Execute

During the fetch cycle,

o The opcode of the next instruction is loaded into the IR and the address
portion is loaded into the MAR.
o This instruction may be taken from the IBR, or it can be obtained from
memory by loading a word into the MBR, and then down to the IBR, IR,
and MAR.

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IAS Instruction Cycles (Cont.)
Execute cycle:
o Once the opcode is in the IR, the execute cycle is performed.
o Control circuitry interprets the opcode and executes the instruction by
sending out the appropriate control signals to cause data to be moved or
an operation to be performed by the ALU.

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Partial flowchart of IAS
operation

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IAS instruction set

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Hardware Contains
Data storage devices
 Memory
 Registers

Instruction decoding and execution devices

 Execution unit (arithmetic logic unit or ALU)
 Data transfer buses
 Control unit

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 Registers in IAS
Size
Register Function
(bits)
Program counter (PC) 12 Holds mem. address of next instruction
Accumulator (AC) 40 Temporary data storage
Multiplier quotient (MQ) 40 Temporary data storage
Memory buffer (MBR) 40 Memory read / write data
Instruction buffer (IBR) 20 Holds right instr. (bits 20-39)
Instruction register (IR) 8 Holds opcode part of instruction
Memory address (MAR) 12 Holds mem. address part of instruction

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Register Transfer
Transfer data synchronously with clock
 Register to register
 Register to register through ALU logic
 Registers to register through memory (write)
 Register to register through memory (read)

Data transfer through communication bus

 Source register writes on bus
 Destination register reads from bus
 Control circuit provides read / write signals for bus and memory

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Von Neumann Bottleneck
Von Neumann architecture uses the same memory for
instructions (program) and data.
The time spent in memory accesses can limit the performance.
This phenomenon is referred to as von Neumann bottleneck.
To avoid the bottleneck, later architectures restrict most
operands to registers (temporary storage in processor).

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John von Neumann (1903-1957)

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Second Generation Computers
1955 to 1964
Transistor replaced vacuum tubes
Magnetic core memories
Floating-point arithmetic
High-level languages used: ALGOL, COBOL and FORTRAN
System software: compilers, subroutine libraries, batch
processing
Example: IBM 7094

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IBM 7094 Configuration

*Multiplexer/ Multiplexor:
Both are used

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Third Generation Computers
Beyond 1965
Integrated circuit (IC) technology
Semiconductor memories
Memory hierarchy, virtual memories and caches
Time-sharing
Parallel processing and pipelining
Microprogramming
Examples: IBM 360 and 370, CYBER, ILLIAC IV, DEC PDP and
VAX, Amdahl 470

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IBM 370 Architecture
Was introduced in 1970
Included a number of models
Could upgrade to a more expensive, faster model without
having to abandon original software
New models are introduced with improved technology, but
retain the same architecture so that the customer’s software
investment is protected
Architecture has survived to this day as the architecture of
IBM’s mainframe product line

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Integrated Circuits
 Data storage – provided by memory cells
 Data processing – provided by gates
 Data movement – the paths among components are used to move data
from memory to memory and from memory through gates to memory
 Control – the paths among components can carry control signals
 A computer consists of gates, memory cells, and interconnections among
these elements
 The gates and memory cells are constructed of simple digital electronic
components
 Exploits the fact that such components as transistors, resistors, and
conductors can be fabricated from a semiconductor such as silicon
 Many transistors can be produced at the same time on a single wafer of
silicon
 Transistors can be connected with a processor metallization to form circuits

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Relationship among Wafer, Chip, and Gate

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Moore’s Law
1965: Gordon Moore – co-founder of Intel
Observed number of transistors that could be put on a single
chip was doubling every year
o The pace slowed to a doubling every 18 months in the 1970’s but has
sustained that rate ever since

Consequences of Moore’s law

o The cost of computer logic and memory circuitry has fallen at a dramatic
rate
o The electrical path length is shortened, increasing operating speed
o Computer becomes smaller and is more convenient to use in a variety of
environments
o Reduction in power and cooling requirements
o Fewer interchip connections

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Transistor Count

* TSMC: Taiwan Semiconductor Manufacturing Company Limited

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Chip Size

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4th Generation
Personal computers
Laptops and Palmtops
Networking and wireless
SOC (System-on-a-Chip) and MEMS (Micro-electromechanical
systems) technology
And the future!
 Quantum computing

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Computer Generations

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Structure and Function
Hierarchical system
o Set of interrelated subsystems
o Hierarchical nature of complex systems is essential to both their design
and their description

Designer need only deal with a particular level of the system at

a time
o Concerned with structure and function at each level

Structure
o The way in which components relate to each other

Function
o The operation of individual components as part of the structure

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Function
There are four basic functions that a computer can perform:
o Data processing
 Data may take a wide variety of forms and the range of processing requirements
is broad
o Data storage
 Short-term
 Long-term
o Data movement
 Input-output (I/O) - when data are received from or delivered to a device
(peripheral) that is directly connected to the computer
 Data communications – when data are moved over longer distances, to or from a
remote device
o Control
 A control unit manages the computer’s resources and orchestrates the
performance of its functional parts in response to instructions

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Structure

Top-down view of a computer

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4 Structural Components
 CPU
o Controls the operation of the computer and performs its data processing
functions

 Main Memory
o Stores data

 I/O
o Moves data between the computer and its external environment

 System Interconnection
o Some mechanism that provides for communication among CPU, main
memory, and I/O

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CPU – Structural Components
Control Unit
o Controls the operation of the CPU and hence the computer

Arithmetic and Logic Unit (ALU)

o Performs the computer’s data processing function

Registers
o Provide storage internal to the CPU

CPU Interconnection
o Some mechanism that provides for communication among the control
unit, ALU, and registers

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Multicore Computer Structure
Central processing unit (CPU)
o Portion of the computer that fetches and executes instructions
o Consists of an ALU, a control unit, and registers
o Referred to as a processor in a system with a single processing unit

Core
o An individual processing unit on a processor chip
o May be equivalent in functionality to a CPU on a single-CPU system
o Specialized processing units are also referred to as cores

Processor
o A physical piece of silicon containing one or more cores
o Is the computer component that interprets and executes instructions
o Referred to as a multicore processor if it contains multiple cores

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Cache Memory
Multiple layers of memory between the processor and main
memory
Is smaller and faster than main memory
Used to speed up memory access by placing in the cache data
from main memory that is likely to be used in the near future
A greater performance improvement may be obtained by using
multiple levels of cache, with level 1 (L1) closest to the core
and additional levels (L2, L3, etc.) progressively farther from
the core

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Multicore

Simplified view of
major elements of a
multicore computer

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Motherboard with Two Intel Quad-Core Xeon
Processors

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 zEnterprise EC12 Processor Unit (PU)
Chip Diagram

SC: Storage Control

GX: I/O bus controller

Announced
in 2012

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zEnterprise EC12 Core Layout

IDU: Instruction sequence unit

IFU: Instruction fetch unit
IDU: Instruction decode unit
LSU: Load-store unit
XU: Translation unit
FXU: Fixed-point unit
BFU: Binary floating point unit
DFU: Decimal floating-point unit
RU: Recovery unit

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Microprocessors
The density of elements on processor chips continued to rise
o More and more elements were placed on each chip so that fewer and
fewer chips were needed to construct a single computer processor

1971 Intel developed 4004

o First chip to contain all of the components of a CPU on a single chip
o Birth of microprocessor

1972 Intel developed 8008

o First 8-bit microprocessor

1974 Intel developed 8080

o First general purpose microprocessor
o Faster, has a richer instruction set, has a large addressing capability

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Evolution of Intel Microprocessors – 1970s

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Evolution of Intel Microprocessors – 1980s

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Evolution of Intel Microprocessors – 1990s

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Evolution of Intel Microprocessors – Recent

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Intel i9 13th Generation: 13900K
Introduced: 2022
Clock Speed: 5.8 GHz
Bus width: 26 billion
Feature size (nm): 10
Addressable memory: 192 GB
Cache memory: 36 MB
Cores: 24

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Evolution of the Intel x86 Architecture
Two processor families are the Intel x86 and the ARM
architectures
Current x86 offerings represent the results of decades of
design effort on complex instruction set computers (CISCs)
An alternative approach to processor design is the reduced
instruction set computer (RISC)
ARM architecture is used in a wide variety of embedded
systems and is one of the most powerful and best-designed
RISC-based systems on the market

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ARM
Advanced RISC Machines and originally Acorn RISC Machine
Family of RISC instruction set architectures (ISAs) for computer
processors
Refers to a processor architecture that has evolved from RISC
design principles and is used in embedded systems
Family of RISC-based microprocessors and microcontrollers
designed by ARM Holdings, Cambridge, England
Chips are high-speed processors that are known for their small
die size and low power requirements
Indeed the most widely used processor architecture of any
kind in the world
o Apple M series, iPhone, Nvidia Grace, Snapdragon (Qualcomm), Samsung
Electronics, etc.

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RISC vs CISC
RISC CISC
Elaboration Reduced Instruction Set Complex Instruction Set
Computer Computer
Performance optimization Software Hardware
Register set to store the Multiple Single
instruction
Decoding of instruction Simple Complex

Execution time Short Long

Instruction format Fixed Variable
RAM requirement More Less
Power Requirement Low High
Example ARM, PA-RISC, Power Intel x86, AMD, VAX,
architecture, SPARC Motorola 68000 family

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MIPS vs RISC-V
MIPS and RISC-V are quite similar
o But RISC-V is like an improved version (more versatile and expandable)

RISC-V specification is open source and many companies are

building things using it
o In December 2018, Wave Computing, the new owner of the MIPS
architecture, announced that MIPS ISA would be open-sourced in a
program dubbed the MIPS Open initiative

RISC-V is the fifth iteration of RISC-I

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