Digital Systems Design Using VHDL 3rd Edition Charles H. Roth - Ebook PDF Download
Digital Systems Design Using VHDL 3rd Edition Charles H. Roth - Ebook PDF Download
https://ebooksecure.com/download/digital-systems-design-using-
vhdl-ebook-pdf/
https://ebooksecure.com/download/digital-systems-design-using-
vhdl-3rd-edition-ebook-pdf/
https://ebooksecure.com/download/analog-and-digital-
electronics-1st-edition-ebook-pdf/
https://ebooksecure.com/download/fundamentals-of-logic-design-
enhanced-edition-ebook-pdf/
https://ebooksecure.com/download/digital-system-design-with-fpga-
implementation-using-verilog-and-vhdl-ebook-pdf/
(eBook PDF) Digital Design with RTL Design VHDL and
Verilog 2nd
http://ebooksecure.com/product/ebook-pdf-digital-design-with-rtl-
design-vhdl-and-verilog-2nd/
https://ebooksecure.com/download/design-recipes-for-fpgas-using-
verilog-and-vhdl-2nd-ed-ebook-pdf/
http://ebooksecure.com/product/ebook-pdf-digital-design-with-an-
introduction-to-the-verilog-hdl-vhdl-and-systemverilog-6th-
edition/
http://ebooksecure.com/product/ebook-pdf-digital-systems-
engineering/
https://ebooksecure.com/download/digital-image-processing-using-
matlab-ebook-pdf/
Third Edition
Third Edition
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
Digital Systems Design Using VHDL®, © 2018, 2008 Cengage Learning®
Third Edition
ALL RIGHTS RESERVED. No part of this work covered by the copyright
Charles H. Roth, Jr. and Lizy Kurian John
herein may be reproduced or distributed in any form or by any means,
Product Director, Global Engineering: except as permitted by U.S. copyright law, without the prior written
Timothy L. Anderson permission of the copyright owner.
Associate Media Content Developer:
ARM® is a registered trademark of ARM Limited. “ARM” is used to
Ashley Kaupert
represent ARM Holding plc; its operating company ARM Limited; and
Product Assistant: Alexander Sham its regional subsidiaries. ARM, the ARM logo, and AMBA are registered
Marketing Manager: Kristin Stine trademarks of ARM Limited. All rights reserved.
Director, Higher Education Production:
Sharon L. Smith For product information and technology assistance, contact us at
Cengage Learning Customer & Sales Support, 1-800-354-9706.
Content Project Manager: Jana Lewis
For permission to use material from this text or product,
Production Service: RPK Editorial submit all requests online at www.cengage.com/permissions.
Services, Inc. Further permissions questions can be emailed to
Copyeditor: Harlan James [email protected].
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
CONTENTS
Preface vii
About the Authors xii
Chapter 1 Review of Logic Design Fundamentals 1
1.1 Combinational Logic 1
1.2 Boolean Algebra and Algebraic Simplification 3
1.3 Karnaugh Maps 7
1.4 Designing With NAND and NOR Gates 10
1.5 Hazards in Combinational Circuits 12
1.6 Flip-Flops and Latches 16
1.7 Mealy Sequential Circuit Design 18
1.8 Moore Sequential Circuit Design 25
1.9 Equivalent States and Reduction of State Tables 28
1.10 Sequential Circuit Timing 30
1.11 Tristate Logic and Busses 31
Problems 34
2.17 Arrays 97
2.18 Loops in VHDL 101
2.19 Assert and Report Statements 102
2.20 Tips for Debugging VHDL Code 106
Problems 114
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
Contents v
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
vi Contents
Appendix A 596
VHDL Language Summary
Appendix B 604
IEEE Standard Libraries
Appendix C 606
TEXTIO Package
Appendix D 608
Projects
References 618
Index 622
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
PREFACE
This textbook is intended for a senior-level course in digital systems design. The book covers
both basic principles of digital system design and the use of a hardware description language,
VHDL, in the design process. After basic principles have been covered, students are encour-
aged to practice design by going through the design process. For this reason, many digital
system design examples, ranging in complexity from a simple binary adder to a microproces-
sor, are included in the text.
Students using this textbook should have completed a course in the fundamentals of logic
design, including both combinational and sequential circuits. Although no previous knowl-
edge of VHDL is assumed, students should have programming experience using a modern
higher-level language such as C. A course in assembly language programming and basic
computer organization is also very helpful, especially for Chapter 9.
This book is the result of many years of teaching a senior course in digital systems design
at the University of Texas at Austin. Throughout the years, the technology for hardware
implementation of digital systems has kept changing, but many of the same design principles
are still applicable. In the early years of the course, we handwired modules consisting of
discrete transistors to implement our designs. Then integrated circuits were introduced,
and we were able to implement our designs using breadboards and TTL logic. Now we are
able to use FPGAs and CPLDs to realize very complex designs. We originally used our own
hardware description language together with a simulator running on a mainframe computer.
When VHDL was adopted as an IEEE standard and became widely used in industry, we
switched to VHDL. The widespread availability of high-quality commercial CAD tools now
enables us to synthesize complex designs directly from the VHDL code.
All of the VHDL code in this textbook has been tested using the Modelsim simula-
tor. The Modelsim software is available in a student edition, and we recommend its use in
conjunction with this text. The companion website that accompanies this text provides a
link for downloading the Modelsim student edition and an introductory tutorial to help
students get started using the software. Students can access these materials by visiting
https://login.cengage.com.
Structure
Because students typically take their first course in logic design two years before this course,
most students need a review of the basics. For this reason, Chapter 1 includes a review of
logic design fundamentals. Most students can review this material on their own, so it is unnec-
essary to devote much lecture time to this chapter.
vii
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
viii Preface
Chapter 2 starts with an overview of modern design flow. It also summarizes various
technologies for implementation of digital designs. Then, it introduces the basics of VHDL,
and this hardware description language is used throughout the rest of the book. Additional
features of VHDL are introduced on an as-needed basis, and more advanced features are
covered in Chapter 8. From the start, we relate the constructs of VHDL to the corresponding
hardware. Some textbooks teach VHDL as a programming language and devote many pages
to teaching the language syntax. Instead, our emphasis is on how to use VHDL in the digital
design process. The language is very complex, so we do not attempt to cover all its features.
We emphasize the basic features that are necessary for digital design and omit some of the
less-used features. Use of standard IEEE VHDL libraries is introduced in this chapter and
only IEEE standard libraries are used throughout the test. Chapter 2 also provides coding tips
and strategies on how to write VHDL code that can lead to the intended hardware quickly.
VHDL is very useful in teaching top-down design. We can design a system at a high level
and express the algorithms in VHDL. We can then simulate and debug the designs at this
level before proceeding with the detailed logic design. However, no design is complete until
it has actually been implemented in hardware and the hardware has been tested. For this
reason, we recommend that the course include some lab exercises in which designs are imple-
mented in hardware. We introduce simple programmable logic devices (PLDs) in Chapter 3
so that real hardware can be used early in the course if desired. Chapter 3 starts with an
overview of programmable logic devices and presents simple programmable logic devices
first, followed by an introduction to complex programmable logic devices (CPLDs) and
Field Programmable Gate Arrays (FPGAs). There are many products in the market, and it
is useful for students to learn about commercial products. However, it is more important for
them to understand the basic principles in the construction of these programmable devices.
Hence we present the material in a generalized fashion, with references to specific products
as examples. The material in this chapter also serves as an introduction to the more detailed
treatment of FPGAs in Chapter 6.
Chapter 4 presents a variety of design examples, including both arithmetic and non-
arithmetic examples. Simple examples such as a BCD to 7-segment display decoder to more
complex examples such as game scoreboards, keypad scanners, and binary dividers are pre-
sented. The chapter presents common techniques used for computer arithmetic, including
carry look-ahead addition and binary multiplication and division. Use of a state machine for
sequencing the operations in a digital system is an important concept presented in this chap-
ter. Synthesizable VHDL code is presented for the various designs. A variety of examples are
presented so that instructors can select their favorite designs for teaching.
Use of sequential machine charts (SM charts) as an alternative to state graphs is covered
in Chapter 5. We show how to write VHDL code based on SM charts and how to realize hard-
ware to implement the SM charts. Then, the technique of microprogramming is presented.
Transformation of SM charts for different types of microprogramming is discussed. Then, we
show how the use of linked state machines facilitates the decomposition of complex systems
into simpler ones. The design of a dice-game simulator is used to illustrate these techniques.
Chapter 6 presents issues related to implementing digital systems in Field Programmable
Gate Arrays. A few simple designs are first hand-mapped into FPGA building blocks to illus-
trate the mapping process. Shannon’s expansion for decomposition of functions with several
variables into smaller functions is presented. Features of modern FPGAs like carry chains,
cascade chains, dedicated memory, dedicated multipliers, etc., are then presented. Instead
of describing all features in a selected commercial product, the features are described in a
general fashion. Once students understand the fundamental general principles, they will be
able to understand and use any commercial product they have to work with. This chapter
also introduces the processes and algorithms in the software design flow. Synthesis, mapping,
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
Preface ix
placement, and routing processes are briefly described. Optimizations during synthesis are
illustrated.
Basic techniques for floating-point arithmetic are described in Chapter 7. We present a
simple floating-point format with 2’s complement numbers and then the IEEE standard float-
ing-point formats. A floating-point multiplier example is presented starting with development
of the basic algorithm, then simulating the system using VHDL, and finally synthesizing and
implementing the system using an FPGA. Some instructors may prefer to cover Chapters 8
and 9 before teaching Chapter 7. Chapter 7 can be omitted without loss of any continuity.
By the time students reach Chapter 8, they should be thoroughly familiar with the basics
of VHDL. At this point we introduce some of the more advanced features of VHDL and
illustrate their use. The use of multi-valued logic, including the IEEE-1164 standard logic, is
one of the important topics covered. A memory model with tri-state output busses illustrates
the use of the multi-valued logic.
Chapter 9 presents the design of a microprocessor, starting from the description of the
instruction set architecture (ISA). The processor is an early RISC processor, the MIPS
R2000. The important instructions in the MIPS ISA are described and a subset is then imple-
mented. The design of the various components of the processor, such as the instruction mem-
ory module, data memory module, and register file are illustrated module by module. These
components are then integrated together, and a complete processor design is presented.
The model can be tested with a test bench, or it can be synthesized and implemented on an
FPGA. In order to test the design on an FPGA, one will need to write input-output mod-
ules for the design. This example requires understanding of the basics of assembly language
programming and computer organization. After presenting the MIPS design, the chapter
progresses to a design with the ARM ISA. A simplified introduction to the ARM ISA is first
presented, followed by an implementation of a subset of the ISA. This is a significant addition
to the previous MIPS design. The coverage is augmented with relevant example questions,
solutions, and exercise problems on the ARM ISA.
Chapter 10 is a new chapter, presenting new material on verification, a concept central to
the design of complex systems. A good understanding of timing in sequential circuits and the
principles of synchronous design is essential to the digital system design process. Functional
verification is introduced, explaining jargon in verification, validation, emulation, and distinc-
tion with testing. Self-testing test benches are explained. Concept of coverage is introduced.
Timing verification is presented with static timing analysis of circuits. Clock skew, clock
gating, power gating, and asynchronous design are introduced.
The important topics of hardware testing and design for testability are covered in
Chapter 11. This chapter introduces the basic techniques for testing combinational and
sequential logic. Then scan design and boundary-scan techniques, which facilitate the testing
of digital systems, are described. The chapter concludes with a discussion of built-in self-test
(BIST). VHDL code for a boundary-scan example and for a BIST example is included. The
topics in this chapter play an important role in digital system design, and we recommend that
they be included in any course on this subject. Chapter 11 can be covered any time after the
completion of Chapter 8.
Chapter 12, available only online via https://login.cengage.com, presents three complete
design examples that illustrate the use of VHDL synthesis tools. First, a wristwatch design
shows the progress of a design from a textual description to a state diagram and then a
VHDL model. This example illustrates modular design. The test bench for the wristwatch
illustrates the use of multiple procedure calls to facilitate the testing. The second example
describes the use of VHDL to model RAM memories. The third example, a serial communi-
cations receiver-transmitter, should easily be understood by any student who has completed
the material through Chapter 8.
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
x Preface
Chapter 1 Logic hazard description is improved. More detailed examples on static haz-
ards are added. Students are introduced to memristors. The sequential circuit
timing section is kept to an introductory level because more elaborate static
timing analysis is presented in a new chapter on verification, Chapter 10.
Chapter 2 Coding examples to improve test bench creation are introduced in Chapter 2.
Coding tips and strategies for synthesizable code are presented. Multiple
debugging examples are presented towards the end of the chapter.
Chapter 3 Information on commercial chips updated to reflect state of the art. Added
introduction to programmable System on a Chip (SoC).
Chapter 4 General introduction to parallel prefix adders with details of Kogge Stone
adder. New exercise problems including those on Kogge Stone and Brent-
Kung adders.
Chapter 5 Added historical perspective on microprogramming. New example problems
and new exercise problems.
Chapter 6 Information on commercial chips updated to reflect state of the art. Xilinx
Kintex chips described. New problems added to make use of the new types
of FPGA architectures.
Chapter 7 Several new example problems on IEEE floating point standards illustrated
in detail. Rounding modes in IEEE standard and Microsoft Excel illustrated
with examples. Several new exercise problems.
Chapter 8 Functions and procedures from the prior edition’s Chapter 2 moved to here.
Many sections from old Chapter 8 are still here. A memory model previously
in old Chapter 9 presented as example of multi-valued logic design in new
Chapter 8.
New examples on functions and procedures added. VHDL function NOW is
introduced. New exercise questions on Kogge-Stone and Brent-Kung adder
to utilize advanced VHDL features such as generate are added.
Chapter 9 This chapter covers ARM processor design. A simplified introduction to the
ARM ISA is first presented followed by an implementation of a subset of
the ISA. This is a significant addition to the MIPS design that was previously
presented. Several example questions and solutions on the ARM ISA are
presented. Several exercise problems are added.
Chapter 10 This is a new chapter on verification. It covers functional verification as
introduced, explaining terminology in verification, validation, emulation,
and distinction with testing. Self-checking test benches are explained. Con-
cept of coverage is introduced. Timing verification is presented with static
timing analysis of circuits. Clock skew, clock gating, power gating, and asyn-
chronous design are briefly presented. Exercise problems cover functional
and timing verification.
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
Preface xi
Instructor Resources
A detailed Instructor’s Solutions Manual containing solutions to all the exercises from the
text, VHDL code used in the book, and Lecture Note PowerPoint slides are available via a
secure, password-protected Instructor Resource Center at https://login.cengage.com.
Acknowledgments
We would like to thank the many individuals who have contributed their time and effort
to the development of this textbook. Over many years we have received valuable feedback
from the students in our digital systems design courses. We would especially like to thank
the faculty members who reviewed the previous edition and offered many suggestions for its
improvement. These faculty include:
Lee Belfore, Old Dominion University
Gang Feng, University of Wisconsin, Platteville
K. Gopalan, Purdue University, Calumet
Miriam Leeser, Northeastern University
Melissa C. Smith, Clemson University
Aaron Striegel, University of Notre Dame
Don Thomas, Carnegie Mellon University
We also wish to acknowledge Dr. Nur Touba’s comments on various parts of the book.
Dr. Earl Swartzlander provided comments on the parallel prefix adder section.
We thank ARM Limited for providing the permission to include an example design
based on the ARM ISA in Chapter 9. Special thanks go to Ian Burgess at Mentor Graphics
for his work on the ModelSim code. We also take this opportunity to express our gratitude
to the student assistants who helped with the word processing, VHDL code testing, and
illustrations: Arif Mondal, Kevin Johns, Jae-Min Jo, Di Xie, Poulami Das, and Kangjoo Lee,
who helped on this version, and Roger Chen, William Earle, Manish Kapadia, Matt Morgan,
Elizabeth Norris, and Raman Suri, who helped on the previous edition.
We wish to acknowledge and thank our Global Engineering team at Cengage Learning for
their dedication to this new book: Timothy Anderson, Product Director; Ashley Kaupert, Asso-
ciate Media Content Developer; Jana Lewis, Content Project Manager; Kristin Stine, Market-
ing Manager; Elizabeth Brown and Brittany Burden, Learning Solutions Specialists; Alexander
Sham, Product Assistant; and Rose Kernan of RPK Editorial Services, Inc. They have skillfully
guided every aspect of this text’s development and production to successful completion.
Charles. H. Roth, Jr.
Lizy K. John
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
ABOUT THE AUTHORS
xii
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
CHAPTER
This chapter reviews many of the logic design topics normally taught in a first course in logic
design. First, combinational logic and then sequential logic are reviewed. Combinational
logic has no memory, so the present output depends only on the present input. Sequential
logic has memory, so the present output depends not only on the present input but also on
the past sequence of inputs. Various types of flip-flops and their state tables are presented.
Example designs for Mealy and Moore sequential circuits are illustrated, followed by tech-
niques to reduce the number of states in sequential designs. Circuit timing and synchronous
design are particularly important, since a good understanding of timing issues is essential to
the successful design of digital systems. A detailed treatment of sequential circuit timing is
presented in Chapter 10 in a section on timing verification. For more details on any of the
topics discussed in this chapter, the reader should refer to a standard logic design textbook
such as Roth and Kinney, Fundamentals of Logic Design, 7th Edition (Cengage Learning,
2014). Some of the review examples that follow are referenced in later chapters of this text.
C A
A C
B
NOT: C = A9 Exclusive OR: C = A % B
1
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
2 Chapter 1 Review of Logic Design Fundamentals
complement (NOT) operation, so C 5 NOT A 5 Ar. The exclusive-OR (XOR) gate has an
output C 5 1 if A 5 1 and B 5 0 or if A 5 0 and B 5 1. The symbol ! represents exclusive
OR, so write
The behavior of a combinational logic circuit can be specified by a truth table that gives the
circuit outputs for each combination of input values. As an example, consider the full adder of
Figure 1-2, which adds two binary digits (X and Y) and a carry 1 Cin 2 to give a sum (Sum) and a
carry out 1 Cout 2 . The truth table specifies the adder outputs as a function of the adder inputs.
For example, when the inputs are X 5 0, Y 5 0, and Cin 5 1, adding the three inputs gives
0 1 0 1 1 5 01, so the sum is 1 and the carry out is 0. When the inputs are 011, 0 1 1 1 1 5 10,
so Sum 5 0 and Cout 5 1. When the inputs are X 5 Y 5 Cin 5 1, 1 1 1 1 1 5 11, so
Sum 5 1 and Cout 5 1.
Derive algebraic expressions for Sum and Cout from the truth table. From the table,
Sum 5 1 when X 5 0, Y 5 0, and Cin 5 1. The term XrYrCin equals 1 only for this com-
bination of inputs. The term XrYCin r 5 1 only when X 5 0, Y 5 1, and Cin 5 0. The term
XYrCinr is 1 only for the input combination X 5 1, Y 5 0, and Cin 5 0. The term XYCin is 1
only when X 5 Y 5 Cin 5 1. Therefore, Sum is formed by ORing these four terms together:
r 1 XYrCinr 1 XYCin
Sum 5 XrYrCin 1 XrYCin (1-2)
Each of the terms in this sum of products (SOP) expression is 1 for exactly one combina-
tion of input values. In a similar manner, Cout is formed by ORing four terms together:
r 1 XYCin
Cout 5 XrYCin 1 XYrCin 1 XYCin (1-3)
Each term in Equations (1-2) and (1-3) is referred to as a minterm, and these equations
are referred to as minterm expansions. These minterm expansions can also be written in
m-notation or decimal notation as follows:
Sum 5 m1 1 m2 1 m4 1 m7 5 Sm 1 1, 2, 4, 7 2
Cout 5 m3 1 m5 1 m6 1 m7 5 Sm 1 3, 5, 6, 7 2
The decimal numbers designate the rows of the truth table for which the corresponding func-
tion is 1. Thus Sum 5 1 in rows 001, 010, 100, and 111 (rows 1, 2, 4, 7).
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
1.2 Boolean Algebra and Algebraic Simplification 3
A logic function can also be represented in terms of the inputs for which the function
value is 0. Referring to the truth table for the full adder, Cout 5 0 when X 5 Y 5 Cin 5 0.
r 2 is
The term 1 X 1 Y 1 Cin 2 is 0 only for this combination of inputs. The term 1 X 1 Y 1 Cin
0 only when X 5 Y 5 0 and Cin 5 1. The term 1 X 1 Yr 1 Cin 2 is 0 only when X 5 Cin 5 0
and Y 5 1. The term 1 Xr 1 Y 1 Cin 2 is 0 only when X 5 1 and Y 5 Cin 5 0. Cout is formed
by ANDing these four terms together:
r 2 1 X 1 Yr 1 Cin 2 1 Xr 1 Y 1 Cin 2
Cout 5 1 X 1 Y 1 Cin 2 1 X 1 Y 1 Cin (1-4)
Cout is 0 only for the 000, 001, 010, and 100 rows of the truth table and, therefore, must
be 1 for the remaining four rows. Each of the terms in the Product of Sums (POS) expression
in Equation (1-4) is referred to as a maxterm, and (1-4) is called a maxterm expansion. This
maxterm expansion can also be written in decimal notation as
Cout 5 M0 # M1 # M2 # M4 5 PM 1 0, 1, 2, 4 2
where the decimal numbers correspond to the truth table rows for which Cout 5 0.
EXAMPLE
Find the complement of F if
F 5 X 1 ErK 1 C 1 AB 1 Dr 2 # 1 1 WZr 1 GrH 1 0 2 2
Fr 5 Xr 1 E 1 Kr 1 1 Cr 1 1 Ar 1 Br 2 D 1 0 2 1 Wr 1 Z 1 1 G 1 Hr 2 # 1 2 2
Additional parentheses in Fr were added when an AND operation in F was replaced with an OR. The dual of an expres-
sion is the same as its complement, except that the variables are not complemented.
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
4 Chapter 1 Review of Logic Design Fundamentals
Duality:
1 X 1 Y 1 Z 1 c2 D 5 XYZ c (1-18) 1 XYZ c2 D 5 X 1 Y 1 Z 1 c (1-18D)
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
1.2 Boolean Algebra and Algebraic Simplification 5
Four ways of simplifying a logic expression using the theorems in Table 1-1 are as follows:
1. Combining terms. Use the theorem XY 1 XYr 5 X to combine two terms. For example,
When combining terms by this theorem, the two terms to be combined should contain
exactly the same variables, and exactly one of the variables should appear complemented
in one term and not in the other. Since X 1 X 5 X, a given term may be duplicated and
combined with two or more other terms. For example, the expression for Cout in Equa-
tion (1-3) can be simplified by combining the first and fourth terms, the second and fourth
terms, and the third and fourth terms:
r 1 XYCin 2
Cout 5 1 XrYCin 1 XYCin 2 1 1 XYrCin 1 XYCin 2 1 1 XYCin
5 YCin 1 XCin 1 XY (1-22)
Note that the fourth term in Equation (1-3) was used three times.
The theorem can still be used, of course, when X and Y are replaced with more compli-
cated expressions. For example,
1 A 1 BC 2 1 D 1 Er 2 1 Ar 1 Br 1 Cr 2 1 D 1 Er 2 5 D 1 Er
3 X 5 D 1 Er, Y 5 A 1 BC, Yr 5 Ar 1 Br 1 Cr 2 4
The expression obtained after applying 1, 2, and 3 will not necessarily have a minimum
number of terms or a minimum number of literals. If it does not and no further simplifi-
cation can be made using 1, 2, and 3, deliberate introduction of redundant terms may be
necessary before further simplification can be made.
4. Adding redundant terms. Redundant terms can be introduced in several ways, such as
adding XXr, multiplying by 1 X 1 Xr 2 , adding YZ to XY 1 XrZ (consensus theorem),
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
6 Chapter 1 Review of Logic Design Fundamentals
or adding XY to X. When possible, the terms added should be chosen so that they will
combine with or eliminate other terms. For example,
1 A 1 B 1 D 2 1 A 1 Br 1 Cr 2 1 Ar 1 B 1 Dr 2 1 Ar 1 B 1 Cr 2
5 1 A 1 1 B 1 D 2 1 Br 1 Cr 2 2 1 Ar 1 B 1 CrDr 2 (by (1-12D))
5 1 A 1 BCr 1 BrD 2 1 Ar 1 B 1 CrDr 2 (by (1-20))
5 A 1 B 1 CrDr 2 1 Ar 1 BCr 1 BrD 2 (by (1-20))
5 AB 1 ACrDr 1 ArBCr 1 ArBrD (by (1-12))
Note that the second distributive law (1-12D) and theorem (1-20) were applied before
the ordinary distributive law. Any Boolean expression can be factored by using the two
distributive laws (1-12 and 1-12D) and theorem (1-20). As an example of factoring, read
the steps in the preceding example in the reverse order.
The following theorems apply to exclusive-OR:
X!05X (1-23)
X ! 1 5 Xr (1-24)
X!X50 (1-25)
X ! Xr 5 1 (1-26)
X!Y5Y!X 1 commutative law 2 (1-27)
1X ! Y2 ! Z 5 X ! 1Y ! Z2 5 X ! Y ! Z 1 associative law 2 (1-28)
X 1 Y ! Z 2 5 XY ! XZ 1 distributive law 2 (1-29)
1 X ! Y 2 r 5 X ! Yr 5 Xr ! Y 5 XY 1 XrYr (1-30)
The expression for Sum in Equation (1-2) can be rewritten in terms of exclusive-OR by
using Equations (1-1) and (1-30):
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
1.3 Karnaugh Maps 7
The simplification rules that you studied in this section are important when a circuit has
to be optimized to use a smaller number of gates. The existence of equivalent forms also
helps when mapping circuits into particular target devices where only certain types of logic
(e.g., NAND only or NOR only) are available.
FIGURE 1-3: AB AB
Four-Variable CD 00 01 11 10 CD 00 01 11 10 Four corner terms
Karnaugh Maps combine to give B9 D9
00 0 4 12 8 00 1 0 0 1
01 1 5 13 9 C 01 0 1 0 0
A9BD
11 3 7 15 11 11 1 1 X 1
10 2 6 14 10 10 1 1 X 1
The variable values along the edge of the map are ordered so that adjacent squares on
the map differ in only one variable. The first and last columns and the top and bottom rows
of the map are considered to be adjacent. Two 1’s in adjacent squares can be combined by
eliminating one variable using xy 1 xyr 5 x. Figure 1-3 shows a four-variable function with
nine minterms and two don’t cares. Minterms ArBCrD and ArBCD differ only in the vari-
able C, so they can be combined to form ArBD, as indicated by a loop on the map. Four 1’s in
a symmetrical pattern can be combined to eliminate two variables. The 1’s in the four corners
of the map can be combined as follows:
as indicated by the loop. Similarly, the six 1’s and two X’s in the bottom half of the map
combine to eliminate three variables and form the term C. The resulting simplified function is
F 5 ArBD 1 BrDr 1 C
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
8 Chapter 1 Review of Logic Design Fundamentals
implicant if it cannot be combined with another group of 1’s to eliminate a variable. A prime
implicant is essential if it contains a 1 that is not contained in any other prime implicant.
When finding a minimum sum of products from a map, essential prime implicants should
be looped first, and then a minimum number of prime implicants to cover the remaining
1’s should be looped. The Karnaugh map shown in Figure 1-4 has five prime implicants and
three essential prime implicants. ArCr is essential because minterm m1 is not covered by any
other prime implicant. Similarly, ACD is essential because of m11, and ArBrDr is essential
because of m2. After looping the essential prime implicants, all 1’s are covered except m7.
Since m7 can be covered by either prime implicant ArBD or BCD, F has two minimum forms:
and
When don’t cares (X’s) are present on the map, the don’t cares are treated like 1’s when
forming prime implicants, but the X’s are ignored when finding a minimum set of prime
00 1 X
0 4 12 8
A9C9
01 1 1 Prime implicants: ArCr, ACD, ArBrDr,
1 5 13 9
ArBD, BCD
11 1 1 1 ACD Essential prime implicants: ArCr, ACD, ArBrDr
3 7 15 11
10 1 X
2 6 14 10
A9B9D 9
implicants to cover all the 1’s. The following procedure can be used to obtain a minimum sum
of products from a Karnaugh map:
1. Choose a minterm (a 1) that has not yet been covered.
2. Find all 1’s and X’s adjacent to that minterm. (Check the n adjacent squares on an
n-variable map.)
3. If a single term covers the minterm and all the adjacent 1’s and X’s, then that term is an
essential prime implicant, so select that term. (Note that don’t cares are treated like 1’s
in steps 2 and 3 but not in step 1.)
4. Repeat steps 1, 2, and 3 until all essential prime implicants have been chosen.
5. Find a minimum set of prime implicants that cover the remaining 1’s on the map. (If there
is more than one such set, choose a set with a minimum number of literals.)
To find a minimum product of sums from a Karnaugh map, loop the 0’s instead of the
1’s. Since the 0’s of F are the 1’s of Fr, looping the 0’s in the proper way gives the mini-
mum sum of products for Fr, and the complement is the minimum product of sums for F.
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
1.3 Karnaugh Maps 9
For Figure 1-3, first loop the essential prime implicants of Fr (BCrDr and BrCrD, indicated
by dashed loops) and then cover the remaining 0 with AB. Thus the minimum sum for Fr is
Fr 5 BCrDr 1 BrCrD 1 AB
from which the minimum product of sums for F is
F 5 1 Br 1 C 1 D 2 1 B 1 C 1 Dr 2 1 Ar 1 Br 2
Karnaugh map techniques can be extended to simplify functions such as this using map-
entered variables. Since E and F are the input variables with the most number of don’t cares
(X), a Karnaugh map can be formed with A, B, C, D and the remaining two variables can be
entered inside the map. Figure 1-5 shows a four-variable map with variables E and F entered
in the squares in the map. When E appears in a square, this means that if E 5 1, the corre-
sponding minterm is present in the function G, and if E 5 0, the minterm is absent. The fifth
and sixth rows in the truth table result in the E in the box corresponding to minterm 5 and
minterm 7. The seventh row results in the F in the box corresponding to minterm 9. Thus, the
map represents the six-variable function
where the minterms are minterms of the variables A, B, C, D. Note that m9 is present in G
only when F 5 1.
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
10 Chapter 1 Review of Logic Design Fundamentals
FIGURE 1-5: AB AB AB AB
Simplification Using CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
Map-Entered Variables 00 1 00 1 00 X 00 X
01 X E X F 01 X X 01 X 1 X 01 X X 1
11 1 E 1 1 11 1 1 1 11 X 1 X X 11 X X X
10 1 X 10 1 X 10 X X 10 X X
G E=F=0 E = 1, F = 0 E = 0, F = 1
MS0 = A9B9 + ACD MS1 = A9D MS2 = AD
where
● MS0 is the minimum sum obtained by setting P1 5 P2 5 c5 0.
● MS1 is the minimum sum obtained by setting P1 5 1, Pj 5 0 1 j 2 1 2 , and replacing all
1’s on the map with don’t cares.
● MS2 is the minimum sum obtained by setting P2 5 1, Pj 5 0 1 j 2 2 2 , and replacing all
1’s on the map with don’t cares.
Corresponding minimum sums can be found in a similar way for any remaining map-entered
variables.
The resulting expression for F will always be a correct representation of F. This expres-
sion will be a minimum sum provided that the values of the map-entered variables can be
assigned independently. On the other hand, the expression will not generally be a minimum
sum if the variables are not independent (for example, if P1 5 P2r ).
For the example of Figure 1-5, maps for finding MS0, MS1, and MS2 are shown, where
E corresponds to P1 and F corresponds to P2. Note that it is not required to draw a map for
E 5 1, F 5 1, because E 5 1 already covers cases with E 5 1, F 5 0 and E 5 1, F 5 1. The
resulting expression is a minimum sum of products for G:
After some practice, it should be possible to write the minimum expression directly from
the original map without first plotting individual maps for each of the minimum sums.
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
1.4 Designing With NA ND and NOR Gates 11
NOR:
A A
B
C ; B
C C = (A + B)9 = A9B 9
Conversion from circuits of OR and AND gates to circuits of all NOR gates or all NAND
gates is straightforward. To design a circuit of NOR gates, start with a product-of-sums rep-
resentation of the function (circle 0’s on the Karnaugh map). Then find a circuit of OR and
AND gates that has an AND gate at the output. If an AND gate output does not drive an
AND gate input and an OR gate output does not connect to an OR gate input, then con-
version is accomplished by replacing all gates with NOR gates and complementing inputs if
necessary. Figure 1-7 illustrates the conversion procedure for
Z 5 G 1 E 1 F 2 1 A 1 Br 1 D 2 1 C 1 D 2 5 G 1 E 1 F 2 3 1 A 1 Br 2 C 1 D 4
Conversion to a circuit of NAND gates is similar, except the starting point should be
a sum of products form for the function (circle 1’s on the map), and the output gate of the
AND-OR circuit should be an OR gate.
Even if AND and OR gates do not alternate, you can still convert a circuit of AND and
OR gates to a NAND or NOR circuit, but it may be necessary to add extra inverters so that
each added inversion is canceled by another inversion. The following procedure may be used
to convert to a NAND (or NOR) circuit:
1. Convert all AND gates to NAND gates by adding an inversion bubble at the output.
Convert OR gates to NAND gates by adding inversion bubbles at the inputs. (To convert
to NOR, add inversion bubbles at all OR gate outputs and all AND gate inputs.)
2. Whenever an inverted output drives an inverted input, no further action is needed, since
the two inversions cancel.
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
12 Chapter 1 Review of Logic Design Fundamentals
3. Whenever a noninverted gate output drives an inverted gate input or vice versa, insert an
inverter so that the bubbles will cancel. (Choose an inverter with the bubble at the input
or output, as required.)
4. Whenever a variable drives an inverted input, complement the variable (or add an
inverter) so the complementation cancels the inversion at the input.
In other words, if we always add bubbles (or inversions) in pairs, the function realized
by the circuit will be unchanged. To illustrate the procedure, you convert Figure 1-8(a) to
NANDs. First, add bubbles to change all gates to NAND gates (Figure 1-8(b)). The high-
lighted lines indicate four places where you have added only a single inversion. This is cor-
rected in Figure 1-8(c) by adding two inverters and complementing two variables.
Bubbles cancel
A
B
C
D F
E
(b) First step in NAND conversion
Added inverter
Added inverter
A
B
C
D9 F
E9
(c) Completed conversion
Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-203
Discovering Diverse Content Through
Random Scribd Documents
L'accent de la mourante eut quelque chose de si solennel que son
pouvoir venu d'une âme agitée réagit violemment sur l'enfant, il
sentit une chaleur exorbitante dans la moelle de ses os.
—Que veux-tu, ma mère?
—Écoute-moi. Demain, tout sera fini pour moi. Nous ne nous
verrons plus. Demain, tu seras un homme, mon enfant. Je suis donc
obligée de faire quelques dispositions qui soient un secret entre nous
deux. Prends la clef de ma petite table. Bien! Ouvre le tiroir. Tu
trouveras à gauche deux papiers cachetés. Sur l'un, il y a:—Louis.
Sur l'autre:—Marie.
—Les voici, ma mère.
—Mon fils chéri, c'est vos deux actes de naissance; ils vous
seront nécessaires. Tu les donneras à garder à ma pauvre vieille
Annette, qui vous les rendra quand vous en aurez besoin.
Maintenant, reprit-elle, n'y a-t-il pas au même endroit un papier
sur lequel j'ai écrit quelques lignes?
—Oui, ma mère.
Et Louis commençant à lire:—Marie Willemsens, née à...
—Assez, dit-elle vivement. Ne continue pas. Quand je serai
morte, mon fils, tu remettras encore ce papier à Annette, et tu lui
diras de le donner à la mairie de Saint-Cyr, où il doit servir à faire
dresser exactement mon acte de décès. Prends ce qu'il faut pour
écrire une lettre que je vais te dicter.
Quand elle vit son fils prêt, et qu'il se tourna vers elle comme
pour l'écouter, elle dit d'une voix calme: Monsieur le comte, votre
femme lady Brandon est morte à Saint-Cyr, près de Tours,
département d'Indre-et-Loire. Elle vous a pardonné.
—Signe...
Elle s'arrêta, indécise, agitée.
—Souffrez-vous davantage? demanda Louis.
—Signe: Louis-Gaston!
Elle soupira, puis reprit:—Cachette la lettre, et écris l'adresse
suivante: A lord Brandon. Brandon-Square, Hyde-Park. Londres.
Angleterre.
—Bien, reprit-elle. Le jour de ma mort tu feras affranchir cette
lettre à Tours.
—Maintenant, dit-elle après une pause, prends le petit
portefeuille que tu connais, et viens près de moi, mon cher enfant.
—Il y a là, dit-elle, quand Louis eut repris sa place, douze mille
francs. Ils sont bien à vous, hélas! Vous eussiez été plus riches, si
votre père...
—Mon père, s'écria l'enfant, où est-il?
—Mort, dit-elle en mettant un doigt sur ses lèvres, mort pour me
sauver l'honneur et la vie.
Elle leva les yeux au ciel. Elle eût pleuré, si elle avait encore eu
des larmes pour les douleurs.
—Louis, reprit-elle, jurez-moi là, sur ce chevet, d'oublier ce que
vous avez écrit et ce que je vous ai dit.
—Oui, ma mère.
—Embrasse-moi, cher ange.
Elle fit une longue pause, comme pour puiser du courage en
Dieu, et mesurer ses paroles aux forces qui lui restaient.
—Écoute. Ces douze mille francs sont toute votre fortune; il faut
que tu les gardes sur toi, parce que quand je serai morte il viendra
des gens de justice qui fermeront tout ici. Rien ne vous y
appartiendra, pas même votre mère! Et vous n'aurez plus, pauvres
orphelins, qu'à vous en aller, Dieu sait où. J'ai assuré le sort
d'Annette. Elle aura cent écus tous les ans, et restera sans doute à
Tours. Mais que feras-tu de toi et de ton frère?
Elle se mit sur son séant et regarda l'enfant intrépide, qui, la
sueur au front, pâle d'émotions, les yeux à demi voilés par les
pleurs, restait debout devant son lit.
—Mère, répondit-il d'un son de voix profond, j'y ai pensé. Je
conduirai Marie au collége de Tours. Je donnerai dix mille francs à la
vieille Annette en lui disant de les mettre en sûreté et de veiller sur
mon frère. Puis, avec les cent louis qui resteront, j'irai à Brest, je
m'embarquerai comme novice. Pendant que Marie étudiera, je
deviendrai lieutenant de vaisseau. Enfin, meurs tranquille, ma mère,
va: je reviendrai riche, je ferai entrer notre petit à l'école
Polytechnique, où je le dirigerai suivant ses goûts.
Un éclair de joie brilla dans les yeux à demi éteints de la mère,
deux larmes en sortirent, roulèrent sur ses joues enflammées; puis,
un grand soupir s'échappa de ses lèvres, et elle faillit mourir victime
d'un accès de joie, en trouvant l'âme du père dans celle de son fils
devenu homme tout à coup.
—Ange du ciel, dit-elle en pleurant, tu as effacé par un mot
toutes mes douleurs. Ah! je puis souffrir.—C'est mon fils, reprit-elle,
j'ai fait, j'ai élevé cet homme!
Et elle leva ses mains en l'air et les joignit comme pour exprimer
une joie sans bornes; puis elle se coucha.
—Ma mère, vous pâlissez! s'écria l'enfant.
—Il faut aller chercher un prêtre, répondit-elle d'une voix
mourante.
Louis réveilla la vieille Annette, qui, tout effrayée, courut au
presbytère de Saint-Cyr.
Dans la matinée, madame Willemsens reçut les sacrements au
milieu du plus touchant appareil. Ses enfants, Annette et la famille
du closier, gens simples déjà devenus de la famille, étaient
agenouillés. La croix d'argent, portée par un humble enfant de
chœur, un enfant de chœur de village! s'élevait devant le lit, et un
vieux prêtre administrait le viatique à la mère mourante. Le viatique!
mot sublime, idée plus sublime encore que le mot, et que possède
seule la religion apostolique de l'Église romaine.
—Cette femme a bien souffert! dit le curé dans son simple
langage.
Marie Willemsens n'entendait plus; mais ses yeux restaient
attachés sur ses deux enfants. Chacun, en proie à la terreur, écoutait
dans le plus profond silence les aspirations de la mourante, qui déjà
s'étaient ralenties. Puis, par intervalles, un soupir profond annonçait
encore la vie en trahissant un débat intérieur. Enfin, la mère ne
respira plus. Tout le monde fondit en larmes, excepté Marie. Le
pauvre enfant était encore trop jeune pour comprendre la mort.
Annette et la closière fermèrent les yeux à cette adorable créature
dont alors la beauté reparut dans tout son éclat. Elles renvoyèrent
tout le monde, ôtèrent les meubles de la chambre, mirent la morte
dans son linceul, la couchèrent, allumèrent des cierges autour du lit,
disposèrent le bénitier, la branche de buis et le crucifix, suivant la
coutume du pays, poussèrent les volets, étendirent les rideaux; puis
le vicaire vint plus tard passer la nuit en prières avec Louis, qui ne
voulut point quitter sa mère. Le mardi matin l'enterrement se fit. La
vieille femme, les deux enfants, accompagnés de la closière,
suivirent seuls le corps d'une femme dont l'esprit, la beauté, les
grâces avaient une renommée européenne, et dont à Londres le
convoi eût été une nouvelle pompeusement enregistrée dans les
journaux, une sorte de solennité aristocratique, si elle n'eût pas
commis le plus doux des crimes, un crime toujours puni sur cette
terre, afin que ces anges pardonnés entrent dans le ciel. Quand la
terre fut jetée sur le cercueil de sa mère, Marie pleura, comprenant
alors qu'il ne la verrait plus.
Une simple croix de bois, plantée sur sa tombe, porta cette
inscription due au curé de Saint-Cyr.
CY GIT
ebooksecure.com