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01 Module1.0 Introduction To HDL

This document serves as an introduction to Hardware Description Languages (HDLs), specifically VHDL and Verilog, outlining their definitions, history, structure, and types of descriptions. It details the components of HDL modules, including entity and architecture in VHDL, and declaration and body in Verilog, along with examples of a half-adder circuit. Additionally, it covers various styles of description and the communication modes of ports used in HDLs.

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22 views29 pages

01 Module1.0 Introduction To HDL

This document serves as an introduction to Hardware Description Languages (HDLs), specifically VHDL and Verilog, outlining their definitions, history, structure, and types of descriptions. It details the components of HDL modules, including entity and architecture in VHDL, and declaration and body in Verilog, along with examples of a half-adder circuit. Additionally, it covers various styles of description and the communication modes of ports used in HDLs.

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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CPE382

Cluster 1 | 2nd Semester A.Y. 2020-2021


Moodle: CPE382 Introduction to HDL
MS Teams: CPE382-H1-C1

INTRODUCTION TO HDL
Module 1

ENGR. JUNDITH D. ALTERADO


Email Address: [email protected]
Facebook Account: (7) Jundith Alterado | Facebook
Module outline
Hardware
Description Ports
Language

Structure of the HDL


Operators
Module

Styles/Types of
Data Types
Description
HARDWARE DESCRIPTION LANGUAGE
HDL D E F I N I T I O N

Hardware
Description
Language

- used to describe digital - After writing and testing the


system (microprocessor, HDL code, the user can
memory or flip-flop) synthesize the code into
- Widely used in logic design digital logic components such
- VHDL and Verilog as gates and flip-flops that
- It facilitates a top-down can be downloaded into
methodology for using FPGAs or compatible
synthesis. electronic components.
- Similar to other software - Two most commonly used
languages such as C. HDLs: VHDL and Verilog
History

1 2
HDL

HDL
Verilog VHDL

• 1980s – introduced and have • VHDL


gone through several iterations • V (Very High Speed
of standardizations by the Integrated Circuit)
Institute of Electrical and • H (Hardware)
Electronic Engineers (IEEE). • D (Description)
• December 1995 – Verilog HDL • L (Langugage)
became IEEE Standard 1364- • Developed in early 1980s
1995 • 1987 – IEEE Std. 1076-1987
• 2001 – IEEE Std. 1364-2001 • 1993 – IEEE Std. 1076-1993
was introduced. • 2008 – IEEE Std. 1076-2008
• 2005 – IEEE Std. 1364-2005
Structure of the HDL Module
Structure of the HDL Module

• Follows the general structure of software


languages such as C.
• Source code – high-level language style.

• Text editors supplied by the HDL package


vendor can be sued to write the module, or the
code can be written using external text editors
and imported to the HDL package.
Structure of the HDL Module
To illustrate: Consider a half-adder circuit.
Half – adder :
-combinational circuit; output solely depends on its inputs .
-adds two input bits and outputs the result as two bits.
-output bits; sum and carry out.

Input Output
a b S C
0 0 0 0
1 0 1 0
0 1 1 0
1 1 0 1
Half-Adder
Logic Symbol Logic Diagram
Structure of the VHDL Module
Two major constructs:
- Entity
- Architecture
ENTITY
- declares the input and output signals of the
system to be described.
ARCHITECTURE
- describes the relationship between the inputs
and outputs of the system.
Entity and Architecture

-Name or Identifier
note: VHDL is case INSENSITIVE.
- should start with a letter
- can include the special character
underscore(_)
Entity
entity Half_adder is port(a: in bit;
b : in bit;
S : out bit;
C : out bit);
end half_adder;

entity (predefined keyword) – begins the entity part of the module followed by
the name of the entity.
Name (user defined) – does not convey any information about the system; just
an identifier.
is (predefined keyword) – must be written after the name of the entity
port (predefined keyword) – starts the input/s and output/s declarations.
in (predefined) – instantiates the mode of the port as an input.
out (predefined) – instantiates the mode of the port as an output.
bit (predefined) – determines the allowed values that signals a , b can take and
S, C outputs.
semicolon (;) - separator
Architecture
Example of Entity Architecture

entity Half_adder is port(a: in bit;


b : in bit;
S : out bit;
C : out bit);
end half_adder;

architecture dtfl_half of Half_adder is


begin
S <= a xor b; -- statement 1
C <= a and b; -- statement 2
--Blank lines are allowed
end dtfl_half;
Structure of the Verilog Module
Two major part:
- Declaration
- Body
DECLARATION
- name, inputs, and outputs of the module is
entered.
BODY
- shows the relationship between the inputs
and outputs of the system.
Identifier

-Name or Identifier
note: Verilog is case SENSITIVE.
- should start with a letter
- can include the special character
underscore(_)
Example of a Verilog Module
module Half_adder (a, b, S, C);
//declarations
input a, b;
output S, C;
//blank lines are allowed

//body
assign S = a ^ b; //statement 1
assign C = a & b; //statement 2
endmodule
STYLES (TYPES) OF DESCRIPTION
Types of Description

• Data Flow
• Behavioral
• Structural
• Switch Level
• Mixed Type
• Mixed Language
Data Flow Description

- Describes how the system’s - Usually done by writing the


signals flow from the inputs Boolean function of the
to the outputs outputs.
Behavioral Description

- Models the system as how


the outputs behave with the
inputs; usually a flowchart is
used to show this behavior.
- One where the architecture
(VHDL) or the module
(Verilog) contains the
predefined word process
(VHDL) or always or initial
(Verilog).
Behavioral Description
VHDL Verilog HDL
Structural Description

- Models the system as - This description is identified


components or gates. by the presence of the
keyword component in the
architecture (VHDL) or gates
construct such as and, or,
and not in the module
(Verilog).
Structural Description
VHDL Verilog HDL
PORTS
Ports – Communication means between the system to
be described and the environment.

MODES
MODES

1 VHDL
• in: The port is only an input
2 Verilog HDL

port. • input: The port is only an


• out: The port is only an output input port.
port. • output: The port is only an
• buffer: The port can be used as output port.
both an input and output but • inout: The port can be used
can have only one source (i.e., as both an input and output.
limited fan out).
• inout: The port can be used as
both an input and output.
• linkage: Same as inout but the
port can only correspond to a
signal.
OPERATORS
Verilog Logical Operators
Verilog Relational Operators
Verilog Arithmetic Operators

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