Scribd
Upload
4 views1 page

Marvell Interview Digital

The document outlines questions and topics covered in two rounds of technical interviews focused on STA, FSM, Verilog, and FPGA. Key areas include setup and hold violations, clock frequency division, sorting algorithms, and FPGA synthesis. The document also touches on practical coding tasks and theoretical discussions relevant to digital systems and design methodologies.

Uploaded by

kesalin .g
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
4 views1 page

Marvell Interview Digital

The document outlines questions and topics covered in two rounds of technical interviews focused on STA, FSM, Verilog, and FPGA. Key areas include setup and hold violations, clock frequency division, sorting algorithms, and FPGA synthesis. The document also touches on practical coding tasks and theoretical discussions relevant to digital systems and design methodologies.

Uploaded by

kesalin .g
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
You are on page 1/ 1

Round-1

-------

Mostly concentrated on STA and FSM


1. Deffine violations in STA ?
2. Draw a digital circuit with 2 FF and a combinational circuit connecting them.?
3. Through above drawn circit explain with waveforms setup and hold violations...
4. How will you resolve the above violations in the circuit..?
5. Without touching the clock path how will you overcome the setup violation..?

6. How will you detect the pattern 11010...(with overlaping)?


7. Circuit to 1/2 the clk frequency with a single flop..
8. Circuit to 1/3 the clk frequency with two flop..

9. C code for any sorting algorithm....its space and time complexity..and how did
you obtain these..

10. There are two Flops in a digital system with one flop output connected to the
next flop input
through some combinational circuit.Fist Flop is clocked at 100MHz and next Flop
clocked at 40MHz.
What are the possible issues arising in this system?
How will you modify the system to overcome this issues..?

Round-2
-------

Concentrated on Verilog and FPGA...


1. Why do we need FPGA?
2. What do you mean by synthesis?
for above i answered that the output from synthesis was gate level netlist and
so he followed with what was netlist..
3. Building block of FPGA and how your design is realised in FPGA ?
4. Verilog codes for the below problems....
a) Print fibonacci series upto 100
b) A number is generated using randon function.Code to ensure that the number
generated is between 1 and 100.
c) 3 t0 8 decoder
5. Disussion of the FPGA project of last sem...
6. Difference in blocking and non blocking statements..
7. Any idea on IP protocols...

You might also like