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Uart Report 2

The document presents a project report on the design and verification of the UART (Universal Asynchronous Receiver/Transmitter) protocol, detailing its communication process, advantages, and disadvantages. It outlines the steps of UART transmission, the design of the UART modules, and includes code for the transmitter and receiver. Additionally, it discusses the UVM (Universal Verification Methodology) environment used for testing the UART functionality.

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Neha
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25 views40 pages

Uart Report 2

The document presents a project report on the design and verification of the UART (Universal Asynchronous Receiver/Transmitter) protocol, detailing its communication process, advantages, and disadvantages. It outlines the steps of UART transmission, the design of the UART modules, and includes code for the transmitter and receiver. Additionally, it discusses the UVM (Universal Verification Methodology) environment used for testing the UART functionality.

Uploaded by

Neha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Futurewiz Super -50

DV Batch 2

Project Report

Design and Verification of


UART PROTOCOL

Submitted by: Submitted to:


1. Sarvagya Karna Neha Sharma
2. Suresh Bhati
3. K. Swati
UART stands for Universal Asynchronous Receiver/Transmitter. It’s a physical
circuit in a microcontroller, or a stand-alone IC. A UART’s main purpose is to
transmit and receive serial data

Introduction to UART communication


In UART communication, two UARTs communicate directly with each other. The
transmitting UART converts parallel data from a controlling device like a CPU into
serial form, transmits it in serial to the receiving UART, which then converts the
serial data back into parallel data for the receiving device. Only 2 wires are needed
to transmit data between two UARTs. Data flows, From the Tx pin of the
transmitting UART to the Rx pin of the receiving UART.

Figure: UART

UARTs transmit data asynchronously, which means there is no clock signal to


synchronize the output of bits from the transmitting UART to the sampling of bits
by the receiving UART. Instead of a clock signal, the transmitting UART adds start
and stop bits to the data packet being transferred. These bits define the beginning
and end of the data packet so the receiving UART knows when to start reading the
bits.
When the receiving UART detects a start bit, it starts to read the incoming bits at a
specific frequency known as the baud rate. Baud rate is a measure of the speed of
data transfer, expressed in bits per second (bps). Both UARTs must operate at about
the same baud rate. The baud rate between the transmitting and receiving UARTs
can only differ by about 10% before the timing of bits gets too far off. Both UARTs
must also must be configured to transmit and receive the same data packet structure.
HOW UART WORKS
The UART that is going to transmit data receives the data from a data bus. The data
bus is used to send data to the UART by another device like a CPU, memory, or
microcontroller. Data is transferred from the data bus to the transmitting UART in
parallel form. After the transmitting UART gets the parallel data from the data bus,
it adds a start bit, a parity bit, and a stop bit, creating the data packet. Next, the data
packet is output serially, bit by bit at the Tx pin. The receiving UART reads the data
packet bit by bit at its Rx pin. The receiving UART then converts the data back into
parallel form and removes the start bit, parity bit, and stop bits. Finally, the receiving
UART transfers the data packet in parallel to the data bus on the receiving end.
We have designed the UART without incorporating the use of a parity bit.

STEPS OF UART TRANSMISSION


1. The transmitting UART receives data in parallel from the data bus.

2. The transmitting UART adds the start bit, parity bit, and the stop bit(s) to the
data frame

3. The complete packet is transmitted serially from the transmitting UART to


the receiving UART. The receiving UART samples the data line at the pre-
configured baud rate.
4. The receiving UART discards the start bit, parity bit, and stop bit from the
data frame.
5. The receiving UART converts the serial data back into parallel and transfers
it to the data bus on the receiving end.

Advantages of UART:
• Only use 2 wire.
• No clocking signal is necessary.
• Has a parity bit to allow for error checking.
• Simplicity.
• Widespread Compatibility.
• Versatility.
• Asynchronous Communication.
• Cost-Effective.

Disadvantages of UART:
• The size of the data frame is limited to a maximum of 9 bits.
• Doesn’t support multiple slave or multiple master systems.
• The baud rates of each UART must be within 10% of each other.
• Limited Distance.
• No Built-in Error Checking.
• Limited Speeds.
• Synchronization Challenges.
• Half-Duplex Communication.
BLOCK DIAGRAM:
Design:
1)Top Module
2) UART_transmitter
3)UART_Receiver:
module uart_top
#(
parameter clk_freq = 1000000,
parameter baud_rate = 9600
)
(
input clk,rst,
input rx,
input [7:0] dintx,
input newd,
output tx,
output [7:0] doutrx,
output donetx,
output donerx
);
//instance of uart transmitter

uarttx #(clk_freq, baud_rate)


utx (clk, rst, newd, dintx, tx, donetx);
//instance of Uart Reciver
uartrx #(clk_freq, baud_rate)
rtx (clk, rst, rx, donerx, doutrx);

endmodule

//////////////////////////////////////////////////////////////////
module uarttx
#(
parameter real clk_freq = 1e6,
parameter baud_rate = 9600
)
(
input clk,rst,
input newd,
input [7:0] tx_data,
output reg tx,
output reg donetx
);
localparam clkcount = (clk_freq/baud_rate);
integer count = 0;
integer counts = 0;

reg uclk = 0;

enum bit[1:0] {idle = 2'b00, transfer = 2'b01,} state;

///////////uart_clock_gen
always@(posedge clk)
begin
if(count < clkcount/2)
count <= count + 1;
else begin
count <= 0;
uclk <= ~uclk;
end
end
reg [7:0] din;
////////////////////Reset decoder

always@(posedge uclk)
begin
if(rst)
begin
state <= idle;
end
else
begin
case(state)
idle:
begin
counts <= 0;
tx <= 1'b1;
donetx <= 1'b0;

if(newd)
begin
state <= transfer;
din <= tx_data;
tx <= 1'b0;
end
else
state <= idle;
end
transfer: begin
if(counts <= 7) begin
counts <= counts + 1;
tx <= din[counts];
state <= transfer;
end
else
begin
counts <= 0;
tx <= 1'b1;
state <= idle;
donetx <= 1'b1;
end
end

default : state <= idle;


endcase
end
end

endmodule

////////////////////////////////////////////////////////////////////
module uartrx
#(
parameter clk_freq = 1000000, //MHz
parameter baud_rate = 9600
)
(
input clk,
input rst,
input rx,
output reg done,
output reg [7:0] rxdata
);

localparam clkcount = (clk_freq/baud_rate);


integer count = 0;
integer counts = 0;
reg uclk = 0;
enum bit[1:0] {idle = 2'b00, start = 2'b01} state;

///////////uart_clock_gen
always@(posedge clk)
begin
if(count < clkcount/2)
count <= count + 1;
else
begin
count <= 0;
uclk <= ~uclk;
end
end
always@(posedge uclk)
begin
if(rst)
begin
rxdata <= 8'h00;
counts <= 0;
done <= 1'b0;
end
else
begin
case(state
idle :
begin
rxdata <= 8'h00;
counts <= 0;
done <= 1'b0;
if(rx == 1'b0)
state <= start;
else
state <= idle;
end

start:
begin
if(counts <= 7)
begin
counts <= counts + 1;
rxdata <= {rx, rxdata[7:1]};
end
else
begin
counts <= 0;
done <= 1'b1;
state <= idle;
end
end
default : state <= idle;
endcase
end
end

endmodule

Interface
TRANSACTION CLASS
GENERATOR CLASS
DRIVER CLASS
MONITORE CLASS
SCOREBOARD CLASS
ENVIRONMENT CLASS
Module Top
RESULTS:

WAVE :
WAVE: showing that tx operation happening correctly

Wave:showing reciver operation

UVM ENVIRONMENT:
INTERFACE CLASS:
TRANSACTION CLASS

GENERATOR CLASS
DRIVER CLASS
MONITOR CLASS
AGENT CLASS
SCOREBOARD CLASS
ENVIRONMENT CLASS

TEST CLASS
TEST TOP

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