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HDlbits

The document contains design code for multiple modules related to a Lemmings game, including state machines for walking, falling, and digging behaviors. It also includes a water service module and a clock count question module, each with their own state transition logic and output assignments. The designs utilize parameters, state registers, and combinational logic to define the behavior of the systems.

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joshnap02619
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110 views13 pages

HDlbits

The document contains design code for multiple modules related to a Lemmings game, including state machines for walking, falling, and digging behaviors. It also includes a water service module and a clock count question module, each with their own state transition logic and output assignments. The designs utilize parameters, state registers, and combinational logic to define the behavior of the systems.

Uploaded by

joshnap02619
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Lemmings 1

Design
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right); //

parameter LEFT=0, RIGHT=1;


reg state, next_state;

always @(*) begin


// State transition logic
case(state)
LEFT: next_state = bump_left ? RIGHT : LEFT;
RIGHT: next_state = bump_right ? LEFT : RIGHT;
endcase
end

always @(posedge clk, posedge areset) begin


// State flip-flops with asynchronous reset
if(areset)
state <= LEFT;
else
state <= next_state;
end

// Output logic
assign walk_left = (state == LEFT) ? 1 : 0;
assign walk_right = (state == RIGHT) ? 1 : 0;

endmodule
Lemmings 2

Design code:
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah );

parameter right=0, left=1, fall_right=2, fall_left=3;


reg [2:0] state, next_state;

always @(*) begin


case(state)
left: begin
if (!ground)
next_state = fall_left;
else
next_state = bump_left ? right : left;
end
right: begin
if (!ground)
next_state = fall_right;
else
next_state = bump_right ? left : right;
end
fall_right: next_state = ground ? right : fall_right;
fall_left: next_state = ground ? left : fall_left;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset)
state <= left;
else
state <= next_state;
end

//output
assign aaah = (state == fall_left || state== fall_right) ? 1 :
0;
assign walk_left = (state == left) ? 1 : 0;
assign walk_right = (state == right) ? 1 : 0;

endmodule
Lemmings 3

Design code:
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );

parameter right=0, left=1, fall_right=2, fall_left=3,


dig_right=4, dig_left=5;
reg [3:0] state, next_state;

always @(*) begin


case(state)
left: begin
if (ground && dig)
next_state = dig_left;
else if (!ground)
next_state = fall_left;
else
next_state = bump_left ? right : left;
end
right: begin
if (ground && dig)
next_state = dig_right;
else if (!ground)
next_state = fall_right;
else
next_state = bump_right ? left : right;
end
fall_right: next_state = ground ? right : fall_right;
fall_left: next_state = ground ? left : fall_left;
dig_left: next_state = ground ? dig_left : fall_left;
dig_right: next_state = ground ? dig_right : fall_right;
endcase
end

always @(posedge clk, posedge areset) begin


if (areset)
state <= left;
else
state <= next_state;
end

//output
assign aaah = (state == fall_left || state== fall_right) ? 1 :
0;
assign walk_left = (state == left) ? 1 : 0;
assign walk_right = (state == right) ? 1 : 0;
assign digging = (state == dig_left || state == dig_right) ? 1 :
0;

endmodule
Lemmings 4

Design code:
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );

integer count_clk=0;

parameter right=0, left=1, fall_right=2, fall_left=3,


dig_right=4, dig_left=5, splatter=6;
reg [3:0] state, next_state;

always @(posedge clk) begin


if (state == fall_left || state == fall_right)
count_clk <= count_clk + 1;
else
count_clk <= 0;
end

always @(*) begin


case(state)
left: begin
if (ground && dig)
next_state = dig_left;
else if (!ground)
next_state = fall_left;
else
next_state = bump_left ? right : left;
end
right: begin
if (ground && dig)
next_state = dig_right;
else if (!ground)
next_state = fall_right;
else
next_state = bump_right ? left : right;
end
fall_right: begin
if(ground)
if (count_clk > 19)
next_state = splatter;
else
next_state = right;
else
next_state = fall_right;
end
fall_left: begin
if(ground)
if (count_clk > 19)
next_state = splatter;
else
next_state = left;
else
next_state = fall_left;
end
dig_left: next_state = ground ? dig_left : fall_left;
dig_right: next_state = ground ? dig_right : fall_right;
splatter: next_state = splatter;
endcase
end

always @(posedge clk, posedge areset) begin


if (areset)
state <= left;
else
state <= next_state;
end

//output
assign aaah = ((state == fall_left || state== fall_right) ? 1 :
0);
assign walk_left =((state == left) ? 1 : 0);
assign walk_right = ((state == right) ? 1 : 0);
assign digging =((state == dig_left || state == dig_right) ? 1 :
0);
endmodule
Water service FSN

Design code (long):


module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);

parameter abv_s3=0, nom_s3_s2=1, sup_s3_s2=2, nom_s2_s1=3,


sup_s2_s1=4, bel_s1=5;
reg [2:0] state, next_state;

always @(posedge clk) begin


state <= reset ? bel_s1 : next_state;
end

always @(*) begin


case (state)
abv_s3: next_state = s[3] ? abv_s3 : s[2] ? sup_s3_s2 :
s[1] ? sup_s2_s1 : bel_s1;
/*
begin
if (s[3])
next_state = abv_s3;
else begin
if (s[2])
next_state = sup_s3_s2;
else begin
if (s[1])
next_state = sup_s2_s1;
else
next_state = bel_s1;
end
end
end
*/

nom_s3_s2: next_state = s[3] ? abv_s3 : s[2] ? nom_s3_s2


: s[1] ? sup_s2_s1 : bel_s1;
/*
begin
if (s[3])
next_state = abv_s3;
else begin
if (s[2])
next_state = nom_s3_s2;
else begin
if (s[1])
next_state = sup_s2_s1;
else
next_state = bel_s1;
end
end
end
*/

sup_s3_s2: next_state = s[3] ? abv_s3 : s[2] ? sup_s3_s2


: s[1] ? sup_s2_s1 : bel_s1;
/*
begin
if (s[3])
next_state = abv_s3;
else begin
if (s[2])
next_state = sup_s3_s2;
else begin
if (s[1])
next_state = sup_s2_s1;
else
next_state = bel_s1;
end
end
end
*/

nom_s2_s1: next_state = s[3] ? abv_s3 : s[2] ? nom_s3_s2


: s[1] ? nom_s2_s1 : bel_s1;
/*
begin
if (s[3])
next_state = abv_s3;
else begin
if (s[2])
next_state = nom_s3_s2;
else begin
if (s[1])
next_state = nom_s2_s1;
else
next_state = bel_s1;
end
end
end
*/

sup_s2_s1: next_state = s[3] ? abv_s3 : s[2] ? nom_s3_s2


: s[1] ? sup_s2_s1 : bel_s1;
/*
begin
if (s[3])
next_state = abv_s3;
else begin
if (s[2])
next_state = nom_s3_s2;
else begin
if (s[1])
next_state = sup_s2_s1;
else
next_state = bel_s1;
end
end
end
*/

bel_s1: next_state = s[3] ? abv_s3 : s[2] ? nom_s3_s2 :


s[1] ? nom_s2_s1 : bel_s1;
/*
begin
if (s[3])
next_state = abv_s3;
else begin
if (s[2])
next_state = nom_s3_s2;
else begin
if (s[1])
next_state = nom_s2_s1;
else
next_state = bel_s1;
end
end
end
*/
endcase
end

assign fr3 = (state == bel_s1);


assign fr2 = (state == sup_s2_s1 || state == nom_s2_s1 || state
== bel_s1);
assign fr1 = (state == sup_s3_s2 || state == nom_s3_s2 || state
== sup_s2_s1 || state == nom_s2_s1 || state == bel_s1);
assign dfr = (state == sup_s3_s2 || state == sup_s2_s1 || state
== bel_s1);

endmodule

Design code (no commnet):


module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);

parameter abv_s3=0, nom_s3_s2=1, sup_s3_s2=2, nom_s2_s1=3,


sup_s2_s1=4, bel_s1=5;
reg [2:0] state, next_state;

always @(posedge clk) begin


state <= reset ? bel_s1 : next_state;
end

always @(*) begin


case (state)
abv_s3: next_state = s[3] ? abv_s3 : s[2] ? sup_s3_s2 :
s[1] ? sup_s2_s1 : bel_s1;
nom_s3_s2: next_state = s[3] ? abv_s3 : s[2] ? nom_s3_s2
: s[1] ? sup_s2_s1 : bel_s1;
sup_s3_s2: next_state = s[3] ? abv_s3 : s[2] ? sup_s3_s2
: s[1] ? sup_s2_s1 : bel_s1;
nom_s2_s1: next_state = s[3] ? abv_s3 : s[2] ? nom_s3_s2
: s[1] ? nom_s2_s1 : bel_s1;
sup_s2_s1: next_state = s[3] ? abv_s3 : s[2] ? nom_s3_s2
: s[1] ? sup_s2_s1 : bel_s1;
bel_s1: next_state = s[3] ? abv_s3 : s[2] ? nom_s3_s2 :
s[1] ? nom_s2_s1 : bel_s1;
endcase
end

assign fr3 = (state == bel_s1);


assign fr2 = (state == sup_s2_s1 || state == nom_s2_s1 || state
== bel_s1);
assign fr1 = (state == sup_s3_s2 || state == nom_s3_s2 || state
== sup_s2_s1 || state == nom_s2_s1 || state == bel_s1);
assign dfr = (state == sup_s3_s2 || state == sup_s2_s1 || state
== bel_s1);

endmodule
clk count question
que : question from HDLbits

Design code
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);

integer clk_count=0, w_count=0;

parameter A=0, B=1;


reg state, next_state;

always @(posedge clk) begin


if (reset) begin
state <= A;
clk_count=0;
w_count=0;
end else begin
state <= next_state;
if (state == B) begin
if (clk_count >= 3) begin
clk_count = 0;
w_count = 0;
end
clk_count = clk_count + 1;
if (w)
w_count = w_count + 1;
end
end
end

always @(*) begin


case(state)
A: next_state = s ? B : A;
B: next_state = B;
endcase
end

assign z = (state == B && clk_count==3 && w_count == 2) ? 1 : 0;


endmodule

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