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SEMICONDUCTOR
APPLICATION NOTE
AN419

UHF AMPLIFIER DESIGN

USING DATA SHEET DESIGN CURVES
INTRODUCTION k [y12 y21 + Re (y12y21)] g22
GL = • – g22
The design of UHF amplifiers usually involves a particular 2 g11
set of device parameters of which h, y, and s parameters
are probably the most familiar. These parameters are (Gs + g11) Zo
Bs = – b11
commonly used to determine device loading (input and k [y12 y21 + Re y12y21]
output) admittances for particular gain and stability criteria.
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The design procedure for determining gain and stability (GL + g22) Zo
usually involves a mathematical solution, a graphical BL = – b22
approach, or a combination of both. k [y12 y21 + Re (y12y21)]
This report describes a design technique for the Where,
unneutralized case whereby the device loading admittances
are taken directly from device design curves. An example (Bs+b11)(GL+g22) + (BL+b22) k (L+M)/2 (GL+g22)
Z=
is given of how these design parameters are used to design k (L + M)
a single stage 1 GHz microstrip amplifier and predicted L = y12y21
results are compared to actual measured values. Practical
circuit construction techniques are also discussed for the M = Re (y12y21)
benefit of readers unfamiliar with microstrip techniques.
Defining D as the denominator in GT expression yields:
Z4 [k (L + M) + 2M] Z2
STABILITY CONSIDERATIONS D= + – 2NZ k (L + M) + A2 + N2
4 2
Two very important methods1 for expressing stability
involve Linvill’s stability factor “C” and Stern’s stability factor where,
“k”. The first deals primarily with the device since an open k (L + M)
termination is assumed on both the input and output and is A= – M,
2
formulated:
N = Im (y12y21),
y12 y21 and,
C= .
2g11 g22 – Re (y12 y21) Zo = that real value of Z which results in the smallest mini-
If “C” is greater than 1, the transistor is potentially mum of D, found by setting,
unstable. However, if C is less than 1, the transistor is dD
unconditionally stable. The C factor versus frequency for the = Z3 + [k (L + M) + 2M] Z – 2N k (L + M) .
dZ
common base and common emitter configurations (2N4957)
are shown in Figures 10 and 17 respectively. equal to zero.
The second method is primarily circuit oriented and is
used to compute the relative stability of an actual amplifier 4 Re (Ys) Re (YL) y212
circuit for the particular source and load terminations used. GT =
(y11 + Ys) (y22 + YL) – y12y21)2
If “k” is greater than 1, the circuit is stable. If “k” is less than
1 the circuit is potentially unstable. k = Stern’s stability factor
Stern has developed equations for calculating the input Gs = Real part of the source admittance
and output loading admittances for maximum power gain GL = Real part of the load admittance
with a particular stability factor, k. These values of input and Bs = Imaginary part of the source admittance
output admittances in conjunction with the device parameters BL = Imaginary part of the load admittance
can then be used to calculate the transducer gain.1 g11 = Real part of y11
g22 = Real part of y22
2 (g11 + Gs) (g22 + GL)
k= YL = Complex load admittance
y12 y21 + Re (y12 y21) Ys = Complex source admittance
GT = Transducer gain
k [y12 y21 + Re (y12y21)] g11 YIN = Input admittance
Gs = – g11 YOUT = Output admittance
2 g22
Gmax = Maximum gain without feedback

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Computer solutions of these equations for various values of a lumped–constant element, would be a lossless coil. This
of k versus frequency have been plotted in Appendix I for loading will result in a stability factor, k, of 4 and a power
the 2N4957. These curves include common-base (Figures gain of 15 dB, the maximum power gain possible for k = 4.
10 through 16) and common-emitter (Figures 17 through 22). This loading does not include stray capacitance. If stray
From these curves, the designer can determine the input capacitance is assumed to be 1 pF, the actual load is
and output loading admittances for maximum power gain at 1.53 mmhos, –j13.5 mmhos (see Figure 1).
a particular circuit stability. In addition, the transducer power
gain under these conditions can also be determined. Thus
the designer, rather than reading s or y parameters from a
curve and using this information to design an amplifier, has  "'&
all the design equations solved and presented in convenient, &)!$
computer-derived design curves.
The following example demonstrates how these curves
 Ω
can be utilized in the design of a 1 GHz amplifier using the
2N4957. In addition, a second example is shown to   0   22/35
demonstrate the special case where input admittance is
determined primarily by noise figure considerations rather
than by maximum power gain. 
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1 GHz AMPLIFIER DESIGN &%&

A preliminary investigation of stability and power gain,

common-emitter and common-base, can be quickly made
from the design curves. For instance, the unilateralized gain    0  22/35
(Figure 8) at 1 GHz is approximately 15 dB for either the
common-emitter or common-base configuration. Also, the C
factor for the common-base configuration (Figure 10) is
!'&"'&
greater than one and indicates potential device instability. &)!$
However, the C factor for the common-emitter configuration
(Figure 17) is less than one and indicates unconditional  Ω
device stability.
Figures 16 and 22 are key curves that show transducer
power gain for the common base and common emitter .  7
(  (
configuration respectively. Assuming a circuit stability factor
  2
of 4*, power gain is approximately 15 dB, common–base.
Although the common-emitter curve is not extended to 1 GHz Figure 1. Common Base Input and Output Admittances
(since this is a region of unconditional stability) power gain Including Stray Capacitance
for k = 4 would be obviously much less than 15 dB.
Using the common base configuration with k = 4, the To facilitate instrumentation, both the source and load
required input and output admittance for maximum power impedance will be 50 ohms. This admittance level must be
gain can be determined directly from Figures 11 through 16. transformed to the required device loading admittance. Micro
For instance, the real part of the output admittance can strip techniques provide a convenient method of achieving
be read from either Figure 11 or 12. Figure 12 is an expanded this transformation without circuit reproducibility and
version of Figure 11 and is intended to facilitate lower component loss problems that are common with many
frequency use. The imaginary portion of the output lumped constant circuits at this frequency.
admittance is shown in Figure 13. Figures 14 and 15 show The Smith Chart is a convenient design tool for solving
the real and imaginary portions of the input admittance transmission line problems of this type. Since space does
respectively. The resultant input and output admittances are not permit, familiarity with this chart will be assumed.
shown in Figure 1 and are summarized: Starting with the output circuit, both the 50 ohm
Conditions: (2N4957) (20 mmhos) load and the desired collector admittance are
VCE = 10 V plotted on the Smith Chart (see Figure 2). As a starting point,
IC = 2 mA a characteristic admittance of 20 mmhos will be assumed.
f = 1 GHz First, the 20 mmho load is plotted (point A, Figure 2), then
GT = 15 dB point B is plotted (1.53 mmhos –j13.5 mmhos).
k =4 Although many different methods exist for transforming
Input admittance = 69.5 mmhos +j27.1 mmhos point A to point B (see Figure 2), a direct, and as it turns
Output admittance = 1.53 mmhos –j7.46 mmhos out, practical approach is that shown in Figure 3. This circuit
uses C1 in parallel with RL to vary the SWR of point A
It becomes apparent that the emitter must “see” an
(Figure 2) to point C. Since point C has the same SWR as
admittance of 69.5 mmhos shunted by a susceptance of
+j27.1 mmhos. The latter, in terms of a lumped constant
element, would be a lossless capacitor. Likewise, the * For the purpose of this report a stability factor of 4 is chosen. Values
collector would be required to see an admittance of of k less than 4 may not prove to be advantageous from the stand-
1.53 mmhos shunted by –j7.46 mmhos. The latter, in terms point of regeneration and parameter spread.

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variable component C1 is more convenient. A typical curve
of Q versus capacitance for (C1) is shown in Figure 4.
The output bias is fed through a 4000 ohm resistor rather
than an RF choke. The resultant 8 volt drop across this
resistor is easier to contend with than the circuit instabilities
sometimes associated with RF chokes.
The same procedure is followed in designing the input
network (see Figure 5). Again, a stray capacitance of 1 pF
is assumed. Thus, the actual input loading becomes
69.5 mmhos +j21.3 mmhos. First, the 20 mmho load is
Chart Not Available Electronically plotted (see Point T, Figure 6). Next, point W is plotted
(69.5 mmhos +j21.3 mmhos). Adjusting the SWR with C3
(point V) allows a transmission line of length L2 to transform
the admittance at point V to the desired level at the base
(point W).

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Figure 2. Output Network Design

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Figure 4. Q versus Capacitance for C1 @ 1 GHz

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Figure 3. Output Network

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point B, a line L1 with an electrical length equal to 0.405λ2
(point E) minus 0.214λ (point D) will complete the trans-  
formation. Collector tuning is available with component C2. 1    4    4
This variable capacitor provides the difference between the
assumed stray capacitance and the actual circuit stray ca-
pacitance.  4
The required SWR could have been realized by using an
inductor in place of C1. However, an inductor would have (
either forced the bias feed-point to be changed to the
collector lead or necessitated a dc-isolated coil. Although this
is readily attainable using transmission line techniques, the Figure 5. Input Network

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constant was judged insignificant. However, this error
increases for larger values of characteristic impedance and
may prove to be quite significant for other laminates or
narrower line widths. A good precaution would be to measure
wavelength versus line width on each laminate used before
TEM propagation is assumed.
Although the lines can be produced by a masking-etch
process, adequate results can be obtained by cutting the
desired strip from a thin copper sheet and gluing this strip
to the teflon glass board. The latter is a convenient method
Chart Not Available Electronically for making rapid design changes.
The author observes several precautions which may or
may not be necessary for all applications:
1. All breadboards have a ground strap which encompasses
the outer periphery of the board. This strip is soldered to
both the top and bottom copper sheets to effectively ground
the outer periphery of the amplifier on all four sides. The cir-
cuit dimensions are held to a minimum to keep the ground
planes as short as possible.
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2. All RF connectors are carefully connected with grounding

surfaces soldered to the ground plate. For instance, mount
the connectors* perpendicularly to the board at a point
where the connection to the center conductor is a minimum
Figure 6. Input Network Design length. Completely solder the outer conductor to the cop-
per sheet on the opposite side of the board. Poorly
CIRCUIT CONSTRUCTION mounted connectors may result in poor transitions and un-
The transmission line lengths L1 and L2 are readily predictable impedance transformations. For example,
transferred to micro-strip lengths once the wavelength and tacking the outer barrel of this connector to the line side of
line-width are known. Hopefully, this information is available the board may seriously alter the predicted impedance lev-
from the manufacturer, but if not, it must be measured before el at the collector.
the design can be completed. The laminate used for this The amplifier was constructed as specified and the
application required a line-width of approximately 0.16 inches admittance levels were measured at the emitter and collector
for a 20 mmho characteristic admittance. This value proved pins. These admittance levels were checked and adjusted
adequate both from a realizable design solution on the Smith to the original design values with C1, C2, C3, and C4.
Chart and also from a practicable circuit construction The 2N4957 was then soldered directly into the circuit
standpoint. with minimum lead length. The resultant power gain was
The actual laminate thickness depends to a large extent 14.3 dB and the noise figure, 6.5 dB, which is within 1 dB
on the desired characteristic impedance and the frequency of the original design requirements. Attempts to re-adjust the
of operation. The line thickness for a 50 ohm line is input loading and output loading for lower noise figure
approximately 0.16 inch for a 1/16 inch laminate and resulted in lower noise figure with decreased circuit stability.
approximately 0.035 inch for the same laminate 1/64 inch Although the circuit (adjusted for minimum noise figure) didn’t
thick. As the intended frequency of operation is increased, oscillate, the calculated k factor from the resultant input and
the line width becomes a larger percentage of the line output admittances was approximately 2.
length.4 Higher ratios of line width to length may result in
undesirable modes of operation. Decreasing the laminate LOW NOISE DESIGN
thickness results in a smaller line width for the same Improvement in noise figure is possible by arbitrarily
characteristic (assuming TEM operation) and a smaller line adjusting the input and output loading. For the purpose of
width to length ratio. this paper, the stability factor (k = 4) will be retained.
The dielectric constant for the material used was 2.6. The However, the design curves represent the maximum
actual wavelength in the laminate is: power gain case. Although the circuit stability factor can be
λ (air) 11.8 inches maintained at k = 4, varying the source loading will result
λ (actual) = = = 7.34 inches in less power gain than indicated in the design curves.
2.6 2.6
The procedure for this case is as follows:
Since L1 = 0.191λ, First, the optimum source resistance is calculated (see
The physical length of L1 is 1.4 inches Appendix ) and found to be 43Ω.** The calculated noise
figure for this source is 5 dB. In addition, the source
Correspondingly, L2 is 0.062λ or 0.455 inches.
reactance was empirically determined to be inductive
It should be pointed out that the actual wavelength3 for (j119Ω).
this laminate is somewhat larger than that calculated from
the dielectric constant. A careful measurement4 of *General Radio Cable Connector 874-G58B.
wavelength versus characteristic impedance (line width) **The actual value of optimum source resistance was empirically de-
demonstrates this phenomena. The slight increase in termined to be 35Ω. Consequently this value was used for the input
wavelength (6%) from that calculated using the dielectric circuit design rather than 43Ω.

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Second, the collector loading was calculated for a stability required re-design (see Figure 7). The calculated value of
factor of 4. Using these values of source resistance and this line length is 1.15 inches as contrasted with .46 inches
stability factor, the calculated gain (GT) and collector loading used in the first example. The complete amplifier is shown
is 11.8 dB and 3.41 mmhos – 7.5 mmhos (neglecting stray in Figure 9.
capacitance). The resultant power gain and noise figure was 11.8 dB
The output network was readily adjusted to the desired and 5.5 dB. These figures compare well with the calculated
collector loading. However, the input line was too short and design.

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Figure 7. Low Noise Input Design Figure 8. Unilateralized Power Gain versus Frequency

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Figure 9. 1 GHz Amplifier Figure 10. Linvill Stability Factor versus Frequency

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Figures 11 and 12. Load Admittance versus Frequency Figure 13. Load Admittance versus Frequency
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Figure 15. Source Admittance versus Frequency

Figure 14. Source Admittance versus frequency (Real) (Imaginary)

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Figure 16. Transducer Gain versus Frequency Figure 17. Linvill Stability Factor versus Frequency

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Figure 19. Load Admittance versus Frequency

Figure 18. Load Admittance versus Frequency (Real) (Imaginary)
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Figure 21. Source Admittance versus Frequency

Figure 20. Source Admittance versus Frequency (Real) (Imaginary)

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Figure 22. Transducer Gain versus Frequency

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APPENDIX Using Stern’s stability equator for k = 4 (see Table 1):

LOW NOISE DESIGN 2 (g11 + Gs) – (g22 + GL)

k=
y12 y21 + Re (y12 Y21)
The procedure followed in designing this amplifier is to
first calculate the optimum source resistance for optimum and calculating GL for GS = 25 mmhos (40 ohms)
noise figure and then calculate the collector loading for a
required value of k. GL = 3.41 mmhos
A first approximation of optimum source resistance for The transducer gain can be calculated from these
optimum noise figure is:2 impedance levels:
k1
RgF(opt) = k 22 + 4 Re (Ys) Re (YL) y212
k3 GT =
(y11 + Ys) (y22 + YL) – y12 y21)2
re GT = 11.8 dB
k1 = rb +
2
k2 = rb + re
Table 1.
1 + (Bo + 1)  f
2
fαb f = 1 GHz VCB = 10 V IC = 2 mA
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k3 =
2Bore yib = 25 –j25

Assuming the above parameters for the 2N4957 are: yob = 0.55 +j7.54
rb = 12.5 ohms yfb = – 4.99 +j41
re = 13 ohms yrb = – 0.01 –j1.19
Bo = 40
fαb = 1600 MHz, REFERENCES

RgF(opt) = 43 ohms
1. R. Hejhall, “RF Small Signal Design Using Admittance Pa-
The noise figure using this source resistance is available rameters”, Motorola Application Note AN-215A, Motorola
from Nielsen’s equation:2 Semiconductor Products, Inc., Phoenix, Arizona.
2. E. G. Nielsen, “Behavior of Noise Figure in Junction Tran-
NF = 1 +
re
+
rb
+
(Rg + re + rb)2
1 + (Bo + 1)  
f 2
sistors,” Proc. IRE, Vol. 45, p. 957, July 1957.
2Rg Rg 2 Bo Rg re fαb
3. F. Assadourian and E. Rimai, “Simplified Theory of Micro-
strip Transmission Systems”, Proc. IRE, pp. 1651–1663,
Using the previous parameter values, December 1953.
NF = 5 dB 4. M. Arditi, “Experimental Determination of the Properties of
Since the impedance level is different at the base, the Microstrip Components,” Electrical Communication, De-
collector loading must be re-designed. cember 1953.

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