IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO.

4, APRIL 2022 3303

A Direct Modulation for Matrix Converters Based

on the One-Cycle Atomic Operation
Developed in Verilog HDL
Pawel Szczepankowski , Member, IEEE, Wojciech Sleszynski , Member, IEEE, and Tomasz Bajdecki

Abstract—This article presents a fast direct pulsewidth si , so Input and output voltage sectors.
modulation (PWM) algorithm for the conventional matrix ωi = 2πfi , where fi is the input frequency.
converters developed in Verilog hardware description lan- ωo = 2πfo , where fo is the output frequency.
guage. All PWM duty cycle calculations are performed in
one cycle by an atomic operation designed as a digital q =√Vo /Vi , Voltage transfer ratio.
module using field-programmable gate array basic blocks. qmax = 3/2, Maximum value of q.
The algorithm can be extended to any number of output TPWM Modulation period.
phases. The improved version of the discontinuous direct fs = 1/TPWM sampling frequency.
analytic voltage PWM (DAV-PWM) method is proposed, in
which the use of trigonometry, angles, and program loops
has been eliminated. The proposed DAV-PWM is equivalent I. INTRODUCTION
to the space vector modulation; it can be applied during
CONVENTIONAL matrix converter (CMC), shown in
input asymmetry and also allows for the control of the
displacement input angle. The proposal has been verified
using the circuit simulation in PSIM, digital structure mod-
A Fig. 1, contains semiconductor switches arranged into a
matrix configuration divided into three cells: {h11 , h21 , h31 },
eling in ModelSim, and finally through an experiment.
{h12 , h22 , h32 }, and {h13 , h23 , h33 }. Compared to ac–dc–ac
Index Terms—AC–AC converters, field-programmable back-to-back converters with large capacitors in the dc link,
gate array (FPGA) device, matrix converters, pulsewidth the CMC allows for direct ac–ac conversion using the small
modulation (PWM). input filter, which is an advantage of these solutions [1]–[3].
The general motor drive application scheme with the matrix
NOMENCLATURE converter is illustrated in Fig. 1. Such a topology permits for
T Transposition of the matrix. regenerative power from the electrical motor M with negligible
vi Measured input voltages [vi1 , vi2 , vi3 ]T . input grid current harmonic content. An important feature of the
vo Averaged output voltages [vo1 , vo2 , vo3 ]T . CMC control is the possibility to adjust the input displacement
ii Averaged input currents [ii1 , ii2 , ii3 ]T . angle to zero [4]–[6]. The single switch h can be built from two
io Measured output currents [io1 , io2 , io3 ]T . transistors with two diodes or two reverse-blocking insulated-
D PWM duty cycle matrix with size 3 × 3. gate bipolar transistor (RB-IGBT) devices [1], [7].
x Real signal component. The single CMC’s cell is properly controlled to prevent line-
y Imaginary signal component. to-line short circuits and to maintain a continuous waveform of
v ix Matrix of vi in-phase components. the load current. Due to the safe commutation process require-
v iy Matrix of vi quadrature components. ment, the dead-time mechanism should be applied during the
v ox Real parts of reference voltages [vo1x , vo2x , vo3x ]T . generation of switch control signals. The overvoltage upon the
v oy Imaginary parts of reference voltages switch, caused by an interruption of the inductive current, has to
[vo1y , vo2y , vo3y ]T . be absorbed by a clamp circuit [8], [9]. The reduction of the scale
φi Input displacement angle. of both the input filters and the clamp circuit can be reached by
applying faster semiconductors with a high operation frequency;
Manuscript received August 5, 2020; revised December 23, 2020 thus, a panel size of the CMC can be significantly reduced [10].
and February 25, 2021; accepted April 19, 2021. Date of publication Attempts to integrate this panel with the electric motor have al-
May 5, 2021; date of current version December 20, 2021. This work
was supported by the Linte laboratory. (Corresponding author: Pawel ready taken place [11]. Gallium nitride (GaN) and silicon carbide
Szczepankowski.) (SiC) semiconductors offer fundamental advantages over silicon
Pawel Szczepankowski and Wojciech Sleszynski are with the solutions [12]–[15]. The switch’s operation frequency can be
Gdańsk University of Technology, 80-233 Gdańsk, Poland (e-mail:
[email protected]; [email protected]). very high compared to the silicon counterparts, which makes
Tomasz Bajdecki is with the Institute of Power Engineering Gdańsk, these devices great for high-frequency applications, which also
80-870 Gdańsk, Poland (e-mail: [email protected]). include high-speed drives in compressors or high-speed genera-
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TIE.2021.3076703. tors in gas turbines [16]–[18]. Such applications require complex
Digital Object Identifier 10.1109/TIE.2021.3076703 calculations within a short period of time.
This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see http://creativecommons.org/licenses/by/4.0/
3304 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 4, APRIL 2022

TABLE I
SUMMARY OF THE CONDUCTED RESEARCH PATH

Fig. 1. Classic matrix converter and its typical application scheme.

This article presents an approach to computations performed

in a field-programmable gate array (FPGA) in one step, during
one cycle, without trigonometry and angles. Thus, the execution
time of the PWM duty cycle calculation is atomic and limited
only by the critical timing constraints of the FPGA device.
The development of a digital structure that performs such an
algorithm, in one clock cycle, requires the use of an appropriate
modulation method that uses only simple arithmetic operations
supported by Verilog HDL. Moreover, the proposed solution
should allow us to obtain the maximum voltage transfer ratio
and to adjust the angle at the input of the system, which is a
characteristic feature of the PWM for the CMC [1].
Fig. 2. DSOGI-OSG structure in continuous time domain.
PWM strategies for the CMC have been widely reported
in the literature, such as the direct control by the Venturini
approach [3], [19], [20], scalar control realized according to the
Roy method [21], and the space vector modulation (SVM) [1], an FPGA device. This article mainly addresses this issue and
[22]. Other control methods, such as hysteresis and direct torque proposes certain improvements, which are clarified in Section
control, are interesting alternatives [23], [24]. However, the II. The theoretical basis of an improved DAV-PWM algorithm,
torque ripple in the low-speed region or switching frequency ready for the hardware description language (HDL) conversion,
variations according to the change of the motor speed are draw- has been presented in the next section. Power electronics sim-
backs of these approaches. The aforementioned methods are not ulation, modeling based on the HDL, and hardware-in-the-loop
suitable for developing the simplest solution, which should be (HIL) verification have been presented in Section IV. The con-
built from basic digital elements such as multiplexes, adders, and ducted research path is summarized in Table I. Experimental
multipliers. A simplified carrier-based modulator based on the results are presented in Section V. The Verilog HDL code of
concept of a virtual matrix converter was presented in [25]. The the improved DAV-PWM algorithm is available in an Appendix
proposed algorithm allows for obtaining the same instantaneous after the conclusion section.
matrix states as the SVM method with a smaller number of
calculations. Although the solution represents a more synthetic
and systematic approach, this original approach has a major II. PROPOSAL FOR CHANGES IN THE DAV-PWM
disadvantage. An input displacement angle is permanently equal
to zero and cannot be adjusted. The use of an FPGA chip offers new possibilities to design
The concept of simplifying and generalizing the PWM algo- the computation structure with a short execution time, provided
rithm is also presented in [26] and [27]. As with the previous that these algorithms do not use advanced mathematical func-
method, the proposal makes it possible to calculate PWM duty tions, such as trigonometric functions, and do not contain the
cycles without trigonometry with minimal computational effort. program loops. Therefore, the computation scheme of the DAV-
Moreover, the proposed computation scheme allows for the PWM should be optimized. The most important modifications
application of various methods of power factor control. Among of the DAV-PWM algorithm are explained in the following
the described modulation methods, the authors indicated that the subsections.
direct analytic voltage pulsewidth modulation (DAV-PWM) is
optimal because it allows reaching the maximum voltage transfer
A. Quadrature Component Generation of an
ratio equal to 0.866 with the same switch state collection as
Input Voltage
the SVM modulation. This algorithm has been developed as a
sequential code, which contains a program loop for preselection Each input voltage with the pulsation, ωi can be expressed as
input voltage vectors. Such a program loop has to be eliminated a rotating vector, as shown in Fig. 3. For pure sinusoidal input
within the atomic and concurrent implementation based on voltages with an amplitude V , the imaginary coordinates are just
SZCZEPANKOWSKI et al.: DIRECT MODULATION FOR MATRIX CONVERTERS BASED ON THE ONE-CYCLE ATOMIC OPERATION 3305

Fig. 3. Regulation of an input power factor in CMC by tilting the

trajectory Γ.

Fig. 4. Schematic diagram of the improved DAV-PWM algorithm.

quadrature components. Thus, the analytic signals correspond-
ing to input voltages can be expressed as follows:
⎡ ⎤
cos(ωi t) sin(ωi t) min = MIN{cos(ωo ), cos(ωo − 2π/3), cos(ωo + 2π/3)}.
vi = V ⎣ cos(ωi t − 2π/3) sin(ωi t − 2π/3) ⎦ . (1) o

cos(ωi t + 2π/3) sin(ωi t + 2π/3) (3)

If the input voltages are not perfectly sinusoidal, all co- To achieve the maximum voltage transfer ratio, the trajectory Γ
ordinates should be determined using Hilbert filter or should to be shifted to the nearest vertex of the triangle Δ[1,2,3] .
fast-Fourier-transform/discrete-Fourier-transform-based opera- According to the original DAV-PWM algorithm, coordinates of
tion [28]–[30], which cannot be easily implemented in the FPGA the shift vector are designated by the program loop routine, in
without using an advanced intellectual property core. However, which the algorithm selects the best candidate among the input
calculations using Clarke’s triple transforms, although simple, in voltage vector set [26]. This solution can also be improved to
the case of asymmetry cause a distortion of the input current [26]. meet the optimization requirements. The Gamma Γ modification
In practice, error signals in the form of dc offsets, glitches, and in (2) can be replaced by a formula containing a rotation matrix.
momentary voltage sags may occur in measurements. Therefore, Thus, the relation between input and output voltages in the CMC
coordinates can be computed by double second-order gener- may be written in a following general form:
alized integrator with loop feedback extension functioning as vo · R = D · vi (4)
orthogonal signal generator (DSOGI-OSG), shown in Fig. 2,
which in the OSG part prevents unexpected resonance and where
variable overflow [31]–[33]. If processed signal frequency does 
cos (φi ) − sin (φi )
not have an exact value, another extension of the second-order R= (5)
sin (φi ) cos (φi )
generalized integrator structure, called the frequency-locked
loop (FLL), may be applied [34]–[36]. and D is a square matrix that contains all PWM duty cycles
⎡ ⎤
d11 d12 d13
B. Simpler Approach to the Input Displacement D = ⎣ d21 d22 d23 ⎦ (6)
Angle Regulation d31 d32 d33
According to the concept proposed in [26] and [27], an input
for switches h11 –h33 . Taking into account the properties of the
angle displacement regulation is realized by tilting the trajectory
R matrix, (4) can be finally rewritten as
Γ by the desired displacement angle, exactly equal to φi , as
illustrated in Fig. 3. The modification of the Γ trajectory results vo = D · (vi · R−1 ) = D · viR . (7)
in decreasing the voltage transfer ratio q. Thus, reference output
voltages can be represented by the following formula: Now, the desired angle of displacement φi can be achieved by
⎡ ⎤ the angular displacement of the input vector collection (1). This
cos (ωo ) + vcm   result has a significant impact on the optimization of the original
vo = q · cos(φi ) ⎣ cos (ωo − 2π) + vcm ⎦ 1 tan (φi ) (2) DAV-PWM algorithm because all calculations can be performed
cos (ωo + 2π) + vcm for reference voltage, which always has a zero imaginary com-
where the common-mode signal vcm is expressed as follows: ponent. Hence, the selection of the shift coordinates is simplified
and is free from an undesired program loop. Reference to the
vcm = −0.5(max + min) new synthesis field ΔR[1,2,3] shown in Fig. 4, the shift vector
o o
always corresponds to an intermediate vertex between the top
max = MAX{cos(ωo ), cos(ωo − 2π/3), cos(ωo + 2π/3)} and the bottom vertex, which can be immediately selected in
o
3306 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 4, APRIL 2022

Fig. 7. Two periods of the load voltage for the ten-switch double-sided
modulator for the conventional SVM method.
Fig. 5. Identifying the sector of the rotated input vectors using three
comparators during an amplitude asymmetry.
TABLE II
DEPENDENCE OF THE SHIFT VECTOR COORDINATES vs , maxo , AND mino
ON INPUT AND OUTPUT SECTOR NUMBER

Fig. 6. Three selected source voltage conditions during operation with

a unity power factor at the input—simulation using PSIM11 software.
TABLE III
PWM DUTY CYCLE MATRICES D WITHIN AN INPUT AND OUTPUT VOLTAGE
SECTORS IN DAV-PWM
a much simpler way using comparators instead of the program
loop.

C. Simplification of the Reference Output

Voltage Generation
The trajectory shift operation eliminates the common voltage
from (2). Therefore, this component can be deleted in the pro-
posed version of the DAV-PWM algorithm. As a consequence,
only the sinusoidal voltage references can be applied in the 
algorithm. viR1x − vo (1, 1) viR1y − vo (1, 2)
d21 = ξ · det (10)
viR3x − vo (1, 1) viR3y − vo (1, 2)
III. IMPROVED DAV-PWM ALGORITHM d31 = 1 − d11 − d21 (11)
A schematic diagram of the improved DAV-PWM algorithm
where det means the determinant of the 2 × 2 matrix, and
is presented in Fig. 5. The input voltage {vi1 , vi2 , vi3 } from  −1
measurements is converted into analytic signal pairs using the v − viR1x viR2y − viR1y
ξ = det iR2x . (12)
DSOGI-OSG or DSOGI-FLL structure. Next, all input vec- viR3x − viR1x viR3y − viR1y
tors are multiplied by the rotation matrix R (5), which takes
Other PWM duty cycles, in the second and third rows of (8),
arguments—cos φi and sin φi —from the input power factor
can be computed analogously. The PWM duty cycle matrices D
control routine. Three coordinates pairs for modulating signals
within an input siR and output so voltage sectors in DAV-PWM
⎡ ⎤
vo1x + vsx vsy are summarized in Table III. The D matrix consists of nine
vo = ⎣ vo2x + vsx vsy ⎦ (8) duty cycles d11 –d33 , which are transformed into the sequence
vo3x + vsx vsy of logical signals for switch state control. These sequences are
usually generated by the specialized digital structure based on
are selected according to the input sector siR and the output counters and comparators according to the selected commutation
sector so . Both sectors are directly identified using comparators, strategy in the CMC [37]–[41]. The cyclic Venturini approach
as shown in Figs. 6 and 7. and the four-step commutation strategy have been chosen [5].
Dependencies of the shift vector coordinates on the input and
output sectors are referred to Table II. The collection of PWM IV. POWER ELECTRONICS SIMULATION, HDL MODELING,
duty cycles for switches h11 , h21 , and h31 can be calculated AND HIL VERIFICATION
without trigonometry and angles using the following formulas:
 This section presents results obtained during the functional
v − vo (1, 1) viR2y − vo (1, 2)
d11 = ξ · det iR2x (9) simulation in PSIM11 software, behavioral modeling of the
viR3x − vo (1, 1) viR3y − vo (1, 2) HDL using ModelSim Intel FPGA environment, and the HIL
SZCZEPANKOWSKI et al.: DIRECT MODULATION FOR MATRIX CONVERTERS BASED ON THE ONE-CYCLE ATOMIC OPERATION 3307

TABLE IV
SWITCH STATE COLLECTION FOR THE SVM METHOD

Fig. 9. Waveforms in the analog form obtained by modeling of the DAV-

PWM algorithm written in Verilog HDL using ModelSim environment. (a)
q = 0.86, φi = 0, and ωi = 2ωo . (b) q = 0.75, φi = −π/6, and ωi = 2ωo .

Fig. 8. ModelSim simplified simulation diagram.

Fig. 10. Early validation scheme of the improved DAV-PWM algorithm

verification using Quartus Intel FPGA software with the signal- developed in Verilog HDL.
tap logic analyzer (STLA) tool.
TABLE V
DECODED SVM SWITCHING SEQUENCES FOR DAV-PWM WITH THE
A. Simulation and Switch State Sequences Comparison CYCLIC VENTURINI SCHEME
for DAV-PWM and SVM
The PSIM environment was used to simulate CMC control
and verify the algorithm compiled as the user DLL block, which
is written in C language. The proposed improved algorithm
maintains the important properties of DAV-PWM proposed
in [26]. The obtained sequences of switch states, including the
waveforms of line-to-line voltages, remain unchanged. An input
voltage amplitude asymmetry or phase angle disturbance change
the shape and area of the synthesis field limiting the value of
The following major conclusions can be formulated based on
the voltage transfer ratio q. However, during operation with a
the switch state sequence comparison.
unity power factor, currents on both sides of the converter are
1) Both the SVM method and DAV-PWM use the same
sinusoidal, as can be seen in Fig. 8, where three selected input
active vectors in their input and output voltage sectors.
conditions for RL load type are presented. This article proposes
2) The construction of the switch state sequences in the DAV-
a direct modulation algorithm, in which the switch states are
PWM method is identical to that of sequences in SVM
not explicitly declared as in the conventional SVM modulation
shown in Fig. 10.
method. Table IV presents all switch states of the CMC. Black
3) The proposed DAV-PWM allows for reducing the har-
dots represent the active switches in the matrix panel.
monic distortion by having two zero vectors per period, as
Several modulation techniques are compared in [42] and
reported in [42], but only the approach illustrated in Fig. 9
analyzed in [43]. Among the described switch state sequences,
permits for reduction of switch operation frequency.
two of them can be distinguished: ten-switch double-sided se-
4) Tabularizing the switch state sequences is not necessary
quence shown in Fig. 9 and low-distortion eight-switch sequence
for a carrier-based modulation such as DAV-PWM.
illustrated in Fig. 10. The switch states for DAV-PWM can be
derived using the switch state parser connected with all nine
control signals h11 –h33 . The state parser is a MATLAB script, B. HDL Compilation
which operates on the PSIM data saved in the CSV file format. The ModelSim software was applied for modeling the digital
Decoded SVM switching sequences for DAV-PWM with the module of the PWM duty cycle computation, in which the
cyclic Venturini scheme are collected in Table V. behavioral equivalent of the C-language-developed DAV-PWM
3308 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 4, APRIL 2022

(a)

(b)

Fig. 11. 5-kW matrix converter with the DSP–FPGA control board. Fig. 12. Schematic diagram of the experiment configuration.

had been coded using Verilog HDL. The ModelSim-simplified

simulation diagram is shown in Fig. 11. This software is usually
dedicated for digital core or module simulation, but, here, that
software has been used for developing the matrix converter
control module. The fixed-point Q15 format arithmetic, in
comparison with the single-precision format, often permits for
developing very fast algorithms without pipelines and recursive
operations. Continuous signals, such as input voltages, can be
represented by the large tables of 16-bit values. The discrete
sampling time was generated by the counter with auto-reload.
An input displacement angle has been expressed as a sin–cos
pair expressed by constant Q15 values. For simulation purpose
only, the cyclic Venturini switching strategy was developed in
Verilog HDL using nonsynthesizable modeling based on the
signal delay command. This Verilog HDL piece of code is inten- Fig. 13. Block diagram of computation performed by the FPGA device
tionally depicted in the drawing. Selected electrical waveforms, during an experiment.
sectors, and PWM duty cycles in the analog form, modeled
using ModelSim simulation environment, are shown in Fig. 12. TABLE VI
The load current was modeled using the first-order infinite IMPROVED DAV-PWM DUTY CYCLE COMPUTATION
impulse response (IIR) filter. All line-to-line load voltages were MODULE RESOURCE UTILIZATION
generated using the signal switching approach controlled by the
input sector number.

C. HIL Verification
For early validation of the Verilog HDL project file syn-
thesizability, the Quartus 18.1 with the STLA was used. An
evaluation board DE10-Lite was used during the HIL test. Two to visualize and record the selected signals in real time. Fig. 14
debugging tools were used during the validation stage. As shown shows improved DAV-PWM algorithm signals during the debug
in Fig. 13, the In-System Sources and Probes tool was used session using the STLA for ωi /ωo = 2.67, fs = 1 MHz, and
to give phase and frequency of signals generated by CORDIC q = 0.8. The proposed PWM duty cycle computation module
numerically controlled oscillators, while the STLA tool allowed resource utilization is presented in Table VI.
SZCZEPANKOWSKI et al.: DIRECT MODULATION FOR MATRIX CONVERTERS BASED ON THE ONE-CYCLE ATOMIC OPERATION 3309

Fig. 17. The block diagram of performed computation by FPGA device

during an experiment.

Fig. 14. Experimental results for ωo /ωi = 0.5 and symmetric input am-
plitudes for (a) unity power factor (q = 0.86 and φi = 0) and (b) reactive
power generation (q = 0.6 and φi = −π/4).

(a)

Fig. 15. Output and input currents for asymmetrical input voltage
source for DAV-PWM: q = 0.55 and ωo /ωi = 0.5.

(b)

Fig. 18. Experimental results for ωo /ωi = 0.5 and symmetric input
amplitudes for: (a) unity power factor, (b) reactive power generation.

is needed to preserve constant modulation frequency. The mod-

Fig. 16. The schematic diagram of the experiment configuration. ulation period was 100 μs, while algorithm computation in Q15
blocks was accomplished through 100-ns positive clock pulse.
V. EXPERIMENTAL RESULTS The waveforms for the normal operation with a zero displace-
ment angle value φi and modulation with φi = −π/4 are shown
A 5-kW CMC with the control board, shown in Fig. 15, based in Fig. 18. The proposed modulation method can be used in the
on the multicore ADSP-SC589 DSP from Analog Devices and case of supply voltage asymmetry. Despite such conditions, the
the MAX10 Intel FPGA device was used during the experimen- input currents in each phase are sinusoidal. Experimental re-
tal stage. The bidirectional power switch was build using two sults for a significant asymmetry of input voltages (Vi1 = 75 V,
SiC transistors C3M0075120D. The schematic diagram of the Vi2 = 100 V, and Vi3 = 125 V) are shown in Fig. 19.
experiment configuration is shown in Fig. 16. The block diagram
of computation performed by the FPGA device during an exper-
VI. CONCLUSION
iment is presented in Fig. 17. The Q15 symbol indicates digital
structures based on fixed-point arithmetic, while SP means the The proposed computation scheme of PWM duty cycles did
floating-point IP core used for time cycle scaling. This element not require trigonometry operation and angles resulting in a
3310 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 4, APRIL 2022

TABLE VIII
COMPARISON OF THE PREVIOUS [26] AND THE IMPROVED
DAV-PWM ALGORITHMS

Fig. 19. An output and input currents for asymmetrical input voltage
source for DAV-PWM modulation: q = 0.55, ωo /ωi = 0.5.

TABLE VII
COMPARISON OF THE SVM AND THE
IMPROVED DAV-PWM compilation stage and HIL verification. Moreover, an early func-
tional simulation of the CMC control can be performed using
the ModelSim software. Finally, the solution can be represented
only by one Verilog HDL file; thus, an export to another FPGA
vendor platform is not complicated, and it is not necessary to
explicitly predefine the semiconductor switch states as in the
SVM methods. Each converter cell is controlled independently
in a direct way. This is especially convenient when the number
of outputs is greater than the standard three. Simulation files are
provided in the IEEE DataPort portal to increase understanding
of this article. The first file is a script for the MATLAB environ-
ment, which is a presentation of the proposed modulation. The
second file contains the testbench of the proposed Verilog HDL
modulator [44].

APPENDIX

{The Verilog HDL code of the improved DAV-PWM algorithm.}

//module definition
module ImprovedDAVPWM #(parameter MSB=33,LSB=18)
(
input iCLK,
input signed [15:0] vi1x,vi2x,vi3x,vi1y,vi2y,vi3y,
input signed [15:0] vo1x,vo2x,vo3x,R_cos,R_sin,
output reg[15:0] d11,d21,d31,d12,d22,d32,d13,d23,d33,sum,
output reg [2:0] si,so
);
//x-coordinate difference
reg signed [16:0] vi1x_vo1x,vi2x_vo1x,vi3x_vo1x;
reg signed [16:0] vi1x_vo2x,vi2x_vo2x,vi3x_vo2x;
reg signed [16:0] vi1x_vo3x,vi2x_vo3x,vi3x_vo3x;
//y-coordinate difference
simplistic matrix converter control algorithm. All calculation reg signed [16:0] vi1y_py,vi2y_py,vi3y_py;
//the real line-to-line voltage
was based on basic arithmetic operations that can be easily reg signed [16:0] vi1x_vi2x,vi2x_vi3x,vi3x_vi1x;
//the imaginary line-to-line voltage
implemented in the FPGA within one clock tact. The proposed reg signed [16:0] vi1y_vi2y,vi2y_vi3y,vi3y_vi1y;
general direct modulation was an SVM equivalent when the //minimum and maximum output voltage
reg signed [15:0] min_vox,max_vox;
low-distortion eight-switch double-sided modulator was ap- //shift vector coordinates
reg signed [15:0] vsx,vsy;
plied. However, compared with SVM, the proposed DAV-PWM //input vector coordinates after rotation

algorithm was much simpler. The comparison of the SVM and reg signed [31:0] viR1xx,viR2xx,viR3xx,viR1yy,viR2yy,viR3yy;
//rescaled input vector coordinates
the improved DAV-PWM was presented in Table VII. With reg signed [15:0] viR1x,viR2x,viR3x,viR1y,viR2y,viR3y;
//shifted real coordinates of output voltages
regard to the solution presented in [26], the following benefits reg signed [15:0] vo1xx,vo2xx,vo3xx;
//rational functions for matrix D calc.
were obtained, as presented in Table VIII. reg signed [33:0] d11w,d21w,d31w,d12w,d22w,d32w,d13w,d23w,d33w,d00w;
The discussed approach was suitable and more robust for //absolute rational functions for matrix D calc.
reg signed [33:0] d11ww,d21ww,d31ww,d12ww,d22ww,d32ww,d13ww,d23ww,d33ww,d00ww;
FPGA implementation than a conventional approach such as
//behavioral description
SVM. For a better understanding of the solution developing always @(posedge iCLK)

process, this article also briefly described the HDL project

SZCZEPANKOWSKI et al.: DIRECT MODULATION FOR MATRIX CONVERTERS BASED ON THE ONE-CYCLE ATOMIC OPERATION 3311

begin
[6] W. Xiong et al., “A cost-effective and low-complexity predictive con-
//output voltage sector calculation trol for matrix converters under unbalanced grid voltage conditions,”
so[2]=(vo1x >= vo2x)? 1:0; so[1]=(vo2x >= vo3x)? 1:0; so[0]=(vo3x >= IEEE Access, vol. 7, pp. 43 895–43905, 2019, doi: 10.1109/AC-
vo1x)? 1:0;
CESS.2019.2908446.
//maximum output voltage
case(so) [7] S. Mori, M. Aketa, T. Sakaguchi, H. Asahara, T. Nakamura, and T. Kimoto,
1: max_vox = vo3x;2: max_vox = vo2x;3: max_vox = vo2x; “Suppression of punch-through current in 3 kV 4h-SiC reverse-blocking
4: max_vox = vo1x;5: max_vox = vo3x;6: max_vox = vo1x; MOSFET by using highly doped drift layer,” IEEE J. Electron Devices
endcase
//minimum output voltage
Soc., vol. 6, pp. 449–453, 2018, doi: 10.1109/JEDS.2018.2819681.
case(so) [8] S. Tammaruckwattana, C. Yue, Y. Ikeda, and K. Ohyama, “Comparison
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Wojciech Sleszynski (Member, IEEE) received
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the M.Sc. degree in control engineering and
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the Gdańsk University of Technology, Gdańsk,
filter based frequency-locked loop for three-phase grid voltage,” IEEE
Poland, in 2000 and 2007, respectively.
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Since 2001, he has been with the Faculty of
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Tomasz Bajdecki received the M.S. degree
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in electrical engineering from the Czestochowa
sign measurement,” IEEE Trans. Ind. Electron., vol. 49, no. 2, pp. 407–414, University of Technology, Czstochowa, Poland,
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in 1992, and the Ph.D. degree in electrotechni-
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cal from the Gdańsk University of Technology
symmetrical pulse width modulation strategies for matrix converters,” in
for dissertation “Control strategy for the matrix
Proc. IEEE 33rd Annu. IEEE Power Electron. Spec. Conf., 2002, vol. 2, converter,” Gdańsk, Poland, in 2003.
pp. 899–904.
He is currently a Research Staff Member
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with the Institute of Power Engineering Gdańsk,
for matrix converters,” in Proc. IEEE 32nd Annu. Power Electron. Spec. Gdańsk. His main research interests include
Conf., 2001, vol. 2, pp. 1102–1107.
control of the high-power converters.