+

William Stallings
Computer Organization
and Architecture
10th Edition
+ Chapter 2
Performance Issues
+
Designing for Performance
 The cost of computer systems continues to drop dramatically, while the performance
and capacity of those systems continue to rise equally dramatically

 Today’s laptops have the computing power of an IBM mainframe from 10 or 15 years ago

 Processors are so inexpensive that we now have microprocessors we throw away

 Desktop applications that require the great power of today’s microprocessor-based

systems include:
 Image processing
 Three-dimensional rendering
 Speech recognition
 Videoconferencing
 Multimedia authoring
 Voice and video annotation of files
 Simulation modeling

 Businesses are relying on increasingly powerful servers to handle transaction and

database processing and to support massive client/server networks that have
replaced the huge mainframe computer centers of yesteryear

 Cloud service providers use massive high-performance banks of servers to

satisfy high-volume, high-transaction-rate applications for a broad spectrum of
clients
+
Microprocessor Speed
Techniques built into contemporary processors include:

• Processor moves data or instructions into a

Pipelining conceptual pipe with all stages of the pipe processing
simultaneously

• Processor looks ahead in the instruction code fetched

Branch prediction from memory and predicts which branches, or groups
of instructions, are likely to be processed next

Superscalar • This is the ability to issue more than one instruction in

every processor clock cycle. (In effect, multiple
execution parallel pipelines are used.)

• Processor analyzes which instructions are dependent

Data flow analysis on each other’s results, or data, to create an
optimized schedule of instructions

Speculative • Using branch prediction and data flow analysis, some

processors speculatively execute instructions ahead
of their actual appearance in the program execution,
execution holding the results in temporary locations, keeping
execution engines as busy as possible
+
Performance
Balance
Increase the number
 Adjust the organization and of bits that are
retrieved at one time
architecture to compensate by making DRAMs
“wider” rather than
for the mismatch among the “deeper” and by
using wide bus data
capabilities of the various paths

components
Reduce the frequency
 Architectural examples of memory access by
incorporating
include: increasingly complex
and efficient cache
structures between
the processor and
main memory

Change the DRAM Increase the

interface to make it interconnect
more efficient by bandwidth between
processors and
including a cache or memory by using
other buffering higher speed buses
scheme on the DRAM and a hierarchy of
chip buses to buffer and
structure data flow
Ethernet modem
(max speed)

Graphics display

Wi-Fi modem
(max speed)

Hard disk

Optical disc

Laser printer

Scanner

Mouse

Keyboard

101 102 103 104 105 106 107 108 109 1010 1011
Data Rate (bps)

Figure 2.1 Typical I/O Device Data Rates

+
Improvements in Chip
Organization and Architecture
 Increase hardware speed of processor
 Fundamentally due to shrinking logic gate size
 More gates, packed more tightly, increasing clock rate
 Propagation time for signals reduced

 Increase size and speed of caches

 Dedicating part of processor chip
 Cache access times drop significantly

 Change processor organization and architecture

 Increase effective speed of instruction execution
 Parallelism
+
Problems with Clock Speed and
Login Density
 Power
 Power density increases with density of logic and clock speed
 Dissipating heat

 RC delay
 Speed at which electrons flow limited by resistance and
capacitance of metal wires connecting them
 Delay increases as the RC product increases
 As components on the chip decrease in size, the wire
interconnects become thinner, increasing resistance
 Also, the wires are closer together, increasing capacitance

 Memory latency
 Memory speeds lag processor speeds
107

106
Transistors (Thousands)
105 Frequency (MHz)
Power (W)
104 Cores

103

102
+
10

0.1
1970 1975 1980 1985 1990 1995 2000 2005 2010

Figure 2.2 Processor Trends

 The use of multiple
processors on the same chip
provides the potential to
increase performance

Multicore without increasing the clock

rate

Strategy is to use two simpler

processors on the chip rather
than one more complex
processor

With two processors larger

caches are justified

As caches became larger it

made performance sense to
create two and then three
levels of cache on a chip
+
Many Integrated Core (MIC)
Graphics Processing Unit (GPU)
MIC GPU
 Leap in performance as well  Core designed to perform
as the challenges in parallel operations on graphics
developing software to exploit data
such a large number of cores
 Traditionally found on a plug-in
 The multicore and MIC graphics card, it is used to
strategy involves a encode and render 2D and 3D
homogeneous collection of graphics as well as process
general purpose processors video
on a single chip
 Used as vector processors for a
variety of applications that
require repetitive computations
+  Proposed by Gene Amdahl in 1967

 Deals with the potential speedup of a

program using multiple processors
compared to a single processor
Amdahl’s  Illustrates the problems facing industry

Law
in the development of multi-core
machines
 Software must be adapted to a highly
parallel execution environment to
exploit the power of parallel
processing

 Can be generalized to evaluate and

design technical improvement in a
computer system
 T
(1 – f)T fT

(1 – f)T fT
N

1
1 f 1 T
N

Figure 2.3 Illustration of Amdahl’s Law

Spedup f = 0.95

f = 0.90

+ f = 0.75

f = 0.5

Number of Processors

Figure 2.4 Amdahl’s Law for Multiprocessors

+
Computer Performance
 Clock Speed
 Operations performed by a processor are governed by a
system clock

 The speed of a processor is dictated by the pulse

frequency produced by the clock

 Measured in cycles per second, or Hertz (Hz)

 Example:
 A 1-GHz processor receives 1 billion pulses per second.

 The rate of pulses is known as the clock rate, or clock

speed

 One increment, or pulse, of the clock is referred to as a

clock cycle, or a clock tick
 q
cr uar
ys tz
ta
l

an
co di alog
nv git to
er al
sio
n

From Computer Desktop Encyclopedia

1998, The Computer Language Co.

Figure 2.5 System Clock

+
Benchmarks

For example, consider this high-level language statement:

A = B + C /* assume all quantities in main memory */

With a traditional instruction set architecture, referred to as a complex instruction

set computer (CISC), this instruction can be compiled into one processor
instruction:

add mem(B), mem(C), mem (A)

On a typical RISC machine, the compilation would look something like this:

load mem(B), reg(1);

load mem(C), reg(2);
add reg(1), reg(2), reg(3);
store reg(3), mem (A)
+
Benchmark Principles

 Desirable characteristics of a benchmark

program:

1. It is written in a high-level language, making it

portable across different machines
2. It is representative of a particular kind of
programming domain or paradigm, such as
systems programming, numerical
programming, or commercial programming
3. It can be measured easily
4. It has wide distribution
+
System Performance Evaluation
Corporation (SPEC)
 Benchmark suite
 A collection of programs, defined in a high-level language
 Together attempt to provide a representative test of a computer in
a particular application or system programming area

 SPEC
 An industry consortium
 Defines and maintains the best known collection of benchmark
suites aimed at evaluating computer systems
 Performance measurements are widely used for comparison and
research purposes
+  Best known SPEC benchmark suite

 Industry standard suite for processor

intensive applications
SPEC  Appropriate for measuring
performance for applications that
spend most of their time doing
computation rather than I/O
CPU2006  Consists of 17 floating point programs
written in C, C++, and Fortran and 12
integer programs written in C and C++

 Suite contains over 3 million lines of

code

 Fifth generation of processor intensive

suites from SPEC
 Benchmark Reference Instr Language Application Brief Description
time count Area
(hours) (billion)
Programming PERL programming
400.perlbench 2.71 2,378 C Language language interpreter, applied
to a set of three programs.
Compression General-purpose data
401.bzip2 2.68 2,472 C compression with most work
done in memory, rather than
doing I/O.

Table 2.5
C Compiler Based on gcc Version 3.2,
403.gcc 2.24 1,064 C
generates code for Opteron.
Combinatoria Vehicle scheduling
429.mcf 2.53 327 C l algorithm.
Optimization
Artificial Plays the game of Go, a
445.gobmk 2.91 1,603 C Intelligence simply described but deeply
complex game.

456.hmmer 2.59 3,363 C

Search Gene
Sequence
Protein sequence analysis
using profile hidden Markov
models.
SPEC
458.sjeng 3.36 2,383 C
Artificial
Intelligence
A highly ranked chess
program that also plays
several chess variants.
CPU2006
462.libquantum 5.76 3,555 C
Physics /
Quantum
Computing
Simulates a quantum
computer, running Shor's
polynomial-time
Integer
Benchmarks
factorization algorithm.
Video H.264/AVC (Advanced
464.h264ref 6.15 3,731 C Compression Video Coding) Video
compression.
Discrete Uses the OMNet++ discrete
Event event simulator to model a
471.omnetpp 1.74 687 C++
Simulation large Ethernet campus
network.
Path-finding Pathfinding library for 2D
473.astar 1.95 1,200 C++
Algorithms maps.
XML A modified version of
483.xalancbmk 1.92 1,184 C++ Processing Xalan-C++, which
transforms XML documents
to other document types.

(Table can be found on page 69 in the textbook.)

 Reference Instr count
Benchmark time (hours) (billion) Language Application Area Brief Description
Computes 3D transonic
410.bwaves 3.78 1,176 Fortran Fluid Dynamics transient laminar viscous
flow.
416.gamess 5.44 5,189 Fortran Quantum Quantum chemical
Chemistry computations.
Physics / Quantum Simulates behavior of
433.milc 2.55 937 C
Chromodynamics quarks and gluons
Computational fluid

Table 2.6
434.zeusmp 2.53 1,566 Fortran Physics / CFD dynamics simulation of
astrophysical phenomena.
Simulate Newtonian
Biochemistry /
equations of motion for
435.gromacs 1.98 1,958 C, Fortran Molecular
Dynamics hundreds to millions of
particles.
436.cactusAD 3.32 1,376 C, Fortran Physics / General Solves the Einstein
M Relativity evolution equations.
437.leslie3d

444.namd
2.61

2.23
1,273

2,483
Fortran

C++
Fluid Dynamics
Biology /
Molecular
Model fuel injection flows.
Simulates large
biomolecular systems.
SPEC
CPU2006
Dynamics
Program library targeted at
Finite Element
447.dealII 3.18 2,323 C++ adaptive finite elements and
Analysis

Floating-Point
error estimation.
Linear Test cases include railroad
450.soplex 2.32 703 C++ Programming, planning and military airlift
Optimization models.
453.povray

454.calculix
1.48

2.29
940

3,04`
C++

C, Fortran
Image Ray-tracing
Structural
Mechanics
3D Image rendering.
Finite element code for
linear and nonlinear 3D
Benchmarks
structural applications.
459.GemsFDT Computational Solves the Maxwell
2.95 1,320 Fortran
D Electromagnetics equations in 3D.
Quantum chemistry
Quantum
465.tonto 2.73 2,392 Fortran package, adapted for
Chemistry
crystallographic tasks.
Simulates incompressible
470.lbm 3.82 1,500 C Fluid Dynamics
fluids in 3D.
481.wrf 3.10 1,684 C, Fortran Weather Weather forecasting model
482.sphinx3 5.41 2,472 C Speech recognition Speech recognition
software. (Table can be found on page 70
in the textbook.)
+
Terms Used in SPEC Documentation
 Benchmark  Peak metric
 A program written in a high-level  This enables users to attempt to
language that can be compiled optimize system performance by
and executed on any computer optimizing the compiler output
that implements the compiler
 Speed metric
 System under test  This is simply a measurement of the
 This is the system to be evaluated
time it takes to execute a compiled
benchmark
 Used for comparing the ability of
 Reference machine a computer to complete single
 This is a system used by SPEC to tasks
establish a baseline performance
for all benchmarks  Rate metric
 Each benchmark is run and  This is a measurement of how many
measured on this machine to tasks a computer can accomplish in
establish a reference time for a certain amount of time
that benchmark  This is called a throughput,
capacity, or rate measure
 Base metric  Allows the system under test to
 These are required for all execute simultaneous tasks to
reported results and have strict take advantage of multiple
guidelines for compilation processors
+ Summary Performance
Issues
Chapter 2

 Designing for performance  Basic measures of computer

 Microprocessor speed performance
 Performance balance  Clock speed
 Improvements in chip  Instruction execution rate
organization and
 Benchmark principles
architecture
 Multicore  SPEC benchmarks
 MICs
 GPGPUs
 Amdahl’s Law