Implementation of Up-Counter

Chapter 1. Implementing Up-Counter Using FPGA

1.1 Introduction:

 Up-Counter:
An up counter is a digital device that sequentially counts in an ascending order,
typically starting from zero and incrementing by one with each clock pulse. This
counting mechanism is essential in digital circuits for keeping track of events or
measuring time intervals, playing a significant role in registers and counters. Up
counters can be implemented using various digital logic circuits, including flip-
flops, which are the basic building blocks of sequential logic. The maximum
count of an up counter depends on its bit width; for example, a 4-bit up counter
can count from 0 to 15. Reset functionality is often included in up counters,
allowing them to return to zero when needed. Up counters can be designed as
synchronous or asynchronous, where synchronous counters change states
simultaneously with the clock pulse and asynchronous counters change states
based on the previous output. They are widely used in applications such as
digital clocks, frequency counters, and event counters in various electronic
systems.

 FPGA ( Field programmable gate array) :

A field-programmable gate array (FPGA) is a type of configurable integrated
circuit that can be repeatedly programmed after manufacturing. FPGAs are a
subset of logic devices referred to as programmable logic devices (PLDs). They
consist of an array of programmable logic blocks with a connecting grid, that
can be configured "in the field" to interconnect with other logic blocks to
perform various digital functions. FPGAs are often used in limited (low)
quantity production of custom-made products, and in research and development,
where the higher cost of individual FPGAs is not as important, and where
creating and manufacturing a custom circuit would not be feasible. Other
applications for FPGAs include the telecommunications, automotive, aerospace,
and industrial sectors, which benefit from their flexibility, high signal
processing speed, and parallel processing abilities.

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1.2 Circuit Diagram :

Fig. : Four bit up-counter (MOD-10/ Decade counter)

 Truth Table :

CLR CLK’ event CLK NO. Q3 Q2 Q1 Q0

1 1 0 0 0 0 0
0 1 1 0 0 0 0
0 1 2 0 0 0 1
0 1 3 0 0 1 0
0 1 4 0 0 1 1
0 1 5 0 1 0 0
0 1 6 0 1 1 1
0 1 7 0 1 1 0
0 1 8 0 1 1 1
0 1 9 1 0 0 0
0 1 10 1 0 0 1

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 Implementation of Up-Counter

1.3 VHDL Code for Up-Counter :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MOD_10 is
Port ( CLK : in STD_LOGIC;
LOAD : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR (03 downto 0));
end MOD_10;

architecture MOD_10_Arch of MOD_10 is

SIGNAL TMP : STD_LOGIC_VECTOR (03 downto 0);
begin

P1 : PROCESS (CLK,CLR)
BEGIN
IF (CLK'EVENT AND CLK ='1') THEN
IF CLR = '1' THEN
TMP <= "0000";
ELSIF LOAD = '1' THEN
IF TMP = "1001" THEN

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 Implementation of Up-Counter

TMP <= "0000";

ELSE TMP <= TMP + "0001";
END IF;
END IF;
END IF;
END PROCESS P1;
Q <= TMP;
end MOD_10_Arch;

1.5 Outputs :

Fig. : Output of MOD 10 UP Counter

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 Implementation of Up-Counter

1.6 Applications :

1) Time of Day Clocks: Up counters are fundamental in digital clocks, where

they increment to track seconds, minutes, and hours.
2)Frequency Measurement: Counters can measure the frequency of a signal
by counting the number of pulses within a specific time interval.
3)Event Counting: They can count the number of occurrences of an event, such
as the number of times a button is pressed or a sensor is triggered.
4)Binary Arithmetic: Counters are used in digital systems for performing
binary arithmetic operations like addition, subtraction, multiplication, and
division.
5)Digital Signal Processing: They can be used in applications like filtering and
signal analysis.
6)Microcontrollers and PLCs: Counters are used in microcontroller and PLC
applications to count external events, generate time delays, and control
processes.

1.7 Conclusion :

In conclusion, up counters are fundamental digital circuits that increment their

count value with each clock pulse, finding applications in event counting, time
measurement, and controlling system states, and can be implemented using flip-

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 Implementation of Up-Counter

flops. In this report we discussed about its working, truth table, implementation
using flip-flops and learn about it.

Chapter 2.VHDL Code For 001 Sequence Detector

2.1 Introduction :

A sequence detector is a finite state machine (FSM) designed to detect a specific

sequence of bits from a continuous stream of binary inputs. Sequence detectors
can be categorized as either overlapping or non-overlapping.
Sequence detectors play a crucial role in communication systems, data integrity
verification, error detection. The design is typically implemented using state
diagrams and state transition tables to define the sequence detection logic.

1) Overlapping Sequence Detector: Detects a sequence even if bits from the

previous sequence are part of the next.
2) Non-Overlapping Sequence Detector: Resets after detecting a sequence,
waiting for a fresh input.

2.2 Working Principle of 001 Sequence Detector :

The sequence detector identifies the occurrence of "001" in a serial bitstream.

The design uses a finite state machine (FSM) with three states :

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 Implementation of Up-Counter

 Initial State (S0): The machine starts in this state, waiting for the first
bit.
 State S1 (0 detected): If the input is "0", the machine transitions to S1,
indicating that the first "0" of the target sequence has been seen.
 State S2 (00 detected): If the input is "0" while in S1, the machine
transitions to S2, indicating that "00" has been detected.
 State S3 (001 detected): If the input is "1" while in S2, the machine
transitions to S3, indicating that the complete sequence "001" has been
detected.

 Block Diagram :

001
S.D.

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 Implementation of Up-Counter

2.3 State Diagram : 0-0-1

2.4 VHDL Code :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SQ_001 is
Port ( A : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
Z : out STD_LOGIC);
end SQ_001;

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 Implementation of Up-Counter

architecture Behavioral of SQ_001 is

TYPE state_type IS ( ST0, ST1, ST2, ST3);
SIGNAL state :state_type;
begin
P0: PROCESS ( CLK)
BEGIN
IF RESET = '1' THEN
STATE <= ST0; Z <= '0';
ELSIF(CLK'EVENT AND CLK = '1' ) THEN
CASE state IS
WHEN ST0 => Z <= '0';
IF (A = '0') THEN
STATE <= ST1;

ELSE
STATE <= ST0;
END IF;
WHEN ST1 => Z <= '0';
IF (A = '0') THEN
STATE <= ST2;
ELSE
STATE <= ST0;
END IF;
WHEN ST2 => Z <= '0';
IF (A = '0') THEN
STATE <= ST2;

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 Implementation of Up-Counter

ELSE
STATE <= ST3;
END IF;
WHEN ST3 => Z <= '1';
IF (A = '0') THEN
STATE <= ST2;
ELSE
STATE <= ST0;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS P0;
end Behavioral;

2.5 Output of 001 Sequence Detector :

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 Implementation of Up-Counter

2.6 Applications :

 Error Detection and Correction: Used in data transmission to identify

specific patterns that indicate errors in digital signals.
 Digital Communication Systems: Helps in detecting preamble sequences

or synchronization signals in serial data streams.

 Cryptography and Security Systems: Plays a role in recognizing unique
sequences in encrypted communication.
 Pattern Recognition in Embedded Systems: Used for recognizing
known patterns in sensor data or input streams.

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 Implementation of Up-Counter

2.7 Conclusion :

The implementation of a 001 sequence detector using VHDL provides an

efficient
method to detect a specific bit pattern in a serial data stream. The design utilizes

a finite state machine (FSM) to track input transitions and generate the
appropriate output. This technique is commonly applied in digital
communication
systems, signal processing, and error detection mechanisms. The developed
VHDL code can be further optimized or extended for detecting more complex
patterns, demonstrating the flexibility and scalability of FSM-based digital
designs.

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