Chapter 8: Memory Management

 Background
 Swapping
 Contiguous Memory Allocation

Chapter 8: Main Memory 


Segmentation
Paging
 Structure of the Page Table
 Example: The Intel 32 and 64-bit Architectures
 Example: ARM Architecture

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Objectives Background

 To provide a detailed description of various ways of  Program must be brought (from disk) into memory and
organizing memory hardware placed within a process for it to be run
 To discuss various memory-management techniques,  Main memory and registers are only storage CPU can
including paging and segmentation access directly
 To provide a detailed description of the Intel Pentium, which  Memory unit only sees a stream of addresses + read
supports both pure segmentation and segmentation with requests, or address + data and write requests
paging
 Register access in one CPU clock (or less)
 Main memory can take many cycles, causing a stall
 Cache sits between main memory and CPU registers
 Protection of memory required to ensure correct operation

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 Base and Limit Registers Hardware Address Protection
 A pair of base and limit registers define the logical address space
 CPU must check every memory access generated in user mode to
be sure it is between base and limit for that user

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Address Binding Binding of Instructions and Data to Memory

 Programs on disk, ready to be brought into memory to execute form an  Address binding of instructions and data to memory addresses
input queue can happen at three different stages
 Without support, must be loaded into address 0000
 Compile time: If memory location known a priori, absolute
 Inconvenient to have first user process physical address always at 0000 code can be generated; must recompile code if starting
 How can it not be? location changes
 Further, addresses represented in different ways at different stages of a  Load time: Must generate relocatable code if memory
program’s life location is not known at compile time
 Source code addresses usually symbolic
 Execution time: Binding delayed until run time if the
 Compiled code addresses bind to relocatable addresses process can be moved during its execution from one memory
 i.e. “14 bytes from beginning of this module” segment to another
 Linker or loader will bind relocatable addresses to absolute addresses  Need hardware support for address maps (e.g., base and
 i.e. 74014 limit registers)
 Each binding maps one address space to another

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 Multistep Processing of a User Program Logical vs. Physical Address Space

 The concept of a logical address space that is bound to a

separate physical address space is central to proper memory
management
 Logical address – generated by the CPU; also referred to
as virtual address
 Physical address – address seen by the memory unit
 Logical and physical addresses are the same in compile-time
and load-time address-binding schemes; logical (virtual) and
physical addresses differ in execution-time address-binding
scheme
 Logical address space is the set of all logical addresses
generated by a program
 Physical address space is the set of all physical addresses
generated by a program

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Memory-Management Unit (MMU) Dynamic relocation using a relocation register

 Hardware device that at run time maps virtual to physical  Routine is not loaded until it is
address called
 Many methods possible, covered in the rest of this chapter  Better memory-space utilization;
 To start, consider simple scheme where the value in the unused routine is never loaded
relocation register is added to every address generated by a  All routines kept on disk in
user process at the time it is sent to memory relocatable load format
 Base register now called relocation register  Useful when large amounts of
 MS-DOS on Intel 80x86 used 4 relocation registers code are needed to handle
infrequently occurring cases
 The user program deals with logical addresses; it never sees the
 No special support from the
real physical addresses
operating system is required
 Execution-time binding occurs when reference is made to  Implemented through program
location in memory design
 Logical address bound to physical addresses  OS can help by providing libraries
to implement dynamic loading

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 Dynamic Linking Swapping
 Static linking – system libraries and program code combined by  A process can be swapped temporarily out of memory to a
the loader into the binary program image backing store, and then brought back into memory for continued
execution
 Dynamic linking –linking postponed until execution time  Total physical memory space of processes can exceed
 Small piece of code, stub, used to locate the appropriate physical memory
memory-resident library routine  Backing store – fast disk large enough to accommodate copies
of all memory images for all users; must provide direct access to
 Stub replaces itself with the address of the routine, and executes these memory images
the routine  Roll out, roll in – swapping variant used for priority-based
 Operating system checks if routine is in processes’ memory scheduling algorithms; lower-priority process is swapped out so
address higher-priority process can be loaded and executed
 Major part of swap time is transfer time; total transfer time is
 If not in address space, add to address space directly proportional to the amount of memory swapped
 Dynamic linking is particularly useful for libraries  System maintains a ready queue of ready-to-run processes
which have memory images on disk
 System also known as shared libraries
 Consider applicability to patching system libraries
 Versioning may be needed

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Swapping (Cont.) Schematic View of Swapping

 Does the swapped out process need to swap back in to same
physical addresses?
 Depends on address binding method
 Plus consider pending I/O to / from process memory space
 Modified versions of swapping are found on many systems (i.e.,
UNIX, Linux, and Windows)
 Swapping normally disabled
 Started if more than threshold amount of memory allocated
 Disabled again once memory demand reduced below
threshold

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 Context Switch Time including Swapping Context Switch Time and Swapping (Cont.)

 If next processes to be put on CPU is not in memory, need to  Other constraints as well on swapping
swap out a process and swap in target process
 Pending I/O – can’t swap out as I/O would occur to wrong
 Context switch time can then be very high process
 100MB process swapping to hard disk with transfer rate of  Or always transfer I/O to kernel space, then to I/O device
50MB/sec
 Known as double buffering, adds overhead
 Swap out time of 2000 ms
 Standard swapping not used in modern operating systems
 Plus swap in of same sized process
 But modified version common
 Total context switch swapping component time of 4000ms
 Swap only when free memory extremely low
(4 seconds)
 Can reduce if reduce size of memory swapped – by knowing
how much memory really being used
 System calls to inform OS of memory use via
request_memory() and release_memory()

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Swapping on Mobile Systems Contiguous Allocation

 Not typically supported  Main memory must support both OS and user processes
 Flash memory based  Limited resource, must allocate efficiently
 Small amount of space  Contiguous allocation is one early method
 Limited number of write cycles  Main memory usually into two partitions:
 Poor throughput between flash memory and CPU on mobile  Resident operating system, usually held in low memory with
platform interrupt vector
 Instead use other methods to free memory if low  User processes then held in high memory
 iOS asks apps to voluntarily relinquish allocated memory  Each process contained in single contiguous section of
 Read-only data thrown out and reloaded from flash if needed memory
 Failure to free can result in termination
 Android terminates apps if low free memory, but first writes
application state to flash for fast restart
 Both OSes support paging as discussed below

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 Contiguous Allocation (Cont.) Hardware Support for Relocation and Limit Registers

 Relocation registers used to protect user processes from each

other, and from changing operating-system code and data
 Base register contains value of smallest physical address
 Limit register contains range of logical addresses – each
logical address must be less than the limit register
 MMU maps logical address dynamically
 Can then allow actions such as kernel code being transient
and kernel changing size

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Multiple-partition allocation Dynamic Storage-Allocation Problem

 Multiple-partition allocation
How to satisfy a request of size n from a list of free holes?
 Degree of multiprogramming limited by number of partitions
 Variable-partition sizes for efficiency (sized to a given process’ needs)  First-fit: Allocate the first hole that is big enough
 Hole – block of available memory; holes of various size are scattered
throughout memory
 Best-fit: Allocate the smallest hole that is big enough; must
 When a process arrives, it is allocated memory from a hole large enough to search entire list, unless ordered by size
accommodate it
 Produces the smallest leftover hole
 Process exiting frees its partition, adjacent free partitions combined
 Operating system maintains information about:
a) allocated partitions b) free partitions (hole)  Worst-fit: Allocate the largest hole; must also search entire list
 Produces the largest leftover hole

First-fit and best-fit better than worst-fit in terms of speed and storage
utilization

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 Fragmentation Fragmentation (Cont.)
 External Fragmentation – total memory space exists to  Reduce external fragmentation by compaction
satisfy a request, but it is not contiguous
 Shuffle memory contents to place all free memory together
 Internal Fragmentation – allocated memory may be slightly in one large block
larger than requested memory; this size difference is memory
 Compaction is possible only if relocation is dynamic, and is
internal to a partition, but not being used
done at execution time
 First fit analysis reveals that given N blocks allocated, 0.5 N
 I/O problem
blocks lost to fragmentation
 Latch job in memory while it is involved in I/O
 1/3 may be unusable -> 50-percent rule
 Do I/O only into OS buffers
 Now consider that backing store has same fragmentation
problems

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Segmentation User’s View of a Program

 Memory-management scheme that supports user view of memory
 A program is a collection of segments
 A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays

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 Logical View of Segmentation Segmentation Architecture
 Logical address consists of a two tuple:
1
<segment-number, offset>,
4
1  Segment table – maps two-dimensional physical addresses; each
table entry has:
2
 base – contains the starting physical address where the
segments reside in memory
3 2  limit – specifies the length of the segment
4
 Segment-table base register (STBR) points to the segment
3 table’s location in memory

 Segment-table length register (STLR) indicates number of

segments used by a program;
user space physical memory space segment number s is legal if s < STLR

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Segmentation Architecture (Cont.) Segmentation Hardware

 Protection
 With each entry in segment table associate:
 validation bit = 0  illegal segment
 read/write/execute privileges
 Protection bits associated with segments; code sharing
occurs at segment level
 Since segments vary in length, memory allocation is a
dynamic storage-allocation problem
 A segmentation example is shown in the following diagram

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 Paging Address Translation Scheme
 Physical address space of a process can be noncontiguous;  Address generated by CPU is divided into:
process is allocated physical memory whenever the latter is  Page number (p) – used as an index into a page table which
available contains base address of each page in physical memory
 Avoids external fragmentation  Page offset (d) – combined with base address to define the
 Avoids problem of varying sized memory chunks physical memory address that is sent to the memory unit
 Divide physical memory into fixed-sized blocks called frames
page number page offset
 Size is power of 2, between 512 bytes and 16 Mbytes
p d
 Divide logical memory into blocks of same size called pages
m -n n
 Keep track of all free frames
 To run a program of size N pages, need to find N free frames and  For given logical address space 2m and page size 2n
load program
 Set up a page table to translate logical to physical addresses
 Backing store likewise split into pages
 Still have Internal fragmentation

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Paging Hardware Paging Model of Logical and Physical Memory

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 Paging Example Paging (Cont.)

 Calculating internal fragmentation

 Page size = 2,048 bytes
 Process size = 72,766 bytes
 35 pages + 1,086 bytes
 Internal fragmentation of 2,048 - 1,086 = 962 bytes
 Worst case fragmentation = 1 frame – 1 byte
 On average fragmentation = 1 / 2 frame size
 So small frame sizes desirable?
 But each page table entry takes memory to track
 Page sizes growing over time
 Solaris supports two page sizes – 8 KB and 4 MB
 Process view and physical memory now very different
n=2 and m=4 32-byte memory and 4-byte pages  By implementation process can only access its own memory

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Free Frames Implementation of Page Table

 Page table is kept in main memory
 Page-table base register (PTBR) points to the page table
 Page-table length register (PTLR) indicates size of the page
table
 In this scheme every data/instruction access requires two
memory accesses
 One for the page table and one for the data / instruction
 The two memory access problem can be solved by the use of
a special fast-lookup hardware cache called associative
memory or translation look-aside buffers (TLBs)

Before allocation After allocation

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 Implementation of Page Table (Cont.) Associative Memory
 Some TLBs store address-space identifiers (ASIDs) in each  Associative memory – parallel search
TLB entry – uniquely identifies each process to provide
address-space protection for that process Page # Frame #

 Otherwise need to flush at every context switch

 TLBs typically small (64 to 1,024 entries)
 On a TLB miss, value is loaded into the TLB for faster access
next time
 Replacement policies must be considered  Address translation (p, d)
 Some entries can be wired down for permanent fast  If p is in associative register, get frame # out
access  Otherwise get frame # from page table in memory

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Paging Hardware With TLB Effective Access Time

 Associative Lookup =  time unit
 Can be < 10% of memory access time
 Hit ratio = 
 Hit ratio – percentage of times that a page number is found in the
associative registers; ratio related to number of associative
registers
 Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
 Effective Access Time (EAT)
EAT = (1 + )  + (2 + )(1 – )
=2+–
 Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
 EAT = 0.80 x 100 + 0.20 x 200 = 120ns
 Consider more realistic hit ratio ->  = 99%,  = 20ns for TLB search,
100ns for memory access
 EAT = 0.99 x 100 + 0.01 x 200 = 101ns

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 Memory Protection Valid (v) or Invalid (i) Bit In A Page Table

 Memory protection implemented by associating protection bit

with each frame to indicate if read-only or read-write access is
allowed
 Can also add more bits to indicate page execute-only, and
so on
 Valid-invalid bit attached to each entry in the page table:
 “valid” indicates that the associated page is in the
process’ logical address space, and is thus a legal page
 “invalid” indicates that the page is not in the process’
logical address space
 Or use page-table length register (PTLR)
 Any violations result in a trap to the kernel

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Shared Pages Shared Pages Example

 Shared code
 One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems)
 Similar to multiple threads sharing the same process space
 Also useful for interprocess communication if sharing of
read-write pages is allowed
 Private code and data
 Each process keeps a separate copy of the code and data
 The pages for the private code and data can appear
anywhere in the logical address space

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 Structure of the Page Table Hierarchical Page Tables
 Memory structures for paging can get huge using straight-  Break up the logical address space into multiple page
forward methods tables
 Consider a 32-bit logical address space as on modern  A simple technique is a two-level page table
computers
 We then page the page table
 Page size of 4 KB (212)
 Page table would have 1 million entries (232 / 212)
 If each entry is 4 bytes -> 4 MB of physical address space /
memory for page table alone
 That amount of memory used to cost a lot
 Don’t want to allocate that contiguously in main memory
 Hierarchical Paging
 Hashed Page Tables
 Inverted Page Tables

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Two-Level Page-Table Scheme Two-Level Paging Example

 A logical address (on 32-bit machine with 1K page size) is divided into:
 a page number consisting of 22 bits
 a page offset consisting of 10 bits

 Since the page table is paged, the page number is further divided into:
 a 12-bit page number
 a 10-bit page offset

 Thus, a logical address is as follows:

 where p1 is an index into the outer page table, and p2 is the

displacement within the page of the inner page table
 Known as forward-mapped page table

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 Address-Translation Scheme 64-bit Logical Address Space

 Even two-level paging scheme not sufficient

 If page size is 4 KB (212)
 Then page table has 252 entries
 If two level scheme, inner page tables could be 210 4-byte entries
 Address would look like

 Outer page table has 242 entries or 244 bytes

 One solution is to add a 2nd outer page table
 But in the following example the 2nd outer page table is still 234 bytes in
size
 And possibly 4 memory access to get to one physical memory
location

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Three-level Paging Scheme Hashed Page Tables

 Common in address spaces > 32 bits
 The virtual page number is hashed into a page table
 This page table contains a chain of elements hashing to the same
location
 Each element contains (1) the virtual page number (2) the value of the
mapped page frame (3) a pointer to the next element
 Virtual page numbers are compared in this chain searching for a
match
 If a match is found, the corresponding physical frame is extracted
 Variation for 64-bit addresses is clustered page tables
 Similar to hashed but each entry refers to several pages (such as
16) rather than 1
 Especially useful for sparse address spaces (where memory
references are non-contiguous and scattered)

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 Hashed Page Table Inverted Page Table

 Rather than each process having a page table and keeping track
of all possible logical pages, track all physical pages
 One entry for each real page of memory
 Entry consists of the virtual address of the page stored in that
real memory location, with information about the process that
owns that page
 Decreases memory needed to store each page table, but
increases time needed to search the table when a page
reference occurs
 Use hash table to limit the search to one — or at most a few —
page-table entries
 TLB can accelerate access
 But how to implement shared memory?
 One mapping of a virtual address to the shared physical
address

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Inverted Page Table Architecture Oracle SPARC Solaris

 Consider modern, 64-bit operating system example with tightly
integrated HW
 Goals are efficiency, low overhead
 Based on hashing, but more complex
 Two hash tables
 One kernel and one for all user processes
 Each maps memory addresses from virtual to physical memory
 Each entry represents a contiguous area of mapped virtual
memory,
 More efficient than having a separate hash-table entry for
each page
 Each entry has base address and span (indicating the number
of pages the entry represents)

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 Oracle SPARC Solaris (Cont.) Example: The Intel 32 and 64-bit Architectures

 TLB holds translation table entries (TTEs) for fast hardware lookups
 Dominant industry chips
 A cache of TTEs reside in a translation storage buffer (TSB)
 Includes an entry per recently accessed page
 Pentium CPUs are 32-bit and called IA-32 architecture
 Virtual address reference causes TLB search
 If miss, hardware walks the in-memory TSB looking for the TTE
 Current Intel CPUs are 64-bit and called IA-64 architecture
corresponding to the address
 If match found, the CPU copies the TSB entry into the TLB
and translation completes  Many variations in the chips, cover the main ideas here
 If no match found, kernel interrupted to search the hash table
– The kernel then creates a TTE from the appropriate hash
table and stores it in the TSB, Interrupt handler returns
control to the MMU, which completes the address
translation.

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Example: The Intel IA-32 Architecture Example: The Intel IA-32 Architecture (Cont.)

 Supports both segmentation and segmentation with paging  CPU generates logical address
 Each segment can be 4 GB  Selector given to segmentation unit
 Up to 16 K segments per process  Which produces linear addresses
 Divided into two partitions
 First partition of up to 8 K segments are private to
process (kept in local descriptor table (LDT))  Linear address given to paging unit
 Second partition of up to 8K segments shared among all  Which generates physical address in main memory
processes (kept in global descriptor table (GDT))
 Paging units form equivalent of MMU
 Pages sizes can be 4 KB or 4 MB

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 Logical to Physical Address Translation in IA-32 Intel IA-32 Segmentation

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Intel IA-32 Paging Architecture Intel IA-32 Page Address Extensions

 32-bit address limits led Intel to create page address extension (PAE),
allowing 32-bit apps access to more than 4GB of memory space
 Paging went to a 3-level scheme
 Top two bits refer to a page directory pointer table
 Page-directory and page-table entries moved to 64-bits in size
 Net effect is increasing address space to 36 bits – 64GB of physical
memory

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 Intel x86-64 Example: ARM Architecture
 Current generation Intel x86 architecture  Dominant mobile platform chip
(Apple iOS and Google Android
 64 bits is ginormous (> 16 exabytes) devices for example)
32 bits

outer page inner page offset

 In practice only implement 48 bit addressing  Modern, energy efficient, 32-bit
CPU
 Page sizes of 4 KB, 2 MB, 1 GB  4 KB and 16 KB pages
4-KB
 Four levels of paging hierarchy  1 MB and 16 MB pages (termed or
16-KB
sections)
 Can also use PAE so virtual addresses are 48 bits and physical page

 One-level paging for sections, two-

addresses are 52 bits level for smaller pages
 Two levels of TLBs 1-MB
or
 Outer level has two micro 16-MB
section
TLBs (one data, one
instruction)
 Inner is single main TLB
 First inner is checked, on
miss outers are checked,
and on miss page table
walk performed by CPU

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End of Chapter 8

Operating System Concepts – 9th Edition Silberschatz, Galvin and Gagne ©2013