0% found this document useful (0 votes)
12 views

Mini Projects Topics

The document outlines the curriculum for the Computer Architecture and Design course at G H Patel College of Engineering & Technology for the academic year 2024-25. It includes course objectives focusing on digital computers, instruction sets, processing units, memory interfacing, and GPU architecture, along with assignment projects that utilize various software tools. Additionally, it provides an evaluation table based on Bloom's Taxonomy levels to assess student performance.

Uploaded by

zojeridy
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
12 views

Mini Projects Topics

The document outlines the curriculum for the Computer Architecture and Design course at G H Patel College of Engineering & Technology for the academic year 2024-25. It includes course objectives focusing on digital computers, instruction sets, processing units, memory interfacing, and GPU architecture, along with assignment projects that utilize various software tools. Additionally, it provides an evaluation table based on Bloom's Taxonomy levels to assess student performance.

Uploaded by

zojeridy
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

G H Patel College of Engineering & Technology

&
A.D Patel Institute of Technology
Department of Computer Engineering
Branch: Computer Science and Design
AY: 2024-25(odd)
Subject Code: 102044507
Computer Architecture and Design
CO1 Demonstrate and understand the basic principles and operations of digital computers
CO2 Understand and classify the instruction set and distinguish the use of different instructions and apply it in assembly
language programming.
CO3 Design processing unit using the concepts of ALU and control logic design and understand the architecture and
functionality of central processing unit
CO4 Design circuits for interfacing memory and I/O with processors.
`CO5 To understand the design and architecture of GPU for general-purpose computing and parallel performance
Assignment questions

1 Design and Simulate a Simple Processor CO1 BL3

● Software: Verilog/VHDL (hardware description languages), ModelSim/Quartus


Prime (simulation tools)
● Project: Design a basic processor architecture (e.g., Harvard, Von Neumann)
using HDL, implement instruction fetch-decode-execute cycle, arithmetic
operations, and control logic, and simulate its behavior.

2 Implement a Simple Compiler CO2 BL5


● Software: C/C++, Flex/Bison (lexical analyzer/parser generators)
● Project: Develop a compiler for a simple programming language, including
lexical analysis, parsing, and code generation.

3 GPU-Accelerated Application CO5 BL3


● Software: CUDA Toolkit (for NVIDIA GPUs), OpenCL (cross-platform API),
Python/C++ (programming languages)
● Project: Implement a computationally intensive task (e.g., image processing,
matrix multiplication, machine learning) using GPU acceleration and compare its
performance with CPU-only implementation.

4 Cache Memory Simulation CO4 BL4


● Software: C/C++, Python, MATLAB
● Project: Simulate different cache replacement policies (e.g., LRU, FIFO, random)
and evaluate their performance. Explore the impact of cache size, associativity,
and block size.

5 . Virtual Memory Simulation CO4 BL4


● Software: C/C++, Python, MATLAB
● Project: Simulate page replacement algorithms (e.g., FIFO, LRU, optimal) and
analyze their performance. Study the impact of page size, frame size, and
reference string.

6 DMA Controller Simulation CO4 BL3


● Software: Verilog/VHDL, ModelSim/Quartus Prime
● Project: Design and simulate a DMA controller, including request generation,
address generation, data transfer, and completion signaling. Evaluate its
performance compared to programmed I/O.
7 RISC Processor Design and Simulation CO4 BL4
● Software: Verilog/VHDL, ModelSim/Quartus Prime
● Project: Design a RISC processor architecture with a reduced instruction set and
pipelining. Implement the instruction set and pipeline stages. Compare its
performance with a CISC processor.

R: Remembering; U: Understanding; A: Application, N: Analyze; E: Evaluate; C: Create

Weightage to Bloom’s Taxonomy Levels (BL1- Remembering -1, BL2-Understanding- 2, BL3-Application-3, BL4- Analysing-4, BL5-
Evaluating, BL6- Creating

Evaluation Table

Bloom’s Level Detail Weightage Sum of Marks Weighted


Taxonomy with same BL Marks
Levels

BL1 Remembering 1 00 00*1=00


BL2 Understanding 2 00 00*2=00
BL3 Applying 3 30 30*3=90
BL4 Analyzing 4 30 30*4=140
BL5 Evaluate 5 10 10*5=50

Calculation:

Overall Blooms Taxonomy Level = (∑ (Weightage * Marks))/ Total Marks

= (1 x00 + 2x00+ 3x30 + 4x30 + 5x10) / 10


=( 00+ 00 + 90 + 140 + 50 ) / 5

= 280 /5

= 56

You might also like