Enrolment No: ________________________

G H Patel College of Engineering & Technology

Faculty of Engineering & Technology,
The Charutar Vidya Mandal (CVM) University
Internal Theory Examination
Subject Code: 202045610 Total Marks: 20 Subject Name: Micro. Tech.
Academic Year: 2024 – 25 Semester: 6 (Even)
Date: 28/10/2025
Time: 9:15 am to 10:15 am
Note: Figures to the right indicates full marks
Q:1 Answer the following short questions: [06]

1) What is the function of the ALE (Address Latch Enable) signal?

To demultiplex address bus and data bus
2) What is stack? What is the role of the Stack Pointer (SP)?
Stack is an area in memory where data is temporarily stored in LIFO
fashion. ½ mark
Stack pointer is a 16 bit special purpose register of 8085 which points
to the top of stack ½ mark
3) Explain the concept of memory mapped I/O in 8085.
When I/O Address is of 16 bit then it is called as memory mapped I/O .
no. of I/O devices can be more than 255 and ½ mark
LDA and STA instruction are used to access I/O ½ mark
4) Explain the function of ANA, ORA, and XRA instructions.
ANA is used for clearing specific bits or checking bits,
The mask helps to isolate the bits to manipulate.
ORA is used for setting specific bits in a register or memory location,
The mask enables to modify only certain bits without altering others.
XRA is Used for Bit Masking in two ways:
Toggling Specific Bits: If you want to invert certain bits of a register
(i.e., change 1 to 0 and 0 to 1), you can use the XRA instruction with a
mask that has 1 in the positions you want to flip.
Preserving Other Bits: The XOR operation ensures that only the bits
corresponding to 1 in the mask are flipped, while the other bits remain
unchanged. 1 mark

5) Explain the function of the IN and OUT instructions

The IN instruction works with I/O ports that are typically connected to
peripheral devices (such as keyboards, sensors, or ADCs).
The data read from the port is transferred into the Accumulator, and
the microprocessor can then process or manipulate this data.
IN 0x05 ; Data from port 0x05 is read into A, A = 0x25
½ mark
The OUT instruction transfers the contents of the Accumulator to an
output port.

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The data from the Accumulator can be sent to peripheral devices like
LEDs, motors, or any other output-controlled devices connected to the
I/O ports.

MVI A, 0x37 ; Load Accumulator A with 0x37

OUT 0x03 ; Send data 0x37 to port 0x03
½ mark
6) Explain the use of ROTATE instructions (RLC, RRC).
RLC and RRC can be used in certain algorithms, such as multiplication
or division by powers of 2, where bit shifting is a core part of the
operation. Rotating bits is an efficient way to manipulate binary
numbers, especially when dealing with binary multiplication and
division. ½ mark
RLC and RRC are particularly useful for bit manipulation operations
where you need to shift bits around while retaining the original pattern.
These instructions provide a simple way to rotate data within the
Accumulator without losing any bits. ½ mark

Q:2 Write an 8085 ALP to count the no. of byte that are greater than 2510 and lesser [04]
than 6510 from an array of twenty bytes stored on memory location 2000h
onwards, store such no. on memory location 2100H onwards.
LXI H, 2000H
LXI D,2100H
MVI C, 14H (20 DECIMAL)
MVI B, 00H
X12: MOV A,M
CPI 19H (25 DECIMAL)
JC X11
CPI 41H (65 DECIMAL)
JNC X11
INR B
STAX D
INX D
X11: INX H
DCR C
JNZ X12
HLT
OR
Following program displays 1-9 on an output port at a certain delay. Answer
the below questions

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2000 LXI SP,2100H DELAY: 2064 PUSH H

2003 LXI B,0000H 2065 PUSH B
2006 PUSH B 2066 LXI B,80FFH
2007 POP PSW LOOP: 2069 DCX B
2008 LXI H,0009H 206A MOV A,B
200B CALL 2064H 206B ORA C
200E INR A 206C JNZ LOOP
200F OUT 01H 206F POP B
2010 DCR L 2070 RET
2010 HLT

a. What is the status of the flags and the contents of the accumulator after
the execution of the POP instruction located at 2007H?
Accumulator: 00H and Flag register: 00H ½ MARKS
b. Specify the stack locations and their contents after the execution of the
CALL instruction (not the Call subroutine).
STACK LOCATION: 20FEH & CONTENT OF 20FE: 0EH ½ MARKS
c. What are the contents of the stack pointer register and the program
counter after the execution of the CALL instruction?
SP:20FE & PC:2064 ½ MARKS
d. Specify the memory location where the program returns after the
subroutine
Program Returns To 200E Memory location ½ MARKS
e. What changes are needed so that the program functions correctly.
(display 1-9 on output port)
ADD instruction POP PSW before RETURN.
Change PUSH H instruction to PUSH PSW in the delay subroutine
Add JNZ 200B instruction before HLT in main program 2 MARKS

Q:3 Design an 8085-microprocessor system such that it should contain 16KByte of [04]
EPROM and 4KByte of RAM with starting addresses 0000H and 4000H
respectively. Use two 8KByte of EPROMs (2764) and two 2KByte of RAMs
(6116) for this system. Use 3 input and 5 input NAND gates for chip select logic.

Memory Requirements:
- 16KB EPROM starting at address 0000H:- Two 8KB EPROMs (2764)
- 4KB RAM starting at address 4000H: Two 2KB RAMs (6116)
Memory Map:
0000H-1FFFH: EPROM1 (8KB)
2000H-3FFFH: EPROM2 (8KB)
4000H-47FFH: RAM1 (2KB)
4800H-4FFFH: RAM2 (2KB)

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Address Decoding Analysis:

--------------------------------------------------------------------------------
Component | Address Range | A15 A14 A13 A12 | A11 A10 A9-A0 | Size
--------------------------------------------------------------------------------
EPROM1 | 0000H - 1FFFH | 0 0 0 x | x x x | 8KB (2^13 bytes)
EPROM2 | 2000H - 3FFFH | 0 0 1 x | x x x | 8KB (2^13 bytes)
RAM1 | 4000H - 47FFH | 0 1 0 0 | 0 x x | 2KB (2^11 bytes)
RAM2 | 4800H - 4FFFH | 0 1 0 0 | 1 x x | 2KB (2^11 bytes)
2 Marks
NAND Gate Implementation:
Since we need active LOW chip selects and the problem requires NAND gates,
we'll use:
- 3-input NAND gates for EPROMs
- 5-input NAND gates for RAMs

Chip Select Logic Implementation:

3-input NAND gates for chip select logic

For EPROM1 (0000H-1FFFH):

CS(EPROM1) = NAND(A15̅, A14̅, A13̅) All pins Active LOW

For EPROM2 (2000H-3FFFH):

CS(EPROM2) = NAND(A15̅, A14̅, A13) All Active LOW except A13

5-input NAND gates for chip select logic

For RAM1 (4000H-47FFH):
CS(RAM1) = NAND(A15̅, A14, A13̅, A12̅, A11̅) All Active LOW except A14

For RAM2 (4800H-4FFFH):

CS(RAM2) = NAND(A15̅, A14, A13̅, A12̅, A11) All Active LOW except A14 and
A11

2 Marks

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Circuit Connections:
1. Connect 8085's address bus (A0-A15) to appropriate pins of memory chips
2. Connect 8085's data bus (D0-D7) to all memory chips
3. Connect control signals (RD, WR) to appropriate memory chip pins
4. Implement the chip select logic using NAND gates as specified above
5. Connect the outputs of NAND gates to respective CS pins of memory chips

Q:4 Attempt the following (any two) [06]

1) Write a program to add the two Hex numbers 7A and 46 and to store the
sum at memory location XX98H and the flag status at location XX97H.
LXI SP,2100H
MVI A, 7AH
ADI 46H
PUSH PSW
POP H
STA XX98H 1.5 MARKS
MOV A, L
STA XX97H 1.5 MARKS
HLT

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2) Identify the bytes from the following set that will be displayed at memory
location 2000H, assuming one byte is loaded into accumulator at a time.
Data(H): 43, 25, 7B, 78, F2, D7

MVI A, Data
MVI B,44H
MVI C, B8H
CMP C
JC Loop
STA 2000H
HLT
Loop: SUB A
STA 2000H
HLT

Ans. 0,0,0,0, F2, D7 3 Marks

2) Draw 8085 timing diagram for execution of the instruction MVI A,32H

1 mark for correct ALE & RD

1 MARKS FOR CORRECT Data Bus
1 mark for correct no. of T-states and Add bus

4) Calculate the delay in the following loop, assuming the system clock
period is 0.33 µS.
LXI B,12FFh

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Delay: DCX B 6T
MOV A,C 4T
ORA B 4T
JNZ Delay 10T/7T

Delay= (count × T State × no. of t-state in loop)

= (4863 × 0.33 µS × 24 ) = 38.515 ms

1.5 mark for correct T-state calculations

1 mark for correct Loop Count
½ mark for correct final answer

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