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DEPARTMENT OF AVIONICS ENGINEERING

SUBJECT : FPGA BASED EMBEDDED SYSTEM

DESIGN
SUBJECT CODE : 408448
LAB NO : 03

TITLE : Testbench to Verify the Functionality of

a Design (Full Adder and Subtractor)

SUBMITTED TO : Engr. Lal Said Khan

SEMESTER :
SECTION :

Marks Obtain
Group Member 1 Group Member 2
NAME Burhan Akram
REGISTRATION NUMBER 220701050
LAB REPORT
PERFORMANCE
TOTAL MARKS

DEADLINE FOR SUBMISSION:

DATE OF SUBMISSION:

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Figure 1: Schematic diagram of a Full Subtractor

Full subt Truth Table:

The Verilog full subtractor module performs binary subtraction of three input bits (A, B,
and BORROW_IN) and produces a difference (DIFF) and a borrow output (BORROW_OUT).
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The DIFF is computed using XOR operations: DIFF = (A ^ B) ^ BORROW_IN, ensuring the correct
result for all input combinations. The BORROW_OUT is determined using the formula (~A & B) |
(~A & BORROW_IN) | (B & BORROW_IN), which accounts for all cases where a borrow is
required—when A is 0 and B is 1, when A is 0 and BORROW_IN is 1, or
when B and BORROW_IN are both 1. The module is purely combinational, using continuous
assignments (assign) for logic operations without requiring clock signals, and the timescale 10ns
/ 100ps directive specifies the simulation time unit and precision for accurate timing analysis.

Algorithm 1: Verilog design code full subtractor

`timescale 10ns / 100ps

module full_subtractor
(
input A, // Input bit A
input B, // Input bit B
input BORROW_IN, // Borrow input
output DIFF, // Difference output
output BORROW_OUT // Borrow output
);

// DIFF is calculated using XOR operations

assign DIFF = (A ^ B) ^ BORROW_IN;

// BORROW_OUT is calculated based on the logic of a full subtractor

assign BORROW_OUT = (~A & B) | (~A & BORROW_IN) | (B & BORROW_IN);

endmodule

The Verilog testbench (full_subtractor_tb) verifies the functionality of the full subtractor module by
applying all eight possible input combinations (A, B, BORROW_IN) and checking the outputs
(DIFF and BORROW_OUT). It defines the inputs as reg and the outputs as wire, then instantiates the
full subtractor module as uut. Using an initial block, the testbench iterates through all input cases
with a 10ns delay (#10) between each change, while $display prints the results in a structured format
for easy verification. The test concludes with $finish, ensuring proper termination of the simulation.
Below is the testbench code:

Algorithm 2: Verilog testbench for Full subtractor

`timescale 10ns / 100ps

module full_subtractor_tb;

// Declare inputs as reg and outputs as wire

reg A, B, BORROW_IN;
wire DIFF, BORROW_OUT;

// Instantiate the full subtractor module

full_subtractor uut (
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.A(A),
.B(B),
.BORROW_IN(BORROW_IN),
.DIFF(DIFF),
.BORROW_OUT(BORROW_OUT)
);

// Test procedure
initial begin
$display("A B BIN | DIFF BOUT");
$display("-----------------");

// Apply all possible input combinations

A = 0; B = 0; BORROW_IN = 0; #10;
$display("%b %b %b | %b %b", A, B, BORROW_IN, DIFF, BORROW_OUT);

A = 0; B = 0; BORROW_IN = 1; #10;
$display("%b %b %b | %b %b", A, B, BORROW_IN, DIFF, BORROW_OUT);

A = 0; B = 1; BORROW_IN = 0; #10;
$display("%b %b %b | %b %b", A, B, BORROW_IN, DIFF, BORROW_OUT);

A = 0; B = 1; BORROW_IN = 1; #10;
$display("%b %b %b | %b %b", A, B, BORROW_IN, DIFF, BORROW_OUT);

A = 1; B = 0; BORROW_IN = 0; #10;
$display("%b %b %b | %b %b", A, B, BORROW_IN, DIFF, BORROW_OUT);

A = 1; B = 0; BORROW_IN = 1; #10;
$display("%b %b %b | %b %b", A, B, BORROW_IN, DIFF, BORROW_OUT);

A = 1; B = 1; BORROW_IN = 0; #10;
$display("%b %b %b | %b %b", A, B, BORROW_IN, DIFF, BORROW_OUT);

A = 1; B = 1; BORROW_IN = 1; #10;
$display("%b %b %b | %b %b", A, B, BORROW_IN, DIFF, BORROW_OUT);

$finish; // Terminate simulation

end

endmodule

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Conclusion:

During the exercises, We built a systematic test environment to thoroughly verify the functionality
of the Full Adder and Full Subtractor modules. By applying all possible input combinations and
analyzing the outputs, they gained hands-on experience in verifying digital circuits. This process not
only reinforced their understanding of combinational logic design but also highlighted the
importance of structured testing in ensuring the correctness of hardware implementations. Through
these exercises, students developed essential skills in debugging, simulation, and interpreting
results, which are critical for designing and validating more complex digital systems in the future.

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