Scribd
Upload
13 views3 pages

Sample PD Resume1

The document is a resume detailing the candidate's career objective, professional experience, technical skills, academic qualifications, certifications, awards, extracurricular activities, and project work. The candidate has completed a Physical Design Course and has practical experience with IC Compiler tools, along with a B.Tech in Electronics and Communication Engineering. Additionally, the resume highlights the candidate's achievements and personal profile information.

Uploaded by

hitheshv1999
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
13 views3 pages

Sample PD Resume1

The document is a resume detailing the candidate's career objective, professional experience, technical skills, academic qualifications, certifications, awards, extracurricular activities, and project work. The candidate has completed a Physical Design Course and has practical experience with IC Compiler tools, along with a B.Tech in Electronics and Communication Engineering. Additionally, the resume highlights the candidate's achievements and personal profile information.

Uploaded by

hitheshv1999
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 3

Name

Email [email protected]
Contact No: +91-Mobile Number

CAREER OBJECTIVE:
To be a part of organization that gives a scope to enhance my knowledge and utilizing my skills
towards the growth of organization.

PROFESSIONAL EXPERIENCE:
 Completed Physical Design Course from May 2023 to October 2023 in Takshila Institute of
VLSI technologies.
 Good Understanding of block level Physical design and verification concepts like Floor
planning, CTS, STA, DRC/LVS, DFM etc.
 Practical exposure to Physical Design tools from IC Compiler tools.

TECHNICAL SKILLS:
 Strong understanding in the RTL to GDSII flow or design implementation.
 Good in concepts related to synthesis, place and route, CTS .
 Good knowledge and experience in Block-level Floor-planning and Physical verification.
 Working experience with tools like ICC.
 Strong knowledge in standard place and route flows ICC/Synopsys flows preferred.
 Well versed with timing constraints and STA.
 Good knowledge of Windows 7, 8 and Linux.

ACADEMIC QUALIFICATION:

Year of Percentage/
Qualification Name of Institution
Passing CGPA
B.Tech (ECE) NIST Berhampur, Orissa 2017 8.89

XII J. N. V. Gandey Giridih, Jharkhand 2012 91.6%


X J. N. V. Gandey Giridih, Jharkhand 2010 9.6

CERTIFICATIONS:
 National Institute of Science and Technology, Berhampur.
Title: Certification course on Automation tools of VLSI EDA and ASIC on June 2015.
 Takshila Institute of VLSI Technologies
Title: Professional Training on Physical Design.
AWARDS & ACHIEVEMENTS:
 Topper of my 2012 school batch in 12th board.
 Got an IASc-INSA-NASI Summer research fellowship in June 2016.
 Qualified Gate in 2019.

EXTRA-CURRICULAR ACTIVITIES:
 Student Guide under “N.I.S.T. Student Counseling Service”.
 Executive core member of “N.I.S.T. Robotics Club”.
 Participated in Roborace, in the event of Sankalp 2014 at NIST, Berhampur.
 Participated in Robowar, in the event of Sankalp 2015 at NIST, Berhampur.
 Participated in ASME SDE in the event of Kshitij 2016 at IIT Kharagpur.
 Participated in Open Hardware in the event of Technex’16 at IIT (BHU), Varanasi.
 Participated in Robocon in 2017 at MIT Pune.

PROJECT WORKED ON:


Title ORCA_TOP

Tool used IC Compiler


Description
 Technology: 32nm
 No. of macros: 40
 Layer: 9
 Std. cell count: 56013
 No. of Clocks: 7
 Frequency: 416MHz

Responsibilities Iterative Floorplan, IO ports placement, Powerplanning, Placement and


CTS reviews, Routing and DRC checks.

Title ORCA_TOP_IO

Tool used IC Compiler


Description
 Technology: 28nm
 No. of macros: 30
 Layer: 9
 Std. cell count: 50000
 No. of Clocks: 7
 Frequency: 400MHz

Responsibilities Iterative Floorplanning and Power-planning


Placement and CTS optimization
Physical Verification and manual optimization
Timing Closure and ECO
ACADEMIC PROJECT:

Hardware design and implementation of low cost low frequency PC based oscilloscope. This
project aims to develop a low frequency (250 KHZ maximum) PC based oscilloscope.

PERSONAL PROFILE:
Date of Birth : 09th August 1995
Languages Known : English, Hindi.
Permanent Address : Amrita Sinha
D/o Ashok Kumar Sinha
Mama House, Burning ghat road, Barmashia
Giridih, Jharkhand-815301

Date:
Place:

You might also like