Digital Logic Design

EEE241
LAB REPORT

LAB #02: Boolean Function

Implementation using
Universal Gates
Objectives
 This lab is designed to simulate and implement any logic function using universals
gates (NAND/NOR).
 To build the understanding of how to construct any combinational logic function
using NAND or NOR gates only.

Pre-Lab:
Background theory:

Digital circuits are more frequently constructed with universal gates. NAND and NOR gate
are called universal gates. Any Boolean logic function can be implemented using NAND only
or NOR only gates. NAND and NOR gates are easier to fabricate with electronic components
than basic gates. Because of the prominence of universal gates in the design of digital
circuits, rules and procedures have been developed for conversion from Boolean function
given in terms of AND, OR, and NOT into its equivalent NAND and NOR logic diagram.

Read and understand the universal gates. List the truth tables of AND, OR, NOT, NAND,
NOR and XOR gates. Identify the NAND and NOR ICs and their specification for CMOS
and TTL families.

In lab:
This lab has two parts. In the first part, simulation and implementation of any logic
expression by using only NAND gates are done. In the second part, the same procedure is
done by using NOR gates only.

Part 1 - Implementing any logic expression by using only NAND gates:

If we can show that the logical operations AND, OR, and NOT can be implemented with
NAND gates, then it can be safely assumed that any Boolean function can be implemented
with NAND gates.

Procedure
 Simulate NOT, AND, OR , XOR and XNOR gates in Proteus software, by using
only NAND gates. Verify their truth tables.
 Insert the IC on the trainer’s breadboard.
 Use any one or more of the NAND gates of the IC for this experiment.
 One or more Logic Switches of the trainer (S1 to S9) can be used for input to the
NAND gate.
 For output indication, connect the output pin of the circuit to any one of the LEDs of
the trainer (L0 to L15).

In-Lab Tasks-Part-1
In-Lab Task 1.1: Verification of NOT function:

 Connect the circuit as shown in Figure 2.1.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of a NOT gate. Record your observations in the Table2.1 below.

A F=A’

Figure 2.1: NOT gate using NAND gate

Table 2.1: Observation Table for NOT gate

 INPUT OUTPUT

𝑨 𝑭

In-Lab Task 1.2: Verification of AND function

 Connect the circuit as shown in Figure 2.2.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an AND gate. Record your observations in Table 2.2 below.

A
(AB)’ F=AB
B

Figure 2.2: AND gate using NAND gates

Table 2.2: Observation Table for AND gate

INPUTS OUTPUT

𝑨 � 𝑭
�
0 0

0 1

1 0

1 1

In-Lab Task 1.3: Verification of OR function

 Connect the circuit as shown in Figure 2.3.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an OR gate. Record your observations in Table 2.3 below.

A A’
 F=A+B

Figure 2.3: OR gate using NAND gates

Table 2.3: Observation Table for OR gate

INPUTS OUTPUT

𝑨 � 𝑭
�
0 0

0 1

1 0

1 1

In-Lab Task 1.4: Verification of XOR function

 Connect the circuit as shown in Figure 2.4.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an XOR gate. Record your observations in Table 2.4 below.

A (A(AB)’)’

F=A’B+AB’
(AB)’

(B(AB)’)
 Figure 2.4: XOR gate using NAND gates

Table 2.4: Observation Table for XOR gate

INPUTS OUTPUT

𝑨 � 𝑭
�
0 0

0 1

1 0

1 1

In-Lab Task 1.5: Verification of XNOR function

 Connect the circuit as shown in Figure 2.5.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an XNOR gate. Record your observations in Table 2.5 below.
A (A(AB)’)’

F=AB+A’B’
(AB)’

B
(B(AB)’)’
 Figure 2.5: XNOR gate
using NAND gates Table
2.5: Observation Table for
XNOR gate

INPUTS OUTPUT

𝑨 � 𝑭
�
0 0

0 1

1 0

1 1

In-Lab Task 1.6: Implementation of any Boolean function

(2-variables) using only NAND gates

𝐹(𝐴, 𝐵) =

(Note: Boolean function will be specified

by Lab Instructor) Table 2.6: Observation Table for the
given Boolean function

Inputs Outputs

𝑨 �
𝑭𝑪 𝑭𝑶
Calculated Observed
�
0 0

0 1

1 0

1 1
Part 2 - Implementing any logic expression by using only NOR gates
If we can show that the logical operations AND, OR, and NOT can be
implemented with NOR gates, then it can be safely assumed that any
Boolean function can be implemented with NOR gates.
Procedure

 Simulate NOT, AND and OR gates in Proteus software, by using

only NOR gates. Verify their truth tables.
 Insert the IC on the trainer’s breadboard.
 Use any one or more of the NOR gates of the IC for this experiment.
 One or more Logic Switches of the trainer (S1 to S9) can be used
for input to the NOR gate.
 For output indication, connect the output pin of the circuit to any
one of the LEDs of the trainer (L0 to L15).
 In-Lab Tasks-Part-2
In-Lab Task 2.1: Verification of NOT function

 Connect the circuit as shown in Figure 2.6.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the
circuit conforms to that of an NOT gate. Record your observations in
Table 2.7 below.

Figure 2.6: NOT gate using NOR gate

Table 2.7: Observation Table for NOT gate

INPUT OUTPUT

𝑨 𝑭

In-Lab Task 2.2: Verification of AND function

  Connect the circuit as shown in Figure 2.7.
 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the
circuit conforms to that of an AND gate. Record your observations in
Table 2.8 below.

Figure 2.7: AND gate

using NOR gates Table
2.8: Observation Table for
AND gate

INPUTS OUTPUT

𝑨 � 𝑭
�
0 0

0 1

1 0

1 1

In-Lab Task 2.3: Verification of OR function

 Connect the circuit as shown in Figure 2.8.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the
circuit conforms to that of an OR gate. Record your observations in
Table 2.9 below.
 Figure 2.8: OR gate using NOR
gates
Table 2.9: Observation Table for
OR gate

INPUTS OUTPUT

𝑨 � 𝑭
�
0 0

0 1

1 0

1 1

Post-Lab:
Task 01: Simulate NAND, XOR and XNOR gates in Proteus software, by
using only NOR gates. Verify their truth tables.
 Critical Analysis/Conclusion
Lab Assessment

Pre-Lab /1

In-Lab /5
Data
/4
Analysis

Post-Lab
Data
Presentation
/4
/4
/10
Writing
/4
Style

Instructor Signature and Comments

NAND:
INPUTS OUTPUT

𝑨 𝑩 𝑭
0 0
0 1

1 0
1 1
XOR:
INPUTS OUTPUT
𝑨 � 𝑭
�
0 0
0 1
1 0
1 1

XNOR:
INPUTS OUTPUT

𝑨 � 𝑭
�
0 0

0 1

1 0

1 1