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Lab 3

The lab report focuses on introducing Verilog and Xilinx ISE for modeling and simulating digital systems. Students are tasked with writing Verilog code for various logic gates and a specified Boolean function, along with creating test benches to verify their simulations. The report also includes a critical analysis section and a grading rubric for assessment.

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9 views9 pages

Lab 3

The lab report focuses on introducing Verilog and Xilinx ISE for modeling and simulating digital systems. Students are tasked with writing Verilog code for various logic gates and a specified Boolean function, along with creating test benches to verify their simulations. The report also includes a critical analysis section and a grading rubric for assessment.

Uploaded by

aznia shireen
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Digital Logic

Design
EEE241
LAB REPORT

LAB #03: Introduction to


Verilog and
Simulation using XILINX ISE
Objective
Part 1
In this lab, Verilog (Hardware Description Language) is introduced with
Xilinx ISE. Verilog is used to model digital systems. It is most commonly
used in the design and verification of digital circuits.
Part 2
Xilinx ISE is a verification and simulation tool for Verilog, VHDL, System
Verilog, and mixed-language designs.

In-Lab Task 2:
Verify all the basic logic gates using the Xilinx ISE simulation tool and verify your
waveform with logic gates truth table.
Task 01: Write a Verilog code (Gate-Level) for NOT, OR, NOR,
NAND, XOR and XNOR.
Task 02: Write a stimulus/test bench for Task 01 and show the simulation
results.
Post-Lab:
Task 01: Write a Verilog code for the given Boolean function* (e.g. 𝐹 = 𝑥 +
𝑥̅𝑦 + 𝑦𝑧̅ ):

a) Using Gate-Level model (Provide Gate Level diagram and Truth Table)

x|y|z|F

0|0|0|0

0|0|1|1

0|1|0|1

0|1|1|1
1|0|0|1

1|0|1|1

1|1|0|1

1|1|1|1
b) Using Dataflow model

Task 02: Write a stimulus/test bench for Task 01 and show the simulation results.
* (Note: Every student should opt different Boolean function)

Critical Analysis/Conclusion
Lab Assessment

Pre-Lab /1

In-Lab /5

Data
Analysis
/4 /10
Data
Post-Lab /4 /4
Presentation

Writing
/4
Style

Instructor Signature and Comments

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