Embedded Systems

Prof. Dr. Faruk Bağcı

Prof. Dr. Mesut Güneş

Prof. Dr. Faruk Bağcı

 CHAPTER OVERVIEW
• Introduction to Embedded Systems
• Embedded & Real-time Operating Systems
• Linux Kernel
• Peripheral Access
• Threads & Processes
• Memory
• Inter-process Communication
• Real-time Scheduling
• Interrupt Handling
• Advanced Topics

Prof. Dr. Faruk Bağcı

BUILT-IN PERIPHERALS

• The interrupt controller

• System time
• Generic timers
• General-purpose I/O
• The watchdog
• Local Bus Interfaces
THE INTERRUPT CONTROLLER

• Assigning different priorities to interrupt lines guarantees a lower

interrupt latency for higher-priority interrupt sources
• makes the system react faster to prioritized events
• Interrupts may, however, occur at any time while the system is
running
• including during the execution of another interrupt service routine.
• In this case, the interrupt controller provides a way to chain the
interrupt handlers
• the order of execution depends on the priority levels assigned to the interrupt
source.
NVIC TAIL-CHAINING MECHANISM
• If one or more interrupts occur while another service routine is
executing,
• pull operation normally occurring at the end of the interrupt to restore the
context from the stack will be canceled
• Controller will instead fetch the location of the second handler in the
interrupt vector and ensure it is executed immediately after the first
• NVIC allows us to change parameters while the system is running,
• It is able to reshuffle the order of execution of the interrupt service routines
associated to the pending signals, according to the priority levels
• Same interrupt is not allowed to run twice in the same chain of
handlers
• May be caused by altering the priorities in the other handlers
• This is intrinsically enforced by the NVIC logic
• ensures that no loops are possible in the chain
 PERIPHERALS INTERRUPT CONFIGURATION
• Each interrupt line can be enabled and disabled through the NVIC Interrupt
Set/Clear Enable registers
• NVIC_ISER, NVIC_ICER located at address 0xE000E100 and 0xE000E180
#define NVIC_ISER_BASE (0xE000E100)
static inline void nvic_irq_enable(uint8_t n)
{
int i = n / 32;
volatile uint32_t *nvic_iser =
((volatile uint32_t *)(NVIC_ISER_BASE + 4 * i));
*nvic_iser |= (1 << (n % 32));
}
#define NVIC_ICER_BASE (0xE000E180)
static inline void nvic_irq_disable(uint8_t n)
{
int i = n / 32;
volatile uint32_t *nvic_icer =
((volatile uint32_t *)(NVIC_ICER_BASE + 4 * i));
*nvic_icer |= (1 << (n % 32));
}
PERIPHERALS INTERRUPT CONFIGURATION
• The interrupt priorities are mapped in an array of 8-bit registers, each containing the
priority value for the corresponding interrupt line, starting at address 0xE000E400

#define NVIC_IPRI_BASE (0xE000E400)

static inline void nvic_irq_setprio(uint8_t n, uint8_t prio)
{
volatile uint8_t *nvic_ipri = ((volatile uint8_t *)
(NVIC_IPRI_BASE + n));
*nvic_ipri = prio;
}
SYSTEM TIME

• Timekeeping is a basic requirement for almost any embedded system

• A microcontroller can be programmed to trigger an interrupt at regular
intervals
• commonly used to increment the monotonic system clock
• To do so, a few configuration steps must be performed at startup in order
to have a stable tick interrupt
• Many processors can run at custom frequencies while using the same oscillator as
source
• The input frequency of the oscillator, which can be internal or external to
the CPU, is used to derive the processor main clock
• The configurable logic integrated in the CPU is implemented by a PLL
• multiplies the input clock from an external stable source,
• and produces the desired frequencies used by the CPU and integrated peripherals
CLOCK CONFIGURATION

• The configuration of the clocks happens through the Reset and Clock Control
(RCC) registers
• located at a specific address within the internal peripheral region
• RCC configuration is vendor-specific, as it depends on the logic of the PLL
implemented in the microcontroller
• The registers are described in the documentation of the microcontroller
• often, example source code is provided by the chip manufacturer to demonstrate how to
properly configure the clocks on the microcontroller
CLOCK DISTRIBUTION

• RCC logic can be programmed to distribute the clock to single peripherals

• To do so, the RCC exposes bit-mapped peripheral clock source registers
• Setting the corresponding bit in one of the registers enables the clock for each
mapped peripherals in the microcontroller
• Each register can control clock gating for 32 peripheral
• Keeping the clock source off for a peripheral that is not in use saves power
• if the target supports clock gating, it can implement optimization and fine-tuning of power
consumption by disabling the single peripherals at runtime through their clock gates
GENERIC TIMERS
• Some targets may not have a system timer
• But all of them expose some kind of interface to program a number of general-
purpose timers for the program
• to be able to implement time-driven operations
• Timers in general are very flexible and easy to configure,
• are generally capable of triggering interrupts at regular intervals
• Microcontrollers can support a number of features
• Including the selection of a different clock source for input
• Possibility to concatenate timers
• To program the internals of the timer implementation
• Possible to configure the timer to count up or down
• Trigger interrupt events on different values of the internal counter
• Timers can be one-shot or continuous.
GENERAL-PURPOSE I/O

• Majority of pins of a microcontroller chip represents configurable

input/output lines
• Each pin can be configured to represent a logic level
• by driving the voltage of the pin as a digital output
• or to sense the logic state by comparing the voltage as a digital input
• Some of the generic pins, though, can be associated to alternate functions,
• such as analog input, a serial interface, or the output pulse from a timer
• Pins may have several possible configurations, but only one is activated at a
time.
• The GPIO controller exposes the configuration of all the pins, and manages
the association of the pins to the subsystems when alternate functions are
in use
PIN CONFIGURATION

• Depending on the logic of the GPIO controller, the pins can be

activated all together, separately, or in groups
• To implement a driver to set up the pins and use them as needed, it is
possible to refer to the datasheet of the microcontroller
• There are different registers for configuring and using each digital I/O
group
• Examples:
• Mode register, Output type register, Output speed register, Port input/output data etc.
 PULSE WIDTH MODULATION

• Pulse Width Modulation (PWM)

is a commonly used technique to
control
• different types of actuators,
• encode messages into signal with
different pulse duration,
• and in general to generate pulses
with fixed frequency and variable
duty cycles on digital output lines
for different purposes
• Example:
• Control brightness of LED
INTERRUPT-BASED INPUT

• Having to proactively read the value of the pin by constantly polling

the IDR (Input Data Register) is not convenient in many cases,
• application is supposed to react to state changes
• Microcontrollers usually provide mechanisms to connect digital input
pins to interrupt lines,
• application can react in real time to events related to the input because the
execution is interrupted to execute the associated service routine
ANALOG INPUT

• Some pins have the possibility to measure the applied voltage dynamically,
• Assign a discrete number to the measured value, using an analog to digital signal
converter, or ADC
• This is very useful to acquire data from a wide range of sensors, capable of
conveying the information as output voltage, or simply using a variable resistor
• The configuration of the ADC subsystem may vary significantly across different
platforms
• ADCs on modern microcontrollers offer a wide range of configuration options
• Multiple features are available, such as DMA transfer of the acquired data, and monitoring
the signals in between two watchdog thresholds etc.
THE WATCHDOG

• Common feature in many microcontrollers is a watchdog timer

• Watchdog ensures that the system is not stuck within an endless loop or
any other blocking situation within the code
• This is particularly useful in bare-metal applications that rely on an event-
driven loop,
• where calls are required not to block,
• and to return to the main event loop within the allowed amount of time
• The watchdog must be seen as the very last resort to recover an
unresponsive system,
• by triggering a forced reboot regardless of the current state of the execution in the
CPU
LOCAL BUS INTERFACES

• Communication with other systems in the vicinity of the target is enabled by a

few protocols
• Most microcontrollers designed for embedded systems support the most
common interfaces that control and discipline the access to serial lines
• Some of these protocols are so popular that they have become the standard for
wired inter-chip communication
• among microcontrollers,
• for controlling electronic devices, such as sensors, actuators, displays, wireless transceivers,
• and many other peripherals
• In the following:
• Serial communication
• UART-based asynchronous serial bus
• SPI bus
• I2C bus
SERIAL COMMUNICATION

• Manage the access to a serial bus, which may consist of one or more wires,
• transporting the information in the form of electrical signals corresponding to logic levels, zeros and ones,
when associated with specific time intervals
• Protocols are different in the way they transmit and receive information on the data bus lines
• To transmit a byte, the transceiver encodes it as a bit sequence, which is synchronized with a clock
• The logic values of the bit are interpreted by the receiver reading its value on a specific front of the clock,
depending on the clock's polarity
• Each protocol specifies the polarity of the clock and the bit order required to transmit the data, which
can start with either the most or the least significant bit
CLOCK AND SYMBOL SYNCHRONIZATION

• In order for the receiving side to understand the message, the clock must be
synchronized between the parts
• The clock synchronization may be implicit, as in setting the same data rate to read and write
on the bus,
• or achieved by sharing the clock line from one side using an additional line, to explicitly
synchronize the transmit data rate
• Serial protocols that don't foresee shared clock lines are called asynchronous
• Symbol synchronization should instead be explicit.
• As we expect to send and receive information in byte form,
• the beginning of each eight bit sequence should be marked either through special preamble
sequences on the data line,
• or by turning the clock on and off at the right time
• The symbol synchronization strategy is defined by each protocol differently
BUS WIRING
• The number of lines needed to establish bidirectional communication depends on the
specific protocol too
• Since one wire can only transport one bit of information in one direction at a time,
• to achieve full-duplex communication, a transceiver should connect to two different wires for
transmitting and receiving data
• If the protocol supports half-duplex communication, it should instead provide a reliable
mechanism to regulate media access and switch between receiving and transmitting data on
the same wire
• Depending on the protocol:
• devices accessing the bus may either share a similar implementation and act as peers,
• or have different roles assigned when participating in the communication (Master/Slave)
• A serial protocol may foresee communication among more than two devices on the same
bus
• May be achieved by using extra slave selection wires, one per slave device sharing the same
bus,
• or by assigning logical addresses to each endpoint, and including the destination address for
the communication in the preamble of each transmission
 Symbol
Protocol Number of wires Clock synchronization Bit order Communication mode
strategy
Configurable
One-to-one or one-to-many, single
UART-based Two (data RX/TX) Asynchronous start/stop bit, LSB first
point-to-point communication
parity bit
Three (master to slave One-to-many single master, multiple
MSB first or
SPI data, slave to master data, Shared through CLK Clock activation slave, using additional slave-selection
LSB first
clock) lines
Clock activation, One-to-many, master/slave with logic
Two (serial data and serial
I2C Shared through SCL with support for MSB first addresses, and dynamic multi-master
clock)
clock stretching selection
Synchronized with a
synchronization
Two (D+/D- half-duplex CRC / end of One host/multiple devices with device
USB pattern at the LSB first
differential signal) packet enumeration
beginning of data
transfer
Two (CAN-Hi and CAN-
Low), differential, half Start bit, CRC, and One-to-many multi-master with
CAN bus Asynchronous MSB first
duplex end sequence address-based master arbitration

Synchronized with Slave selection

Master/slave with fixed master, slave
Dallas 1-Wire One data wire the front of the before each byte LSB first
discovery with 64-bit addresses
signal CRC
UART-BASED ASYNCHRONOUS SERIAL BUS

• Stands for Universal Asynchronous Reception and Transmission (UART)

• Simple serial communication protocol that allows the host communicate
with the auxiliary device.
• UART supports bidirectional, asynchronous and serial data transmission.
• It has two data lines, one to transmit (TX) and another to receive (RX)
which is used to communicate through digital pin 0, digital pin 1.
• TX and RX are connected between two devices. (eg. USB and computer)
• UART can also handle synchronization management issues between
computers and external serial devices.
HOW DOES UART WORK?

• It can operate between devices in 3 ways:

• Simplex, Half duplex, and Full duplex
• Once connected, data flows from TX to RX of the receiving UART
• As UART is an asynchronous serial transmission = No clocks
• Transmitting UART converts parallel data from master device (eg.
CPU) into serial form and transmit in serial to receiving UART
• It will then convert the serial data back into parallel data for the
receiving device
HOW DOES UART WORK? (CONTD.)

• As UART has no clocks, UART adds start and stop bits that are being
transferred
• Helps receiving UART know when to start reading bits as the bits represent
the start and the end of the data packet
• When the receiving UART detect a start bit, it will read the bits at BAUD rate
• UART data transmission speed is referred to as BAUD Rate and is set
to 115,200 by default (BAUD rate is based on symbol transmission
rate, but is similar to bit rate)
• Both UARTs must operate at about the same baud rate.
ADVANTAGES OF USING UART

• Simple to operate, well documented as it is a widely used method

with a lot of resources online
• No clock needed
• Parity bit to allow for error checking
DISADVANTAGES OF USING UART

• Size of data frame is limited to only 9 bits

• Cannot use multiple master systems and slaves
• Baud rates of each UART must be within 10% of each other to prevent
data loss
• Low speed
SERIAL PERIPHERAL INTERFACE (SPI)

• Different form of serial-communications protocol specially designed

for microcontrollers to connect
• Operates at full duplex where data can be sent and received
simultaneously
• Operate at faster data transmission rates = 8Mbits or more
• Even if data/clock lines are shared between devices, each device will
require a unique address wire
• Used in places where speed is important.
• For example: SD cards, display modules or when info updates and changes
quickly like thermometers
HOW DOES SPI WORK?

• Communicate with 2 ways:

• The first is by selecting each device with a Chip Select line. A separate Chip Select
line is required for each device.
• The second is through daisy chaining where each device is connected to the other
through its data out to the data in line of the next.
• There is no limit to the number of SPI device that can be connected.
• However, there are practical limits due to the number of hardware select lines
available on the main device with the chip select method
• or the complexity of passing data through devices in the daisy chaining method
• In point-to-point communication, the SPI interface does not require
addressing operations and is full-duplex communication,
• simple and efficient
ADVANTAGES OF USING SPI

• Protocol is simple as there is no complicated slave addressing system

• It is the fastest protocol compared to UART and I2C.
• No start and stop bits unlike UART which means data can be
transmitted continuously without interruption
• Separate MISO and MOSI lines which means data can be transmitted
and received at the same time
DISADVANTAGES OF USING SPI

• More Pin ports are occupied, practical limit to number of devices.

• There is no flow control specified, and no acknowledgement
mechanism confirms whether data is received
• Uses four lines – MOSI, MISO, NCLK, NSS
• No form of error check unlike in UART (using parity bit)
• Only 1 master