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Q1. What is the size of address and data bus in the 8086?

-Intel 8086 is 16-bit processor designed by Intel in 1978 and laid the
foundation for the x86 architecture.
-The performance of Intel 8086 depends on the modes and it have clock
frequencies up to 10MHZ.
Intel 8086 modes of operation
-Minimum Mode: For single-processor systems.
- Maximum Mode: For multi-processor systems
The Intel 8086 microprocessor has:
-A 16-bit data bus, which allows it to transfer 16 bits of data at a time.
-A 20-bit address bus, enabling it to access up to 2^20 memory locations.

Q2.Draw the register organization of the 8086 and explain

typical applications of each register.
The 8086 microprocessor has a well-organized set of registers that are
classified into general-purpose registers, segment registers, pointer and
index registers, and status/control registers. Below is the register
organization diagram followed by an explanation of their applications.
Diagram: Register Organization of 8086

Category Registers Size

General-Purpose Registers AX, BX, CX, DX 16 bits

Segment Registers CS, DS, SS, ES 16 bits

 Category Registers Size

Pointer Registers SP (Stack Pointer), BP (Base Pointer) 16 bits

Index Registers SI (Source Index), DI (Destination Index) 16 bits

Instruction Pointer IP (Instruction Pointer) 16 bits

Status/Control Registers FLAGS Register 16 bits

Explanation of Registers and Their Applications

1. General-Purpose Registers

These are versatile registers used for arithmetic, logical operations, and data
manipulation. They can also be divided into two 8-bit parts: higher (H) and
lower (L).
 AX (Accumulator Register): Used for arithmetic and logical operations. It is
the default register for input/output instructions.
 BX (Base Register): Often used as a base address for memory access.
 CX (Count Register): Primarily used as a counter in loop and string
operations.
 DX (Data Register): Used for I/O operations and multiplication/division
involving large data.

2. Segment Registers

Segment registers define the base address of memory segments in the

segmented memory model.
 CS (Code Segment): Points to the segment containing executable instructions.
 DS (Data Segment): Points to the segment containing program data.
 SS (Stack Segment): Points to the segment used for stack operations.
 ES (Extra Segment): Used as an additional data segment, often in string
operations.

3. Pointer Registers

Pointer registers hold offset addresses within segments.

 SP (Stack Pointer): Points to the top of the stack. It is used during push/pop
operations.
 BP (Base Pointer): Used to access data within the stack segment, particularly
in subroutine calls.

4. Index Registers

Index registers are used for offset calculations in memory addressing.

 SI (Source Index): Typically used as a source pointer in string operations.
 DI (Destination Index): Typically used as a destination pointer in string
operations.

5. Instruction Pointer

 IP: Holds the offset address of the next instruction to be executed. It works
with CS to form a physical address for fetching instructions.
6. Status/Control Registers
The FLAGS register contains condition flags that reflect results of
arithmetic/logical operations and control flags that influence processor
behavior.
 Condition Flags:
 Carry Flag (CF), Zero Flag (ZF), Sign Flag (SF), Overflow Flag (OF), etc.
 Control Flags:
 Interrupt Flag (IF), Direction Flag (DF), Trap Flag (TF).

Typical Applications of Each Register

1. General-Purpose Registers:
 Performing arithmetic/logical operations.
 Temporary storage during program execution.
 Loop counters and base addresses for memory access.
2. Segment Registers:
 Efficiently accessing different parts of memory using segmentation.
 Organizing code, data, and stack separately for better modularity.
3. Pointer and Index Registers:
 Facilitating stack manipulation during function calls or interrupts.
 Supporting advanced addressing modes like indexed or based addressing.
4. Instruction Pointer:
 Ensuring sequential execution of instructions by pointing to the next
instruction.
5. FLAGS Register:
 Controlling program flow based on results of comparisons or arithmetic
operations.
 Enabling/disabling interrupts or managing string operation directions.

Q3.How is the 20-bit physical memory address calculated in the

8086 processor?
In the 8086 microprocessor, the 20-bit physical memory address is
calculated using segmentation. The processor uses a combination of a 16-bit
segment address (stored in one of the segment registers) and a 16-bit offset
 address (stored in an offset register) to generate the 20-bit physical address.
This allows the 8086 to access up to 1 MB of memory.

Calculation of the Physical Address

The formula for calculating the physical address is:

Physical Address=(Segment Register×16)+Offset AddressPhysical Address=(S
egment Register×16)+Offset Address
 The segment register value is multiplied by 16 (or shifted left by 4 bits),
effectively appending four zeros to its right.
 The offset address is then added to this shifted value to generate the final 20-
bit physical address.

Example:-If:

 Segment Register = 0x1000

 Offset Address = 0x0010
The physical address is calculated as:
Physical Address=(0x1000×16)+0x0010=0x10000+0x0010=0x10010
Thus, the physical address is 0x10010.

Segment Registers and Their Uses

The segment registers and their corresponding purposes are:

 CS (Code Segment): Holds the base address for code instructions. Offset is
typically provided by the Instruction Pointer (IP).
 DS (Data Segment): Holds the base address for data. Offset can be provided
by registers like SI, DI, or BX.
 SS (Stack Segment): Holds the base address for stack operations. Offset is
usually provided by SP or BP.
 ES (Extra Segment): Used for additional data storage or destination
addresses in string operations.

Q4.Write the different memory segments used in the 8086 and their
functions.

The Intel 8086 microprocessor uses memory segmentation to divide its

addressable memory space into manageable segments.
 There are four memory segment in 8086 microprocessor:
Code Segment -This segment stores the executable instructions of a
program.
Data Segment - Holds global and static data variables used during
program execution.
Stack Segment - Manages stack operations such as function calls and
temporary storage.
Extra Segment - Provides an additional data segment for
overflowed information.
Q5.Write the function of the DF, IF and TF bits in the 8086.
The DF,IF and TF are control flags located in the Flag Register, these flags
play key roles in controlling program execution and system behavior.
DF (Direction Flag) – It’s function is Controlling the direction of string
operations and it uses MOVS, CMPS, SCAS, LODS, and STOS to determine
the direction of data processing.
IF (Interrupt Flag) - Enables or disables maskable hardware interrupts
also have instructions like CLI and STI.
TF (Trap Flag) - Enables single-step debugging by generating a trap
interrupt after every instruction.

Q6.The content of the different registers in the 8086 is CS = F000H,

DS = 1000H, SS = 2000H and ES = 3000H. Find the base address of the
different segments in the memory.

The base address of a segment in the 8086 microprocessor is calculated by

multiplying the value in the segment register by 1616 (or shifting it left by 4
 bits). This process appends four zeros to the right of the segment register
value, producing the base address.
Given the segment register values:
 CS = F000H
 DS = 1000H
 SS = 2000H
 ES = 3000H

Calculation of Base Addresses

1. Code Segment (CS):

Base Address=F000H×16=F0000HBase Address=F000H×16=F0000H
2. Data Segment (DS):
Base Address=1000H×16=10000HBase Address=1000H×16=10000H
3. Stack Segment (SS):
Base Address=2000H×16=20000HBase Address=2000H×16=20000H
4. Extra Segment (ES):
Base Address=3000H×16=30000HBase Address=3000H×16=30000H

Q7.What is the difference between the minimum and maximum mode

operation of the 8086?

The 8086 microprocessor operates in two distinct modes—

minimum and maximum—determined by the state of the MN/MX̄ pin (pin
33). In minimum mode, the 8086 functions as a single-processor system,
generating all control signals internally. In maximum mode, it supports
multiprocessing with external coprocessors (e.g., 8087, 8089) and relies on
the 8288 bus controller to manage system operations.

Key Differences
 Aspect Minimum Mode Maximum Mode

Multi-processor/coprocessor
Configuration Single-processor system system

Generated internally by the Generated by the 8288 bus

Control Signals 8086 controller

MN/MX̄ Pin State Set to logic 1 (high) Set to logic 0 (low)

More complex due to bus

Complexity Simpler circuit design arbitration

Bus Arbitration Uses HOLD/HLDA signals Uses RQ̄ /GT̄ signals

Higher performance (parallel

Performance Lower performance processing)

INTĀ signal generated by the

Interrupt Handling 8086 INTĀ signal generated by the 8288

Pin Functions (24– Direct control signals (e.g., Status/control signals for
31) ALE, DEN̄ ) multiprocessing
 Q8.What is meant by DMA operation? Which pins of the 8086 are
used to perform the DMA operation in the minimum and
maximum modes of the 8086?
Direct Memory Access (DMA) is a hardware feature that allows peripherals
or co-processors to transfer data directly to/from system memory without
continuous CPU involvement, improving efficiency by freeing the CPU for
other tasks. In the 8086 microprocessor, DMA operation is managed through
specific pins depending on its operating mode:

DMA Pins in 8086 Modes

Mode Pins Used Function

- HOLD: Requests control of the system bus from the

CPU.
Minimum - HLDA: CPU acknowledges the request and releases
Mode HOLD and HLDA the bus.

- RQ/GT0 (higher priority) and RQ/GT1 (lower

priority) handle bidirectional bus arbitration.
Maximum RQ/GT0 and RQ/ - A peripheral sends a request via RQ, and the CPU
Mode GT1 responds with a grant (GT) to relinquish bus control
 Q9.Explain the architecture of the 8086 with a neat functional block
diagram.

The 8086 microprocessor is divided into two main functional units:

1. Bus Interface Unit (BIU)
2. Execution Unit (EU)
These units work independently and simultaneously, enabling pipelined
architecture for faster processing and increased throughput. Below is the
functional block diagram and explanation of each unit.

Functional Block Diagram of 8086

 Explanation of Functional Units

1. Bus Interface Unit (BIU)

The BIU handles all interactions with memory and I/O devices. It is
responsible for fetching instructions, reading/writing data, and calculating
physical addresses.
 Segment Registers: CS (Code Segment), DS (Data Segment), SS (Stack
Segment), ES (Extra Segment). These define the base addresses of memory
segments.
 Instruction Pointer (IP): Holds the offset address of the next instruction to
be executed.
 Instruction Queue: A 6-byte FIFO queue that prefetches instructions to
improve execution speed.
 Address Adder: Combines segment base address and offset to generate a 20-
bit physical address.
 Bus Control Logic: Manages the data bus, address bus, and control signals for
memory and I/O operations.

2. Execution Unit (EU)

The EU executes instructions fetched by the BIU. It performs

arithmetic/logical operations and controls program flow.
 Arithmetic Logic Unit (ALU): Executes arithmetic and logical operations.
 General Registers: AX (Accumulator), BX (Base Register), CX (Count
Register), DX (Data Register).
 Pointer Registers: SP (Stack Pointer), BP (Base Pointer).
 Index Registers: SI (Source Index), DI (Destination Index).
 Flags Register: Contains condition flags (e.g., Zero Flag, Carry Flag) and
control flags (e.g., Interrupt Flag).

Key Features of 8086 Architecture

1. Pipelined Architecture: BIU fetches instructions while EU executes them,

improving throughput.
2. Memory Segmentation: Allows access to up to 1 MB of memory by dividing it
into segments of 64 KB each.
3. Instruction Queue: Prefetching instructions reduces execution delays.
4. Separate BIU and EU: Enables simultaneous fetching and execution.
 Q10.Explain the function of different flags in the 8086.

The flag register in the 8086 microprocessor is a 16-bit register that holds
information about the state of the processor and the results of arithmetic or
logical operations. It consists of 9 active flags, categorized into conditional
flags and control flags.

1. Conditional Flags

These flags reflect the outcome of arithmetic or logical operations.

 Carry Flag (CF): Indicates a carry out or borrow into the most significant bit
during arithmetic operations. It is set to 1 if there is a carry/borrow;
otherwise, it is 0.
 Parity Flag (PF): Indicates whether the number of 1s in the lower byte of the
result is even (set to 1) or odd (set to 0).
 Auxiliary Carry Flag (AF): Set when there is a carry/borrow between the
lower nibble (bits D0–D3) and upper nibble (bits D4–D7) in an operation. It is
used for BCD (Binary Coded Decimal) arithmetic.
 Zero Flag (ZF): Set to 1 if the result of an operation is zero; otherwise, it is
cleared.
 Sign Flag (SF): Reflects the sign of the result. It is set to 1 if the result is
negative (most significant bit = 1); otherwise, it is cleared.
 Overflow Flag (OF): Indicates whether an arithmetic operation has resulted
in a value too large for the destination to hold. It is set for signed overflow.

2. Control Flags

These flags control specific operations within the processor.

 Trap Flag (TF): Enables single-step execution for debugging. When set, the
processor generates an interrupt after executing each instruction.
 Interrupt Flag (IF): Controls whether external interrupts are enabled or
disabled. When set, interrupts are allowed; when cleared, they are disabled.
 Direction Flag (DF): Determines the direction for string operations. If set,
string operations process data from high memory to low memory; if cleared,
they process from low memory to high memory.

Q11.What is the function of segment override prefix? Give two

examples?

The segment override prefix in the 8086 microprocessor allows a

program to explicitly specify a segment register for
a memory operation, overriding the default segment register that the CPU
would normally use.
Function:
It changes the default segment register (e.g., DS for data, SS for stack) to
another segment register (e.g., CS, ES, FS, GS) for a specific instruction.
Examples:MOV AX, ES:[BX]:
Overrides the default DS segment with the ES segment.
Fetches data from the memory location pointed to by ES:BX instead
of DS:BX.
MOV CX, CS:[SI]:
Overrides the default DS segment with the CS segment.
Fetches data from the memory location pointed to by CS:SI instead
of DS:SI.
This prefix is useful when accessing data in non-default segments without
changing the default segment registers.
Q12.What is the difference between inter-segment and intra-
segment jump in the 8086?

In the 8086 microprocessor, jumps are classified into two types based on
memory addressing: intra-segment and inter-segment.
1.Intra-Segment Jump:
Definition: A jump within the same code segment.
Addressing: Only the IP (Instruction Pointer) is modified; the CS (Code
Segment) register remains unchanged.
Range: Limited to ±32KB within the current segment.
Example: JMP SHORT LABEL or JMP NEAR PTR LABEL.
2.Inter-Segment Jump:
Definition: A jump to a different code segment.
Addressing: Both the CS (Code Segment) and IP (Instruction Pointer) are
modified to point to the new segment and offset.
Range: Can jump anywhere in the 1MB address space.
Example: JMP FAR PTR LABEL.
Key Difference:
Intra-segment jumps stay within the same segment (only IP changes).
Inter-segment jumps move to a different segment (both CS and IP
change).
Q13.What is the difference between short and near jump in the
8086?
In the 8086 microprocessor, short and near jumps are types of intra-segment
jumps (within the same code segment), but they differ in their range and
encoding:
1.Short Jump:
Range: Can jump within -128 to +127 bytes from the current instruction.
Encoding: Uses 1 byte for the opcode and 1 byte for the relative offset (8-bit
displacement).
Example: JMP SHORT LABEL.

2.Near Jump:
Range: Can jump within ±32KB from the current instruction.
Encoding: Uses 1 byte for the opcode and 2 bytes for the relative offset (16-bit
displacement).
Example: JMP NEAR PTR LABEL.
Key Difference:
Short jump is limited to a smaller range (±128 bytes) and uses a smaller offset
(8-bit).
Near jump covers a larger range (±32KB) and uses a larger offset (16-bit).
Q14.What are the different uses of stack in a microprocessor?
-The stack is a special region of memory that use LIFO to store temporary
data. There are about 6 primary use of stack:
Function Calls and Return Addresses - During a function call, the return
address is pushed onto the stack and when function completes the return
address is popped from the stack.
Temporary Storage of Data - stores data such as register contents while
other operations are performed.
Passing Parameters to Functions - Parameters for functions can be
passed via the stack and useful in Parameters for functions or subroutines
can be passed via the stack.
Interrupt Handling - When an interrupt occurs, the processor pushes the
current program counter and status flags onto the stack.
Q15.What is the difference between the MUL and IMUL instructions
in the 8086?

In the 8086 microprocessor, MUL and IMUL are instructions for

multiplication, but they differ in the type of numbers they handle and how
they process them:
1.MUL (Unsigned Multiplication):
Operation: Performs unsigned multiplication.
Operand: Multiplies an 8-bit or 16-bit unsigned number by
the AL or AX register.
Result:
For 8-bit: Result is stored in AX.
For 16-bit: Result is stored in DX:AX (upper 16 bits in DX, lower 16 bits in
AX).
Example: MUL BL (multiplies AL by BL, result in AX).

2.IMUL (Signed Multiplication):

Operation: Performs signed multiplication.
Operand: Multiplies an 8-bit or 16-bit signed number by
the AL or AX register.
Result:
For 8-bit: Result is stored in AX.
For 16-bit: Result is stored in DX:AX (upper 16 bits in DX, lower 16 bits in
AX).
Example: IMUL BX (multiplies AX by BX, result in DX:AX).
Key Difference:
MUL is for unsigned numbers.
 IMUL is for signed numbers.
Both store results in AX (8-bit) or DX:AX (16-bit), but IMUL handles
negative values correctly.

Q16.What is the difference between the DIV and IDIV instructions in

the 8086?

In the 8086 microprocessor, DIV and IDIV are instructions for division,
but they differ in the type of numbers they handle and how they
process them:
1.DIV (Unsigned Division):
Operation: Performs unsigned division.
Operand: Divides an 16-bit or 32-bit unsigned number
in AX or DX:AX by an 8-bit or 16-bit unsigned divisor.
Result:
For 8-bit: Quotient is stored in AL, remainder in AH.
For 16-bit: Quotient is stored in AX, remainder in DX.
Example: DIV BL (divides AX by BL, quotient in AL, remainder in AH).
2.IDIV (Signed Division):
Operation: Performs signed division.
Operand: Divides an 16-bit or 32-bit signed number in AX or DX:AX by
an 8-bit or 16-bit signed divisor.
Result:
For 8-bit: Quotient is stored in AL, remainder in AH.
For 16-bit: Quotient is stored in AX, remainder in DX.
Example: IDIV BX (divides DX:AX by BX, quotient in AX, remainder in
DX).
Key Difference:
DIV is for unsigned numbers.
IDIV is for signed numbers.
Both store the quotient and remainder in the same registers,
 but IDIV handles negative values correctly.

Q17.What is the function of DAA instruction in the 8086?

The DAA (Decimal Adjust after Addition) instruction in the 8086
microprocessor is used to adjust the result of an addition operation to
produce a valid BCD (Binary-Coded Decimal) result. BCD is a way to represent
decimal numbers in binary form, where each digit (0-9) is represented by a 4-
bit binary number.

Purpose of DAA

After adding two BCD numbers using the ADD instruction, the result may not
be a valid BCD number. The DAA instruction corrects this result to ensure it is
a valid BCD number and It works only on the AL register.

How DAA Works?

If the lower nibble (4 bits) of AL is greater than 9 or the Auxiliary Carry Flag
(AF) is set, the DAA instruction adds 6 to AL.

If the upper nibble of AL is greater than 9 or the Carry Flag (CF) is set, the DAA
instruction adds 6 to the upper nibble of AL.

Example
MOV AL, 35H ; Load AL with 35H (BCD for 35)

ADD AL, 47H ; Add 47H (BCD for 47) to AL

DAA ; Adjust AL to valid BCD

 Q18.What is the difference between maskable and non-
maskable interrupts?
Difference Between Maskable and Non-Maskable Interrupts

Interrupts are signals sent to the processor to request its attention. They can
be categorized into maskable and non-maskable interrupts based on whether
the processor can ignore them or not.

1. Maskable Interrupts

Definition: Maskable interrupts are interrupts that can be ignored or disabled

by the processor.

Control: The processor can enable or disable these interrupts using the
Interrupt Flag (IF) in the flag register.

 If IF = 1, maskable interrupts are enabled.

 If IF = 0, maskable interrupts are disabled.

Examples:

o Hardware interrupts from peripherals like keyboards, timers, etc.

o Software interrupts (e.g., INT instruction in 8086).
STI ; Enable maskable interrupts
CLI ; Disable maskable interrupts

How to Enable/Disable Maskable Interrupts

o Enable: Use the STI (Set Interrupt Flag) instruction.
o Disable: Use the CLI (Clear Interrupt Flag) instruction.

2. Non-Maskable Interrupts (NMI)

Definition: Non-maskable interrupts are interrupts that cannot be
ignored or disabled by the processor.

Control: These interrupts are always serviced, regardless of the state of

the Interrupt Flag (IF).

Examples:
Critical hardware failures (e.g., power failure, memory parity error).
High-priority events that require immediate attention.

Key Differences Between Maskable and Non-Maskable Interrupts

Maskable Interrupts:-Can be ignored or disabled by the processor

-Controlled by the Interrupt Flag (IF)

- Have Lower priority and it’s Instructions are STI (Enable), CLI
(Disable)
Examples:- Keyboard, timer, software interrupts
Non-Maskable Interrupts (NMI):- Cannot be ignored or disabled

- Not controlled by the Interrupt Flag (IF)

- Higher priority and No specific instructions (always enabled)
Examples:- Power failure, memory parity error
 Q19What is the difference between hardware and software
interrupts?
-Interrupts are signals that temporarily halt the normal execution of a
program to handle a specific event. They can be categorized into hardware
interrupts and software interrupts based on their source.

1. Hardware Interrupts

 Definition: Hardware interrupts are generated by external hardware

devices to request the processor's attention.
 Source: These interrupts are triggered by hardware devices such as
keyboards, mice, timers, disk drives, etc.
 Control: Hardware interrupts can be maskable or non-maskable.
o Maskable: Can be enabled or disabled using the Interrupt Flag (IF).
o Non-Maskable (NMI): Cannot be disabled and must always be serviced.

Examples:

o A key is pressed on the keyboard.

o A timer reaches its specified value.
 How Hardware Interrupts Work
1. The hardware device sends an interrupt request (IRQ) to the processor.
2. The processor stops its current task and saves its state (e.g., registers,
program counter).
3. The processor jumps to the interrupt service routine (ISR) to handle the
interrupt.
4. After servicing the interrupt, the processor resumes its previous task.

2. Software Interrupts

Definition: Software interrupts are generated by software instructions to

request the processor's attention.
Source: These interrupts are triggered by executing specific instructions in a
program (e.g., INT in 8086).

Control: Software interrupts are always non-maskable because they are

explicitly invoked by the program.

Examples:System calls (e.g., file operations, memory allocation).

Debugging (e.g., breakpoints).

How Software Interrupts Work

 The program executes a software interrupt instruction (e.g., INT 21H).

 The processor stops its current task and saves its state.
 The processor jumps to the interrupt service routine (ISR) associated
with the interrupt number.
 After servicing the interrupt, the processor resumes its previous task.

Example:

MOV AH, 09H ; Function to display a string

LEA DX, MSG ; Load address of the message

INT 21H ; Invoke software interrupt 21H

MSG DB "Hello, World!$"

 Key Differences Between Hardware and Software Interrupts.

Aspect Hardware Interrupts Software Interrupts

Source External hardware devices Software instructions

(e.g., INT)

Control Can be maskable or non-maskable Always non-maskable

Trigger Generated by hardware signals Generated by executing specific

instructions instructions

Examples Keyboard, timer, disk drive System calls, debugging

Priority Depends on the hardware device Depends on the software
instruction

Q20.Write a program to move a word string 200 bytes (i.e.

100 words) long from the offset address 1000H to the offset
address 3000H in the segment 5000H.
Assembly Program

MOV AX, 5000H ; Load segment address 5000H into AX

MOV DS, AX ; Set DS (Data Segment) to 5000H

MOV ES, AX ; Set ES (Extra Segment) to 5000H (same segment)

MOV SI, 1000H ; Set SI (Source Index) to 1000H (source offset)

MOV DI, 3000H ; Set DI (Destination Index) to 3000H (destination offset)

MOV CX, 100 ; Set CX (Counter) to 100 (100 words = 200 bytes)

CLD ; Clear Direction Flag (DF = 0) for auto-increment

REP MOVSW ; Move 100 words from [SI] to [DI]

HLT ; Halt the program

Q21.Write a program to find the smallest word in an array of 100
words stored sequentially in the memory; starting at the offset
address 1000H in the segment address 5000H. Store the result at
the offset address 2000H in the same segment?
Assembly Program

MOV AX, 5000H ; Load segment address 5000H into AX

MOV DS, AX ; Set DS (Data Segment) to 5000H

MOV SI, 1000H ; Set SI (Source Index) to 1000H (start of array)

MOV CX, 99 ; Set CX (Counter) to 99 (100 words - 1)

LODSW ; Load first word into AX

MOV BX, AX ; Store first word in BX (assume it's the smallest)

FindSmallest:

LODSW ; Load next word into AX

CMP AX, BX ; Compare AX with BX

JAE Skip ; If AX >= BX, skip

MOV BX, AX ; Update BX with the new smallest word

Skip:

LOOP FindSmallest ; Repeat for all words

MOV DI, 2000H ; Set DI (Destination Index) to 2000H

MOV [DI], BX ; Store the smallest word at 2000H

HLT ; Halt the program