Programmable Logic

• So far, have only talked about PALs (see

22V10 figure next page).
22V10 PLD
• What is the next step in the evolution of
PLDs?
– More gates!
• How do we get more gates? We could put
several PALs on one chip and put an
interconnection matrix between them!!
– This is called a Complex PLD (CPLD).

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Cypress CPLD
Programmable
interconnect matrix.
Any other approaches?
Another approach to building a “better” PLD is place a lot of
primitive gates on a die, and then place programmable interconnect
between them:

Each logic block is

similar to a 22V10.

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Field Programmable Gate Arrays Other FPGA features

The FPGA approach to arrange primitive logic elements • Besides primitive logic elements and
(logic cells) arrange in rows/columns with programmable programmable routing, some FPGA families
routing between them. add other features
What constitutes a primitive logic element? Lots of different • Embedded memory
choices can be made! Primitive element must be classified as a
“complete logic family”. – Many hardware applications need memory for data
storage. Many FPGAs include blocks of RAM for
• A primitive gate like a NAND gate
this purpose
• A 2/1 mux (this happens to be a complete logic family)
• Dedicated logic for carry generation, or other
• A Lookup table (I.e, 16x1 lookup table can implement any
4 input logic function).
arithmetic functions
Often combine one of the above with a DFF to form the • Phase locked loops for clock synchronization,
primitive logic element. division, multiplication.
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Altera Flex 10K FPGA Family Altera Flex 10K FPGA Family (cont)

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Dedicated memory

16 x1 LUT

DFF

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Emedded Array Block

• Memory block, Can be configured:
– 256 x 8, 512 x 4, 1024 x 2, 2048 x 1

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 Altera APEX II Differential Serial IO support in APEX II

• Altera’s latest FPGA family is the APEX II

• Latest addition is support for high speed serial
transfer protocols, embedded processor cores

Separate PLL
for differential
receivers

1 Gbps per
receiver

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Altera Excalibur device has embedded processor + programmable Altera NIOS processor IP block
logic.
• An IP (Intellectual Property) block is some functional block
such as a PCI bus interface, processor, etc specified in an RTL
and mapped to an FPGA implementation
– Altera licenses IP based on their FPGAs so companies do
not have to re-invent the wheel
• NIOS softcore processor specs:
– Load/store RISC architecture
Logic – Datapath size of 16 or 32 bits
– 16 bit instruction set
– 5 stage pipeline
– Up to 512 registers (windowed, 32 visible)
– 13% of Apex 20K200 device (16 bit datapath), 20% in 32-
bit datapath configuration
– User can add custom instructions
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Issues in FPGA Technologies Issues in FPGA Technologies (cont)

• Complexity of Logic Element • Macro elements
– How many inputs/outputs for the logic element? – Are there SRAM blocks? Is the SRAM dual ported?
– Does the basic logic element contain a FF? What type? – Is there fast adder support (i.e. fast carry chains?)
• Interconnect – Is there fast logic support (i.e. cascade chains)
– How fast is it? Does it offer ‘high speed’ paths that cross the – What other types of macro blocks are available (fast decoders?
chip? How many of these? register files? )
– Can I have on-chip tri-state busses? • Clock support
– How routable is the design? If 95% of the logic elements are – How many global clocks can I have?
used, can I route the design? – Are there any on-chip Phase Logic Loops (PLLs) or Delay
• More routing means more routability, but less room for Locked Loops (DLLs) for clock synchronization, clock
logic elements multiplication?

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 Issues in FPGA Technologies (cont) Altera FPGA Family Summaries
• What type of IO support do I have?
– TTL, CMOS are a given • Altera Flex10K/10KE
– Support for mixed 5V, 3.3v IOs? – LEs (Logic elements) have 4-input LUTS (look-up tables)
+1 FF
• 3.3 v internal, but 5V tolerant inputs?
– Fast Carry Chain between LE’s, Cascade chain for logic
– Support for new low voltage signaling standards?
operations
• GTL+, GTL (Gunning Tranceiver Logic) - used on Pentium II
• HSTL - High Speed Transceiver Logic
– Large blocks of SRAM available as well
• SSTL - Stub Series-Terminate Logic • Altera Max7000/Max7000A
• USB - IO used for Universal Serial Bus (differential signaling) – EEPROM based, very fast (Tpd = 7.5 ns)
• AGP - IO used for Advanced Graphics Port – Basically a PLD architecture with programmable
– Maximum number of IO? Package types? interconnect.
• Ball Grid Array (BGA) for high density IO – Max 7000A family is 3.3 v

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Xilinx FPGA Family Summaries Xilinx Virtex II Family

• Virtex Family • Virtex II is Xilinx’s latest & greatest
– SRAM Based • New technology:
– Largest device has 1M gates – embedded multipliers 18x18=36 bit, 2’s complement (signed
multiplier)
– Configurable Logic Blocks (CLBs) have two 4-input LUTS, 2
– Differential serial IO
DFFs
• Multiplier inputs are linked to embedded SRAM outputs for
– Four onboard Delay Locked Loops (DLLs) for clock speed.
synchronization – Intended to be used for digital filter applications where sample
– Dedicated RAM blocks (LUTs can also function as RAM). cofficient values are stored in the SRAM

– Fast Carry Logic • A FIR filter (finite impulse response) equation has the form
y = x * a0 + x[1]*a1 + x[2]*a2 +…. X[N-1]* aN-1
• XC4000 Family The ‘x’ values are previous sample values (x[1] is one sample
– Previous version of Virtex back), the ‘a’ values are coefficient.
– No DLLs, No dedicated RAM blocks
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Virtex II basic Logic Module

Actel FPGA Family Summaries
4-input LUT, can • MXDS Family
also be used as – Fine grain Logic Elements that contain Mux logic + DFF
RAM,ROM
– Embedded Dual Port SRAM
Used for building – One Time Programmable (OTP) - means that no
distributed configuration loading on powerup, no external serial ROM
multipliers – AntiFuse technology for programming (AntiFuse means
that you program the fuse to make the connection).
Dedicated carry
– Fast (Tpd = 7.5 ns)
logic
Storage – Low density compared to Altera, Xilinx - maximum number
element – of gates is 36,000
FF or latch,
enabled
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Actel ProAsic basic logic module
Cypress CPLDs
• Ultra37000 Family
– 32 to 512 Macrocells
– Fast (Tpd 5 to 10ns depending on number of
macrocells)
– Very good routing resources for a CPLD
Extremely primitive logic module (fine-grain architecture).
Mux is basic building block – two muxes shown can
implement a DFF via a master/slave latch arrangement.

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