assignment2
assignment2
NOTE: Zero marks will be awarded if the contents of two submissions are same
Q2. Let the page fault service time be 10ms in a computer with average memory access time
being 20ns. If one page fault is generated for every 10^6 memory accesses, what is the
effective access time for the memory?
Q3. A system uses FIFO policy for page replacement. It has 4 page frames with no pages
loaded to begin with. The system first accesses 100 distinct pages in some order and then
accesses the same 100 pages but now in the reverse order. How many page faults will occur?
Q4. Why multilevel page table is preferred in comparison to a single level page table for
translating virtual address to physical address ?
Q5 Assume that there are 3 page frames which are initially empty. If the page reference string is
1, 2, 3, 4, 2, 1, 5, 3, 2, 4, 6, the number of page faults using the optimal replacement policy is
Q6computer has twenty physical page frames which contain pages numbered 101 through 120.
Now a program accesses the pages numbered 1, 2, …, 100 in that order, and repeats the
access sequence THRICE. Which one of the following page replacement policies experiences
the same number of page faults as the optimal page replacement policy for this program?
Q7. A system uses 3 page frames for storing process pages in main memory. It uses the Least
Recently Used (LRU) page replacement policy. Assume that all the page frames are initially
empty. What is the total number of page faults that will occur while processing the page
reference string given below? 4, 7, 6, 1, 7, 6, 1, 2, 7, 2
Q8. Consider a paging hardware with a TLB. Assume that the entire page table and all the
pages are in the physical memory. It takes 10 milliseconds to search the TLB and 80
milliseconds to access the physical memory. If the TLB hit ratio is 0.6, the effective memory
access time (in milliseconds) is _________
Q9. The memory access time is 1 nanosecond for a read operation with a hit in cache, 5
nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation
with a hit in cache and 10 nanoseconds for a write operation with a miss in cache. Execution of
a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read
operations and 40 memory operand write operations. The cache hit-ratio is 0.9. The average
memory access time (in nanoseconds) in executing the sequence of instructions is __________
Q10. Consider a machine with 64 MB physical memory and a 32-bit virtual address space. If the
page size is 4KB, what is the approximate size of the page table?
Q11. If we execute kernel programs in the user mode and user programs in kernel mode what
are some consequences?
Q12. Differentiate between preemptive and non-preemptive scheduling. State why non-
preemptive scheduling is unlikely to be used in a computer center. In which computer systems
non-preemptive scheduling is appropriate?
Q13. Give examples of at least two applications which in your opinion are real-time applications.
Q14. What scheduling policy will you use for each of the following cases? Explain Your reasons for
choosing them.
Q15. What happens if the time allocated in a Round Robin Scheduling is very large? And what happens
if the time allocated is very low?
Q16. Assume you have the following jobs to execute with one processor, with the
0 80 0 3
1 20 10 1
2 10 10 4
3 20 80 2
4 50 85 2
a. Suppose a system uses RR scheduling with a quantum of 15, preemptive and non preemptive priority.
Create a Gantt chart illustrating the execution of these processes?
b. What is the average wait time & Turnaround time for the processes?
Q17. Define three styles of switching from user mode to supervisor mode
Q18. Explain caching and buffering. Discuss under what circumstances all of these are used?
Q19. Discuss the concept of Overlay.