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CMOS Comparator Design using 90nm Technology

Article in Engineering World · December 2024

DOI: 10.37394/232025.2024.6.31

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 Vasudeva G., Bharathi Gururaj,
Engineering World Mallikarjun P. Y., Nagaraj M Lutimath,
DOI:10.37394/232025.2024.6.31 Tripti R. Kulkarni

CMOS Comparator Design using 90nm Technology

VASUDEVA G1, BHARATHI GURURAJ 2, MALLIKARJUN P Y3,
NAGARAJ M LUTIMATH4, TRIPTI R KULKARNI5
1,5
Department of ECE, Dayananda Sagar Academy of Technology and Management, Bangalore-560082, INDIA
2
Department of ECE,KSIT, Bangalore, INDIA
3
Department of ECE, Dayananda Sagar Academy of Technology and Management, Bangalore-560082, INDIA
4
Department of CSE, Dayananda Sagar Academy of Technology and Management, Bangalore-560082, INDIA

Abstract: In many digital circuits the parameters gain and offset voltage are calculated. In our design of
CMOS comparator with high performance using GPDK 90nm technology we optimize these parameters.
The gain is calculated in AC analysis and also we measure area, delay, power dissipation, slew rate, rise
time, fall time. The circuit is built by using PMOS and NMOS transistor with a body effect and we also
measure mobility variation and channel length modulation based on the second order channel effects. A
plot of gain and offset voltage also discussed in the paper. Finally a test schematic is built and transient
analysis for an input voltage of 1.2V is measured using Cadence virtuoso.
Keywords: CMOS Comparator, Offset voltage, Gain, cadence virtuoso, slew rate
Received: April 26, 2024. Revised: October 15, 2024. Accepted: November 17, 2024. Published: December 18, 2024.

1. Introduction
In modern telecommunication systems the analog to digital conversion process, it is
low power, high speed and high performance necessary to first sample the input[10]. This
ADCs are main building blocks[1] .This ever sampled signal is then applied to a combination
growing application of portable devices make of comparators to determine the digital
the power consumption a very critical equivalent of the analog signal[11]. If the + VP,
constraint for circuit designer[2]. Comparators the input of the comparator is at a greater
are widely used in ADCs, data transmission, potential than the –VN input, the output of the
switching power regulators and many other comparator is a logic 1, where as if the + input
applications[3]. The comparator design plays is at a potential less than the – input, the output
an important role in high speed ADCs[4]. of the comparator is at logic 0.In pipeline A/D
Power consumption[5]and speed are key converter, internal comparator must amplify
metrics in comparator design. For all high speed small voltage into logic levels[12]. The Symbol
ADCs regardless of the architecture, one of the of comparator as shown in figure 1.
critical performance limiting building blocks is
the comparator, which in large measure In the proposed design pre-amplifier circuit that
determines the overall performance of data amplifies very weak signal it is considered to be
converters[6]. In conversion of analog signal to the input stage of the proposed comparator.
digital signal comparator plays very important Latch stage is used to determine which of the
role and influences the overall performance input signal is larger and amplifies their
directly[7]. In high speed ADC, speed limiting difference. Clock is used to indicate output
element is comparator[8]. The comparatoris a level; whether its differential input signal is
circuit that compares an analog signal with positive or negative[24]. In order to provide
another analog signal or reference and outputs a maximum offset voltage we provide reference
binary signal based on the comparison[9]. The voltage to the circuit. Output buffer stage is
comparator is widely used in the process of used to convert the output of the latch stage
converting analog signal to digital signals. In circuit into a logic signal[25].

E-ISSN: 2692-5079 291 Volume 6, 2024

 Vasudeva G., Bharathi Gururaj,
Engineering World Mallikarjun P. Y., Nagaraj M Lutimath,
DOI:10.37394/232025.2024.6.31 Tripti R. Kulkarni

Fig 1: Basic comparator circuit

based on the switched capacitor network using

2. Related Work a two phase nano overlapping clock. The offset
Behzad Razavi and Bruce.A.Wooley[1] voltage of the designed comparator has been
described precision techniques for the design reduced by means of an positive feedback. Here
of comparator used in high performance presented clocked comparator circuit which
Analog-Digital converters employing parallel consist of a pre amplification stage followed by
conversion stage. Here introduced a number of a positive feedback stage forming the latch[4].
comparator techniques for use in parallel Riyan Wang , Kaichang Li, Jianquin
Analog-Digital converters that are Zhang, Bin Nie presented a high speed and high
implemented in BiCMOS and CMOS VLSI resolution comparator intended to be
technologies [2]. implemented in a 12 bit 100MHz pipeline
Lauri sumanen, Mikko Walteri, Kari analog to digital converter for frequency
halonen[2] Described and proposed a new fully wireless local area network application. Here
differential CMOS dynamic comparator the designed comparator presents a rail-rail
topology suitable for pipeline A/D converters input range pre amplifier without any
with low stage resolution[14].Here proposed capacitance required [5].
topology, based on switchable current sources, Anand Mohan, Aladin Zayegh , Alex
has a small power and area dissipation. The Stojceski, and Ronny Veljanovski , Presented
main benefits of the pipeline A/D converter the design and implementation of a high speed,
architecture are its capability to a high low power CMOS comparator as part of an ultra
resolution and very high bandwidth with low fast reconfigurable flash analog to digital
power consumption in a small area [2]. converter for a direct sequence, spread
R.Lotfi, M.Taherzadev-sami, M.Yaser spectrum based ultra wide band radio receiver.
Azizi and O.Shoaei,[3] describe a 1-V fully Here Ultra means of communication has been
differential low power MOSFET only around for decades [6].
comparator with rail-to-rail input swing is
presented which can be suitably used in very
3. Design and Analysis
low voltage, low power pipelined A/D In the pre-amplifier stage input voltage
converters. This comparator utilizes a resistive Vin=1.2 V we get an amplified output also we
divider configuration with a MOSFET only include transconductance gm in the circuit[13].
clock booster to supply a higher voltage for the In the preamplifier stage Idc=10µA because of
dynamic latch in theintervals that a comparison drain saturation current the preamplifier works
is to be made . in saturation region, where Vds= β/2 (Vgs-
M. B.Gnermaz, Vt)[14]. By using a clock and providing offset
L.Bouzerara.A.Slimane, M.T.Belaroussi, voltage from the clock the output of the
B.Lehoudj and R.Zirmi[4]describes and preamplifier stage compares both input
analyzes a low power and high speed voltages Vin+ and Vin- and produce an output
differential comparator. This comparator is same as Vin+ - Vin-[15]. The substrate terminal
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E-ISSN: 2692-5079 292 Volume 6, 2024
 Vasudeva G., Bharathi Gururaj,
Engineering World Mallikarjun P. Y., Nagaraj M Lutimath,
DOI:10.37394/232025.2024.6.31 Tripti R. Kulkarni

of PMOS connected to Vdd[16] and substrate [17] to the NMOS transistor and result in an
terminal of NMOS are connected to the output voltage which is the difference between
ground. Vin+ =1.2 V provides an input voltage
Vin-. The preamplifier circuit also acts as a current mirror circuit two PMOS and 2 NMOS
transistor we use a clock circuit to provide a dc offset voltage[18].

Fig 2 Schematic diagram of CMOS comparator

the preamplifier stage which reduces the noise
In the latch circuit the PMOS and
from the signal[20].
NMOS circuits are connected in antiparallel
In the output buffer stage[21] we supply
which found a common source stage usually in
clock frequency of 100MHz which reduces the
the latch circuit the output of the preamplifier is
offset voltage in terms of milli volts. The power
taken[16] as the input for two PMOS transistor
dissipation which includes static and dynamic
when clock is high the comparator starts to
power[22] dissipation are calculated from the
work during this operation the commonsource
output buffer stage[23]. Finally an amplified
stage produces the transconductance gm
output is obtained from the output buffer stage
[17]which approximately equal to 1/β. The gate
which is free of noise variations.
of the NMOS transistor are connected to the
We also calculate slew rate, area, power
drain of the PMOS transistor which reduces the
dissipation, delay, rise time, fall time, offset
second order effects[18] such as channel length
voltage andgain of the comparator.
modulation, body effect, and mobility variation
also in this stage the feedback[19] is given to
4. Result and Discussions
is discussed below.
From the proposed design of high
The transient analysis for CMOS comparator is
speed CMOS comparator, designed using
obtained and the input voltage Vin=1.2V is
cadence virtuso with GPDK 90nm technology
given below
335
E-ISSN: 2692-5079 293 Volume 6, 2024
 Vasudeva G., Bharathi Gururaj,
Engineering World Mallikarjun P. Y., Nagaraj M Lutimath,
DOI:10.37394/232025.2024.6.31 Tripti R. Kulkarni

Fig 3: Transient Analysis of CMOS comparator with Vin=1.2V

Fig 4: Offset voltage of a comparator

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E-ISSN: 2692-5079 294 Volume 6, 2024
 Vasudeva G., Bharathi Gururaj,
Engineering World Mallikarjun P. Y., Nagaraj M Lutimath,
DOI:10.37394/232025.2024.6.31 Tripti R. Kulkarni

Fig 5 : Gain of the comparator

Next we consider the design of slew rate, rise time, fall time, power dissipation, delay, gain
,offset voltage, and area calculations in the below table

Parameter Value

Power supply 1.2v

Power dissipation 360 µW

Offset voltage 240 mV

Delay 292.3 µsec

Rise time 2.727 µsec

Fall time 2.727 µsec

Slew rate 363.7 kV/Sec

Area 180fsqm

Technology 90nm

Clock frequency 100MHz

Gain 53.98dB

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 Vasudeva G., Bharathi Gururaj,
Engineering World Mallikarjun P. Y., Nagaraj M Lutimath,
DOI:10.37394/232025.2024.6.31 Tripti R. Kulkarni

produced a low offset voltage and low power

5. Conclusion dissipation.
In this work we proposed a high
6. Future Scope
performance CMOS comparator with low
offset voltage with high gain. The CMOS The main scope of future work in
comparator will work in 90nm technology and CMOS comparator is that we have to reduce the
results are discussed. The proposed CMOS circuit area which is one of the important
comparator will operate at a power supply of constraints in any VLSI design. The comparator
1.2V with offset voltage 192mV and power converts analog signal to digital signal with a
dissipation 1.2mW also we have carried out an high sampling frequency. In future both area
output buffer stage for CMOS comparator in and time should be reduced so that an external
this stage the glitches present in the circuit are circuit can be built which should reduce the
reduced. The objective has been achieved that both constraints.
is the proposed design of CMOS comparator as
in IEEE Electron Device Letters, vol. 8, no. 9, pp.
References
410-412, Sept. 1987, doi:
[1] Behzad Razavi and Bruce.A.Wooley
10.1109/EDL.1987.26677.
“Design Techniques for High speed, High
[10] Vahid Baghi Rahin, Amir Baghi Rahin. A
resolution comparators “, IEEE Journal of solid
Low-Voltage and Low-Power Two-Stage
state circuit. vol 27, No 12, Dec 2018.
Operational Amplifier Using FinFET Transistors,
[2] Lauri sumanen , Mikko Walteri , kari
International Academic Journal of Science and
halonen “A mismatch insensitive CMOS dynamic
Engineering, Vol. 3, No. 4, 2016, pp. 80-95.
Comparator for pipeline A/D converter” , IEEE
[11] C. Enz and C. G. Temes, Circuit techniques
2020.
for reducing the effects of op-amp imperfections:
[3] R.Lotfi, M.Taherzadev-sami, M.Yaser
autozeroing, correlated double sampling, and
Azizi and O.Shoaei , “A 1-V MOSFET-only fully
chopper stabilization, Proceedings of the IEEE,
differential dynamic comparator for use in low
vol. 84(11), pp. 1584 1614, 1996.
voltage pipelined A/D converter ”, IEEE 2021.
[12] P. de Jong and G. Meijer, Absolute Voltage
[4] Fernando Paixao Corters, Eric Fabris ,
Amplication Using Dynamic Feedback Control,
Sergio Bampi, “Analysis and design of amplifiers
IEEE Transactions on Instrumentation and
and comparators in CMOS 0.35µm Technology ”,
Measurement, vol. 46(4), pp. 758763, 1997.
Microrol 2023
[13] R. Wu, J. Huijsing, and K. Makinwa, A
[5] Carsten Wulff and Trond Ytternal “0.8V 1
Current-Feedback Instrumentation Amplier with a
GHz dynamic comparator in digital 90nm CMOS
Gain Error Reduction Loop and 0.06Gain Error,
technology” , NUST, N- 7491 IEEE 2023
IEEE Journal of Solid State Circuits, vol. 46(12),
[6] M. B.Gnermaz, L.Bouzerara.A.Slimane,
pp. 27942806, 2011.
M.T.Belaroussi, B.Lehoudj and R.Zirmi, “High
[14] S. Kashmiri, S. Xia, and K. Makinwa, A
speed low power CMOS Comparator for Pipeline
Temperature-to-Digital Converter based on an
ADC’s”, IEEE 2022.
Optimized Electrothermal Filter, IEEE Journal of
[7] Anand Mohan , Aladin Zayegh , Alex
Solid-State Circuits, vol. 44(7), pp. 20262035,
Stojceski, and Ronny Veljanovski , “Comparator
2009.
for High speed low power ultra wideband A/D
[15] J. Huijsing, Operational Ampliers: Theory
converter ” ICCCP 07, IEEE 2017.
and Design. Kluwer Academic, 2001.
[8] C. Jakobson, I. Bloomand Y. Nemirovsky,
[16] Q. Fan, J. Huijsing, and K. Makinwa, A 21
Solid - State Electron. 42, 10, 1807(1998).
nV/√ Hz Chopper-Stabilized Multi-Path Current-
[9] Balestra, S. Cristoloveanu, M. Benachir, J.
Feedback Instrumentation Amplier With 2 µV O-
Brini and T. Elewa, "Double-gate silicon-
set, IEEE Journal of SolidState Circuits, vol.
oninsulator transistor with volume inversion: A
47(2), pp. 464475, 2012.
new device with greatly enhanced performance,"

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E-ISSN: 2692-5079 296 Volume 6, 2024
 Vasudeva G., Bharathi Gururaj,
Engineering World Mallikarjun P. Y., Nagaraj M Lutimath,
DOI:10.37394/232025.2024.6.31 Tripti R. Kulkarni

[17] M. Pertijs and W. Kindt, A 140-dB-CMRR Contribution of Individual Authors to the

Current-Feedback Instrumentation Amplier Creation of a Scientific Article (Ghostwriting
Employing Ping-Pong Auto-Zeroing and Policy)
Chopping, IEEE Journal of Solid-State Circuits, The authors equally contributed in the present
vol. 45(10), pp. 20442056, 2010. research, at all stages from the formulation of the
[18] S. Sakunia, F. Witte, M. Pertijs, and K. problem to the final findings and solution.
Makinwa, A Ping-Pong-Pang CurrentFeedback
Sources of Funding for Research Presented in a
Instrumentation Amplier with 0.04 Error, in
Scientific Article or Scientific Article Itself
Symposium on VLSI Circuits, Digest of Technical No funding was received for conducting this study.
Papers, 2011. Scale Integr. (VLSI) Syst. 2022, 30,
1739– 1747. Conflict of Interest
[19] Vasudeva G. and B. V. Uma. “22nm FINFET The authors have no conflicts of interest to declare
Based High Gain Wide Band Differential that are relevant to the content of this article.
Amplifier.” International Journal of Circuits,
Systems and Signal Processing (2021): n. pp.55- Creative Commons Attribution License 4.0
(Attribution 4.0 International, CC BY 4.0)
62.
This article is published under the terms of the
[20] Vasudeva G., Uma B. V., "Low Voltage Low Creative Commons Attribution License 4.0
Power and High Speed OPAMP Design using https://creativecommons.org/licenses/by/4.0/deed.en
High-K FinFET Device," WSEAS Transactions _US
on Circuits and Systems, vol. 20, pp. 80-87, 2021
[21] Vasudeva G, Uma B V, “Operational
transconductance amplifier-based comparator for
high frequency applications using 22 nm FinFET
technology”, International Journal of Electrical
and Computer Engineering (IJECE), vol. 12, no. 2,
ISSN: 2088-8708, DOI: 10.11591/ijece.v12i2, pp.
2158-2168, April 2022
[22] Vasudeva G, Uma B. V., "Design and
Implementation of High Speed and Low Power
12-bit SAR ADC using 22nm FinFET," WSEAS
Transactions on Systems and Control, vol. 17, pp.
1-15, 2022
[23] Gowdagere, Vasu & Gururaj, Bharathi
& Jatkar, Mandar & Kulkarni, Tripti
& Kulkarni, Roopa. (2023). Design of
FinFET Based Op-Amp Using High-K Device 22
nm Technology 10.3233/ATDE231033.
[24] L, Srivathsava & Kulkarni, Tripti.
(2011). Novel Design of VCO with Output Peak to
Peak Control. International Journal of
Instrumentation Control and Automation. 192-
195. 10.47893/IJICA.2011.1035.

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