See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/224694473

Development of TSMC 0.25μm standard cell library

Conference Paper · April 2007

DOI: 10.1109/SECON.2007.342966 · Source: IEEE Xplore

CITATIONS READS
6 5,703

4 authors, including:

Thien van Nguyen Cheng Wei Ren

da nang University of Science and Technology Virginia Tech
11 PUBLICATIONS 152 CITATIONS 1 PUBLICATION 6 CITATIONS

SEE PROFILE SEE PROFILE

All content following this page was uploaded by Cheng Wei Ren on 21 July 2015.

The user has requested enhancement of the downloaded file.

 Development of TSMC 0.25µm Standard Cell Library
Jeannette Donan Djigbenou, Thien Van Nguyen, Cheng Wei Ren, and Dong Sam Ha
Virginia Tech VLSI for Telecommunications (VTVT) Group
Bradley Department of Electrical and Computer Engineering
Virginia Polytechnic Institute and State University
Blacksburg, VA 24061
{jddjig01, thieng71, cren, ha}@vt.edu

Abstract
Standard library cells are basic building blocks for ASIC Table 1: List of VTVT’s Representative Library
(Application-Specific Integrated Circuit) design, which Cells
improves designers’ productivity through reduced design Cell Name Description
time and debugging. In this paper, we present the Non-inverting buffer, drive
development of a CMOS standard cell library by the VTVT buf_[1,2,4]
strength 1, 2, or 4
(Virginia Tech for VLSI and Telecommunications) Lab. inv_[1,2,4] Inverter, drive strength 1, 2 or 4
and3_[1,2,4] 3-input AND gate, drive strength
Keywords: VLSI design, CAD tools, Standard cell library. 1, 2, or 4
2-input OR gate, drive strength 1,
or2_[1,2,4]
1. Introduction 2, or 4
Commercial library cells are companies’ proprietary nand4_[1,2,4] 4-input NAND gate, drive
information, and understandably, companies usually strength 1, 2, or 4
impose certain restrictions on the access and use of nor2_[1,2,4] 2 input NOR gate, drive strength 1,
their library cells. Those restrictions on commercial 2, or 4
library cells severely hamper VLSI research and xor2_[1,2] 2 input XOR gate, drive strength 1
or 2
teaching activities of academia. To address the
xnor2_[1,2] 2 input XNOR gate, drive strength
problem, the VTVT (Virginia Tech for VLSI and 1 or 2
Telecommunications) Lab of Virginia Tech has mux2_[1,2,4] 2-to-1 multiplexer, drive strength
developed a TSMC 0.25 µm CMOS standard cell 1, 2, or 4
library under the sponsorship of the National Science fulladder One-bit ripple-carry adder, drive
Foundation and distributed it to over 258 universities strength 1
worldwide [1]. invzp_[1,2,4] inverting tristate buffer, low
enabled, drive strength 1, 2, or 4
2. Features of VTVT’s Standard Cell Library ABnorC (ip1*ip2+ip3)’ drive strength 1
The VTVT’s cell library intends to support a cell- not_ab_or_c_or_d (ip1*ip2+ip3+ip4)’ drive strength
based VLSI design flow starting from a behavioral 1
description to a layout. Specifically, it supports major cd_16
clock driver, drive strength 16
tasks such as logic simulation and synthesis, place and
lp_[1,2] high active D latch, drive strength 1 or
routing (P&R), and layout versus schematic (LVS).
2
The VTVT’s cell library has been targeted and tested lrsp_[1, 2, 4] high active D latch with asynchronous
with Synopsys tools for logic simulation and low
synthesis, and with Cadence tools for P&R and dp_[1,2,4] rising edge triggered D flip
physical design. It has 84 cells including both rising-edge triggered D flip-flop
combinational and sequential cells with different drive drp_[1,2,4] with asynchronous low-active
strengths. Some of the representative cells are listed in reset
Table 1. (1, 2, or 4 drive strength)
Figure 1 through Figure 3 show cell views of 2- rising-edge triggered JK flip-flop
input AND gates with different driving strengths. with asynchronous active-low
jkrp_2
reset
and extra inverted output, drive
strength 2.
1-4244-1029-0/07/$25.00 ©2007 IEEE. 566
 rising-edge triggered D flip-flop
dtsp_1
with asynchronous active high set
input and serial scan input.

Figure 3: 2-input AND gate with driving strength 4

3. Cell Library Design

The major tasks for development of a cell library
are: layout of cells, characterization, and LEF files
Figure 1: 2-input AND gate with driving strength 1
generation. Our cells were laid out with Cadence
Virtuoso and follow MOSIS DEEP rules
(SCN5M_DEEP). TSMC 0.25 µm CMOS technology
supports 5 metal layers, but the layout of cells is
limited to only two metal layers, metal 1 and metal 2.
This constraint allows P&R tools to use the remaining
metal layers for routing. In addition to the design
rules, the layout of cells follows rules shown in Table
2, which are necessary for P&R.

Table 2: Rules for Cell Layouts

Cell Design Settings Values
Cell Height 108 λ
Cell Width Multiple of 9 λ
9 λ for metal 1 through
Metal Pitch
metal 4, 18 λ for metal 5
Metal Width 4 λ for all layers
Metal Offset 0 for all layers
Power/Ground Pins/Rails 11λ for VDD and VSS
Note: λ is 0.12 µm.
Figure 2: 2-input AND gate with driving strength 2
Characterization of cells consists of capturing key
parameters of cells such as propagation delay, rise and
fall delays, and power dissipation. It was performed
by extracting SPICE netlists from layouts and then
simulating them using a SPICE simulator, HSPICE.
The simulation results were ported into a .lib file and
compiled by Synopsys Library Compiler for logic
simulation and synthesis.

567
 A LEF file for the cell library was generated for a
P&R tool, specifically Cadence SOC Encounter. The
extraction of abstract views and the generation of a
LEF file were performed using Cadence Abstract.
Mapping files, which enable Cadence Virtuoso to
import the layouts from Cadence SOC Encounter,
were generated manually based on the Cadence SOC
Encounter mapping format.

5. Symbol Library
A symbol library allows users to view customized
cell symbols rather than generic symbols, typically
black boxes. Symbols were drawn using Cadence
Virtuoso Schematic and Symbol editing tools. Then,
symbols were exported into an EDIF file, which was
compiled into an ASCII symbol library and eventually
.sdb file using Synopsys Design Compiler, Figure 4
shows the process for generating a symbol library.

Export EDIF file from Cadence Environment

(*.edif file)

Generate ASCII Symbol Library file in Synopsys dc_shell

(*.slib)

Generate Symbol Library Database file in Synopsys dc_shell Figure 5: Design Flow Adopted by VTVT Lab
(*.sdb)
7. Summary
Figure 4: Generation of a Symbol Library We presented basic features of TSMC 0.25 µm
CMOS standard cell library developed by the VTVT
A symbol library also allows synthesized designs to lab and the design flow. We plan to develop cell
be exported back from the synthesis tools into CAD libraries for more advanced technologies such as
tools for further design verification. This process of TSMC 0.18 µm and TSMC 0.10 µm and RAM
verification is part of the design flow approach that compilers in the next two years. Finally, any
has been used by the VTVT Lab to test and use the university can obtain our cell library at no cost. For
standard cell libraries. details, refer to [1].

6. VTVT’s Design Flow Using the Standard Acknowledgement:

Cell Library This material is based upon work supported by the
The design entry is a VHDL description, which is National Science Foundation under Grant No.
simulated and then synthesized into a gate level netlist 0551652.
in verilog. The verilog netlist is imported into
Cadence ICFB as a schematic view, and Cadence References:
SOC Encounter performs P&R and generates the P&R 1. http://www.vtvt.ece.vt.edu/vlsidesign/cell.php
layout view. Finally, the layout is verified against the 2. http://www.vtvt.ece.vt.edu/vlsidesign/designFlow.
synthesized schematic. The design flow is shown in php
Figure 5. For details, refer to [2].

568

View publication stats