Lecture 04

Chapter 3 – Introduction (4/15/02) Page 3.0-1

CHAPTER 3 - CMOS MODELS

Chapter Outline
3.1 MOS Structure and Operation
3.2 Large signal MOS models suitable for hand calculations
3.3 Extensions of the large signal MOS model
3.4 Capacitances of the MOSFET
3.5 Small Signal MOS models
3.6 Temperature and noise models for MOS transistors
3.7 BJT models
3.8 SPICE level 2 model
3.9 Models for simulation of MOS circuits
3.10Extraction of a large signal model for hand calculations from the BSIM3 model
3.11Summary
Perspective

CMOS Analog CMOS

Technology Integrated Transistor and Passive
and Circuit Component
Fabrication Design Modeling

Fig.3.0-1

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Introduction (4/15/02) Page 3.0-2

Philosophy for Models Suitable for Analog Design

The model required for analog design with CMOS technology is one that leads to
understanding and insight as distinguished from accuracy.
Technology
Understanding
and Usage

Updating Model Thinking Model Updating Technology

Simple,
±10% to ±50% accuracy

Comparison of Design Decisions- Extraction of Simple

simulation with "What can I change to Model Parameters
expectations accomplish ....?" from Computer Models
Expectations
"Ballpark"
Computer Simulation

Refined and
optimized
design Fig.3.0-02

This chapter is devoted to the simple model suitable for design not using simulation.
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Introduction (4/15/02) Page 3.0-3

Categorization of Electrical Models

Time Dependence
Time Independent Time Dependent

Linear Small-signal, midband Small-signal frequency

Rin, Av, Rout response-poles and zeros
Linearity (.TF) (.AC)

Nonlinear DC operating point Large-signal transient

iD = f(vD,vG,vS,vB) response - Slew rate
(.OP) (.TRAN)

Based on the simulation capabilities of SPICE.

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 1 (4/15/02) Page 3.1-1

3.1 - MOS STRUCTURE AND OPERATION

Metal-Oxide-Semiconductor Structure
Bulk/Substrate Source Gate Drain
Thin Oxide
(10-100nm
Polysilicon 100Å-1000Å)

p+ n+ n+

p- substrate

Heavily Lightly Intrinsic Lightly Heavily Metal

Doped p Doped p Doping Doped n Doped n Fig.3.1-01

Terminals:
• Bulk - Used to make an ohmic contact to the substrate
• Gate - The gate voltage is applied in such a manner as to invert the doping of the
material directly beneath the gate to form a channel between the source and drain.
• Source - Source of the carriers flowing in the channel
• Drain - Collects the carriers flowing in the channel
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 1 (4/15/02) Page 3.1-2

Formation of the Channel for an Enhancement MOS Transistor

Subthreshold (VG<VT)
VB = 0 VS = 0 VG < VT VD = 0

Polysilicon

p+ n+ n+

p- substrate Depletion Region

Threshold (VG=VT)
VB = 0 VS = 0 VG =VT VD = 0

Polysilicon

p+ n+ n+

p- substrate Inverted Region

Strong Threshold (VG>VT)

VB = 0 VS = 0 VG >VT VD = 0

Polysilicon

p+ n+ n+

p- substrate Inverted Region

Fig.3.1-02
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 1 (4/15/02) Page 3.1-3

Transconductance Characteristics of an Enhancement NMOS FET when VDS = 0.1V

VGS≤VT:
VB = 0 VS = 0 vG =VT VD = 0.1V iD
iD
Polysilicon

p+ n+ n+

p- substrate Depletion Region 0 vGS

0 VT 2VT 3VT
VGS=2VT:
VB = 0 VS = 0 VG = 2VT VD = 0.1V iD
iD
Polysilicon

p+ n+ n+

p- substrate Inverted Region

0 vGS
0 VT 2VT 3VT
VGS=3VT:
VB = 0 VS = 0 VG = 3VT VD = 0.1V iD
Polysilicon

p+ n+ n+

p- substrate Inverted Region

0 vGS
0 VT 2VT 3VT Fig.3.1-03

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 1 (4/15/02) Page 3.1-4

Output Characteristics of the Enhancement NMOS Transistor for VGS = 2VT

VDS=0:
VB = 0 VS = 0 vG =2VT VD = 0V iD
iD
Polysilicon VGS = 2VT

p+ n+ n+

p- substrate Inverted Region

0 vDS
0 0.5VT VT
VDS=0.5VT:
VB = 0 VS = 0 VG = 2VT VD = 0.5VT iD
iD
Polysilicon VGS = 2VT

p+ n+ n+

p- substrate Channel current

0 vDS
0 0.5VT VT
VDS=VT:
VB = 0 VS = 0 VG = 2VT VD =VT iD
iD VGS = 2VT
Polysilicon

p+ n+ n+
A depletion region
p- substrate
forms between the drain and channel 0 vDS
0 0.5VT VT Fig.3.1-04

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 1 (4/15/02) Page 3.1-5

Output Characteristics of the Enhanced NMOS when vDS = 2VT

VGS=VT:
VB = 0 VS = 0 vG =VT VD = 2VT iD
iD
Polysilicon

p+ n+ n+

p- substrate VGS =VT

0 vDS
0 VT 2VT 3VT
VGS=2VT:
VB = 0 VS = 0 VG = 2VT VD = 2VT iD
iD
Polysilicon
VGS =2VT
p+ n+ n+

p- substrate
0 vDS
0 VT 2VT 3VT
VGS=3VT:
VB = 0 VS = 0 VG = 3VT VD = 2VT iD
VGS =3VT
iD
Polysilicon

p+ n+ n+
Further increase in
p- substrate
VG will cause the FET to become active 0 vDS
0 VT 2VT 3VT
Fig.3.1-05

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 1 (4/15/02) Page 3.1-6

Output Characteristics of an Enhancement NMOS Transistor

2000
VGS = 3.0

1500

VGS = 2.5
iD(µA)

1000

VGS = 2.0
500
VGS = 1.5

VGS = 1.0
0
0 1 2 3 4 5
vDS (Volts) Fig. 3.1-6
SPICE Input File:
Output Characteristics for NMOS M5 6 5 0 0 MOS1 w=5u l=1.0u
M1 6 1 0 0 MOS1 w=5u l=1.0u VGS5 5 0 3.0
VGS1 1 0 1.0 VDS 6 0 5
M2 6 2 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VGS2 2 0 1.5 +gamma=0.4 +lambda=.04 phi=.7)
M3 6 3 0 0 MOS1 w=5u l=1.0u .dc vds 0 5 .2
VGS3 3 0 2.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 6 4 0 0 MOS1 w=5u l=1.0u ID(M5)
VGS4 4 0 2.5 .end
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 1 (4/15/02) Page 3.1-7

Transconductance Characteristics of an Enhancement NMOS Transistor

6000
VDS = 5V
5000
VDS = 4V
VDS = 3V
iD(µA) 4000

3000
VDS = 2V
2000
VDS = 1V
1000

0
0 1 2 3 4 5
vGS (Volts) Fig. 3.1-7
SPICE Input File:
Transconductance Characteristics for NMOS M5 5 6 0 0 MOS1 w=5u l=1.0u
M1 1 6 0 0 MOS1 w=5u l=1.0u VDS5 5 0 5.0
VDS1 1 0 1.0 VGS 6 0 5
M2 2 6 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VDS2 2 0 2.0 +gamma=0.4 lambda=.04 phi=.7)
M3 3 6 0 0 MOS1 w=5u l=1.0u .dc vgs 0 5 .2
VDS3 3 0 3.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 4 6 0 0 MOS1 w=5u l=1.0u ID(M5)
VDS4 4 0 4.0 .probe
.end
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 2 (4/15/02) Page 3.2-1

3.2 - LARGE SIGNAL FET MODEL FOR HAND CALCULATIONS

Large Signal Model Derivation +
Derivation- vGS
-
+
iD - vDS
1.) Let the charge per unit area in the channel
inversion layer be n+ n+
v(y)
QI(y) = -Cox[vGS-v(y)-VT] (coul./cm2) p -
Source dy Drain
y
0 y y+dy L
2.) Define sheet conductivity of the inversion
Fig.110-03
layer per square as
 cm2  coulombs amps 1
σS = µoQI(y)  v·s  cm2  = volt = Ω/sq.
   

3.) Ohm's Law for current in a sheet is

iD dv -iD -iDdy
JS = W = -σSEy = -σS dy → dv = σ W dy = µoQI(y)W → iD dy = -WµoQI(y)dv
S
4.) Integrating along the channel for 0 to L gives
L vDS vDS
⌠
⌡ iDdy = - ⌠⌡WµoQI(y)dv = ⌠
⌡ WµoCox[vGS-v(y)-VT] dv
0 0 0
5.) Evaluating the limits gives
WµoCox  v2(y)vDS WµoCox  vDS2
iD = 2  0 →
 (vGS-VT)v(y) -  iD =  (v -V )v - 
L  L  GS T DS 2 
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 2 (4/15/02) Page 3.2-2

Saturation Voltage - VDS(sat) iD

Interpretation of the large vDS = vGS-VT
signal model:
Active Region Saturation Region

Increasing
values of vGS

vDS
Fig. 110-04

The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of
the inverted parabolas.
vDS
diD µoCoxW
dvDS = L [(vGS-VT) - vDS] = 0
Cutoff Saturation Active
vDS(sat) = vGS - VT

T
V
S-
vG
Useful definitions:

S=
µoCoxW K’W

vD
0 vGS
L = L =β 0 VT Fig. 3.2-4

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 2 (4/15/02) Page 3.2-3

The Simple Large Signal MOSFET Model

Regions of Operation of the MOS Transistor:
1.) Cutoff Region:
vGS - VT < 0
iD = 0
(Ignores subthreshold currents)
2.) Active Region Output Characteristics of the MOSFET:
0 < vDS < vGS - VT iD/ID0
vDS = vGS-VT
µoCoxW vGS-VT
iD = 2L 2(vGS - VT) - vDS vDS
  1.0 Active VGS0-VT
= 1.0
Region Saturation Region
vGS-VT
= 0.867
3.) Saturation Region 0.75
Channel modulation effects
VGS0-VT
vGS-VT
0 < vGS - VT < vDS VGS0-VT
= 0.707
0.5
vGS-VT
µoCoxW VGS0-VT
= 0.5
iD = 2L vGS - VT 2 0.25 vGS-VT
=0
Cutoff Region VGS0-VT
vDS
0
0 0.5 1.0 1.5 2.0 2.5 VGS0-VT
Fig. 110-05

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 2 (4/15/02) Page 3.2-6

Influence of VDS on the Output Characteristics

Channel modulation effect: VG > VT VD > VDS(sat)
As the value of vDS increases, the
effective L decreases causing the B S
current to increase. Depletion
Polysilicon Region

Illustration: p+ n+ n+

Leff
Note that Leff = L - Xd
Therefore the model in saturation p- substrate Xd
becomes, Fig110-06

K’W diD K’W dLeff iD dXd

iD = 2L (vGS-VT)2 → dv = - (vGS - VT)2 dv = ≡ λ iD
eff DS 2Leff 2 DS Leff dvDS
Therefore, a good approximation to the influence of vDS on iD is
diD K’W
iD ≈ iD(λ = 0) + dvDS vDS = iD(λ = 0)(1 + λvD) = 2L (vGS-VT)2(1+λvDS)

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 2 (4/15/02) Page 3.2-7

Channel Length Modulation Parameter, λ

Assume the MOS is transistor is saturated-
µCoxW
∴ iD = 2L (vGS - VT)2(1 + λvDS)
Define iD(0) = iD when vDS = 0V.

µCoxW
∴ iD(0) = 2L (vGS- VT)2
Now,
iD = iD(0)[1 + λvDS] = iD(0) + λiD(0) vDS
Matching with y = mx + b gives the value of λ
iD
iD3(0) VGS3
iD2(0)
iD1(0) VGS2
VGS1
vDS
-1
λ

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 2 (4/15/02) Page 3.2-8

Influence of the Bulk Voltage on the Large Signal MOSFET Model

Illustration of the influence of the bulk: VBS0 = 0V
VS = 0 VG > VT VD > 0
VSB0 = 0V: iD
Polysilicon

p+ n+ n+

p- substrate Channel current

Fig.110-07A
VSB1 > 0V
VSB1>0V: VS = 0 VG > VT VD > 0
iD
Polysilicon

p+ n+ n+

p- substrate Channel current

Fig.110-07B
VSB2 > VSB1: VSB2 >VSB1 V = 0 VG > VT VD > 0
S
iD = 0
Polysilicon

p+ n+ n+

p- substrate
Fig.110-07C
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 2 (4/15/02) Page 3.2-9

Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued
Bulk-Source (vBS) influence on the transconductance characteristics-
iD
Decreasing values
of bulk-source voltage

VBS = 0

ID

vDS ≥ vGS-VT

vGS
VT0 VT1 VT2 VT2
Fig. 110-08

In general, the simple model incorporates the bulk effect into VT by the previously
developed relationship:

VT(vBS) = VT0 + γ 2|φf| + |vBS| - γ 2|φ f|

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 2 (4/15/02) Page 3.2-10

Summary of the Simple Large Signal MOSFET Model D

N-channel reference convention: +
iD
G B
Non-saturation- +
v
+ DS
WµoCox  vDS2 vGS vBS
iD = L  (vGS - VT)vDS -
 2  (1 + λvDS) - -
S Fig. 110-10
Saturation-
WµoCox  vDS(sat)2 WµoCox 2(1+λvDS)
iD =  (vGS-VT)vDS(sat) -  (1+λvDS) = (vGS -V T)
L  2  2L
where:
µo = zero field mobility (cm2/volt·sec)
Cox = gate oxide capacitance per unit area (F/cm2)
λ = channel-length modulation parameter (volts-1)
VT = VT0 + γ 2|φf| + |vBS| - 2|φf|
VT0 = zero bias threshold voltage
γ = bulk threshold parameter (volts-0.5)
2|φf| = strong inversion surface potential (volts)
For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert
current.
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 2 (4/15/02) Page 3.2-11

Silicon Constants

Constant Constant Description Value Units

Symbol
VG Silicon bandgap (27°C) 1.205 V
k Boltzmann’s constant 1.381x10-23 J/K
ni Intrinsic carrier 1.45x1010 cm-3
concentration (27°C)
ε0 Permittivity of free space 8.854x10-14 F/cm
ε si Permittivity of silicon 11.7 ε0 F/cm
εox Permittivity of SiO2 3.9 ε0 F/cm

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 2 (4/15/02) Page 3.2-12

MOSFET Parameters
Model Parameters for a Typical CMOS Bulk Process (0.8µm CMOS n-well):

Parameter Parameter Typical Parameter Value

Symbol Description N-Channel P-Channel Units
VT0 Threshold Voltage 0.7± 0.15 -0.7 ± 0.15 V
(VBS = 0)
K' Transconductance Para- 110.0 ± 10% 50.0 ± 10% µA/V2
meter (in saturation)
γ Bulk threshold 0.4 0.57 (V)1/2
parameter
λ Channel length 0.04 (L=1 µm) 0.05 (L=1 µm) (V)-1
modulation parameter 0.01 (L=2 µm) 0.01 (L=2 µm)
2|φF| Surface potential at 0.7 0.8 V
strong inversion

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 3 (4/15/02) Page 3.3-1

3.3 - LARGE SIGNAL MODEL EXTENSIONS

TO SHORT-CHANNEL MOSFETS
Extensions
• Velocity saturation
• Weak inversion (subthreshold)
• Substrate currents
Substrate Interference
• Problems of mixed signal circuits on the same substrate
• Modeling and potential solutions

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 3 (4/15/02) Page 3.3-2

VELOCITY SATURATION
What is Velocity Saturation?
The most important short-channel
effect in MOSFETs is the velocity

Electron Drift Velocity (m/s)

105
saturation of carriers in the channel.
A plot of electron drift velocity
versus electric field is shown below. 5x104

2x104

An expression for the electron drift 104

velocity as a function of the electric
field is, 5x103
105 106 107
µnE
vd ≈ 1 + E/Ec Electric Field (V/m) Fig130-1

where
vd = electron drift velocity (m/s)
µn = low-field mobility (≈ 0.07m2/V·s)
Ec = critical electrical field at which velocity saturation occurs

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 3 (4/15/02) Page 3.3-9

Important Short Channel Effects n

1.) An approximate plot of the n as a function
of channel length is shown below where 2
iD ∝ (vGS – VT)n
1
0 L
0 1 2 3 4 5 Lmin
Fig.130-5
2.) Note that the value of λ varies with channel length, L. The data below is from a
0.25µm CMOS technology.
Channel Length Modulation (V-1)

0.6
0.5

0.4
PMOS
0.3

0.2
NMOS
0.1
0
0 0.5 1 1.5 2 2.5
Channel Length (microns) Fig.130-6

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 3 (4/15/02) Page 3.3-10

SUBTHRESHOLD MOSFET MODEL

What is Weak Inversion Operation?
Weak inversion operation occurs when the applied gate voltage is below VT and
pertains to when the surface of the substrate beneath the gate is weakly inverted.
VGS

n+ n-channel n+
Diffusion Current
p-substrate/well
Fig. 140-01

Regions of operation according to the surface potential, φS (or ψS)

φS < φF : Substrate not inverted
φ F < φ S < 2φ F : Channel is weakly inverted (diffusion current)
2φF < φS : Strong inversion (drift current)

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 3 (4/15/02) Page 3.3-11

Drift versus Diffusion Current

1.) For strong inversion, the gate voltage controls the charge in the inverted region but
not in the depletion region. The concentration of charge across the channel is
approximately constant and the current is drift caused by electric field.
2.) For weak inversion, the charge in channel is much less that that in the depletion region
and drift current decreases. However, there is a concentration gradient in the channel,
that causes diffusion current.
The n-channel MOSFET acts like a NPN BJT: the emitter is the source, the base is
the substrate and the collector is the drain.
Illustration:
log iD
Diffusion Current
Drift Current
10-6

10-12 V
0 VT Fig. 140-02 GS

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 3 (4/15/02) Page 3.3-15

Simulation of an n-channel MOSFET in both Weak and Strong Inversion

Uses the BSIM model.†

100µA

10µA
iD vGS
1µA
ID(M1)

100nA

10nA

1nA

100pA
0V 0.4V 0.8V 1.2V 1.6V 2V
VGS Fig. 140-05

†
Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User’s Guide, Kluwer Academic Publishers, Boston, 1999.
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 3 (4/15/02) Page 3.3-17

SUBSTRATE CURRENT FLOW IN MOSFETS

Impact Ionization
Impact Ionization:
Occurs because high electric fields cause an impact which generates a hole-electron
pair. The electrons flow out the drain and the holes flow into the substrate causing a
substrate current flow.
Illustration:
VG > V T
B S VD > VDS(sat)
Polysilicon
Depletion
Region
p+ n+ A
Free n+
Fixed electron
Atom
p- substrate Free
hole
Fig130-7

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 3 (4/15/02) Page 3.3-19

SUBSTRATE INTERFERENCE IN CMOS CIRCUITS

How Do Carriers Get Injected into the Substrate?
1.) Hot carriers (substrate current)
2.) Electrostatic coupling (across depletion regions and other dielectrics)
3.) Electromagnetic coupling (parallel conductors)

Why is this a Problem?

With decreasing channel lengths, more circuitry is being integrated on the same
substrate. The result is that noisy circuits (circuits with rapid transitions) are beginning
to adversely influence sensitive circuits (such as analog circuits).

Present Solution
Keep circuit separate by using multiple substrates and put the multiple substrates in the
same package.

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 3 (4/15/02) Page 3.3-20

Hot Carrier Injection in CMOS Technology without an Epitaxial Region

Noisy Circuits Quiet Circuits
VDD
VDD(Analog)

RL Substrate Noise
vin vout vout
VGS vin

vin VDD(Analog)

vin vout RL
VDD(Digital) VGS
Digital Ground
n+ channel vout Analog Ground
stop (1 Ω-cm)
p+ n+ n+ p+ p+ n+ n+ n+ p+
p+ channel stop (1Ω-cm)
n- well "AC ground"
Hot Back-gating due to a
iD
Carrier momentary change in
Put substrate connections reverse bias
as close to the noise source
as possible ∆iD
ID
"AC ground" ∆iD

vGS
p- substrate (10 Ω-cm) VGS

Heavily Lightly Intrinsic Lightly Heavily Metal Fig. SI-01

Doped p Doped p Doping Doped n Doped n

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 3 (4/15/02) Page 3.3-21

Hot Carrier Injection in CMOS Technology with an Epitaxial Region

Noisy Circuits Quiet Circuits
VDD
VDD(Analog)

RL Substrate Noise
vin vout vout
VGS vin

vin VDD(Analog)

vin vout RL
VDD(Digital) VGS
Digital Ground vout Analog Ground

p+ n+ n+ p+ p+ n+ n+ n+ p+
n- well "AC ground" p-epitaxial Reduced back
Put substrate Hot layer (15 Ω-cm) gating due to
connections Carrier smaller resistance
as close to the
noise source
as possible
"AC ground"

p+ substrate (0.05 Ω-cm)

Heavily Lightly Intrinsic Lightly Heavily Metal Fig. SI-02

Doped p Doped p Doping Doped n Doped n

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 3 (4/15/02) Page 3.3-22

Computer Model for Substrate Interference Using SPICE Primitives

Noise Injection Model:
VDD

VDD
vin vout
L1
Cs1
n- well
Digital Ground VDD(Digital)
vin vout
Cs3 Cs2
vin vout Rs1 Substrate
Rs2
Rs3
p+ n+ n+ p+ p+ n+
n- well Cs4
Hot Cs5
Carrier Coupling
Hot
L2 L3
Carrier Coupling
Coupling

Cs1 = Capacitance between n-well and substrate

Cs2,Cs3 and Cs4 = Capacitances between interconnect lines
(including bond pads) and substrate
Cs5 = All capacitance between the substrate and ac ground
p- substrate
Rs1,Rs2 and Rs3 = Bulk resistances in n-well and substrate
L1,L2 and L3 = Inductance of the bond wires and package leads
Heavily Lightly Intrinsic Lightly Heavily Metal
Doped p Doped p Doping Doped n Doped n
Fig. SI-06

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 3 (4/15/02) Page 3.3-23

Computer Model for Substrate Interference Using SPICE Primitives

Noise Detection Model:
VDD(Analog)

RL Substrate Noise
vin vout
VGS VDD
VDD(Analog)
vin RL RL
vout
vout
VGS Analog Ground L4 CL
L6
n+ n+ p+
VGS
Cs6 Rs4 Cs7
Substrate

Cs5
L5

Cs5,Cs6 and Cs7 = Capacitances between interconnect lines

(including bond pads) and substrate
p- substrate Rs4 = Bulk resistance in the substrate
L4,L5 and L6 = Inductance of the bond wires and package leads
Heavily Lightly Intrinsic Lightly Heavily Metal Fig. SI-07
Doped p Doped p Doping Doped n Doped n

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 3 (4/15/02) Page 3.3-24

Other Sources of Substrate Injection

(We do it to ourselves and can’t blame the digital circuits.)

Inductor
Substrate BJT

Collector Base Emitter Collector

n+ p+ n+ n+
p- well

Fig. SI-04
Heavily Lightly Intrinsic Lightly Heavily Metal
Doped p Doped p Doping Doped n Doped n

Also, there is coupling from power supplies and clock lines to other adjacent signal lines.

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 3 (4/15/02) Page 3.3-25

What is a Good Ground?

• On-chip, it is a region with very low bulk resistance.
It is best accomplished by connecting metal to the region at as many points as
possible.
• Off-chip, it is all determined by the connections or
20
bond wires.
16 Settling Time to within 0.5mV (ns)
The inductance of the bond wires is large enough
to create significant ground potential changes for 12
fast current transients. 8
Peak-to-Peak Noise (mV)
di
v = L dt 4

0
Use multiple bonding wires to reduce the ground 0 1 2 3 4 5 6 7 8
noise caused by inductance. Number of Substrate Contact Package Pins
Fig. SI-08

• Fast changing signals have part of C2

their path (circuit through ground
and power supplies. Therefore t=0
bypass the off-chip power supplies " VDD
to ground as close to the chip as Vout
Vin C1 !
possible.
VSS

CMOS Analog Circuit Design © P.E. Allen - 2002

Fig. SI-05
Chapter 3 – Section 3 (4/15/02) Page 3.3-26

Summary of Substrate Interference

• Methods to reduce substrate noise
1.) Physical separation
2.) Guard rings placed close to the sensitive circuits with dedicated package pins.
3.) Reduce the inductance in power supply and ground leads (best method)
4.) Connect regions of constant potential (wells and substrate) to metal with as
many contacts as possible.
• Noise Insensitive Circuit Design Techniques
1.) Design for a high power supply rejection ratio (PSRR)
2.) Use multiple devices spatially distinct and average the signal and noise.
3.) Use “quiet” digital logic (power supply current remains constant)
4.) Use differential signal processing techniques.
• Some references
1.) D.K. Su, M.J. Loinaz, S. Masui and B.A. Wooley, “Experimental Results and Modeling Techniques for
Substrate Noise in Mixed-Signal IC’s,” J. of Solid-State Circuits, vol. 28, No. 4, April 1993, pp. 420-430.
2.) K.M. Fukuda, T. Anbo, T. Tsukada, T. Matsuura and M. Hotta, “Voltage-Comparator-Based
Measurement of Equivalently Sampled Substrate Noise Waveforms in Mixed-Signal ICs,” J. of Solid-State
Circuits, vol. 31, No. 5, May 1996, pp. 726-731.
3.) X. Aragones, J. Gonzalez and A. Rubio, Analysis and Solutions for Switching Noise Coupling in Mixed-
Signal ICs, Kluwer Acadmic Publishers, Boston, MA, 1999.

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 4 (4/15/02) Page 3.4-1

3.4 - CAPACITANCES OF THE MOSFET

Types of Capacitance
Physical Picture:

SiO2

Gate
Source Drain
C1 C2 C3
FOX FOX
C4
CBS CBD
Bulk
Fig120-06

MOSFET capacitors consist of:

• Depletion capacitances
• Charge storage or parallel plate capacitances

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 4 (4/15/02) Page 3.4-3

Charge Storage (Parallel Plate) MOSFET Capacitances - C1, C2, C3 and C4

Mask L Oxide encroachment

Overlap capacitances:
Actual C1 = C3 = LD·Weff·Cox = CGSO or CGDO
Actual
L (Leff) Mask
W (Weff) (LD ≈ 0.015 µm for LDD structures)
LD W

Gate Channel capacitances:

Drain-gate overlap
C2 = gate-to-channel = CoxWeff·(L-2LD) =
Source-gate overlap
capacitance CGS (C1) capacitance CGD (C3) CoxWeff·Leff
Gate C4 = voltage dependent channel-
FOX FOX
Source Drain bulk/substrate capacitance
Gate-Channel Channel-Bulk
Bulk
Capacitance (C2) Capacitance (C4)
Fig. 120-09

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 4 (4/15/02) Page 3.4-4

Charge Storage (Parallel Plate) MOSFET Capacitances - C5

View looking down the channel from source to drain
Overlap Overlap

Gate
FOX C5 Source/Drain C5 FOX

Bulk
Fig120-10
C5 = CGBO
Capacitance values based on an oxide thickness of 140 Å or Cox=24.7 × 10-4 F/m2:
Type P-Channel N-Channel Units
CGSO 220 ×10-12 220 × 10-12 F/m
CGDO 220 × 10-12 220 × 10-12 F/m
CGBO 700 × 10-12 700 × 10-12 F/m
CJ 560 × 10-6 770 × 10-6 F/m2
CJSW 350 × 10-12 380 × 10-12 F/m
MJ 0.5 0.5
MJSW 0.35 0.38
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 4 (4/15/02) Page 3.4-6

Illustration of CGD, CGS and CGB

Comments on the variation of CBG in the cutoff region:
1
CBG = 1 1 + 2C5 Capacitance
C2 + C4 C4 Large
1.) For vGS ≈ 0, CGB ≈ C2 + 2C5 C2 + 2C5
CGS
(C4 is large because of the thin C1+ 0.67C2
CGS, CGD
C1+ 0.5C2
inversion layer in weak inversion
vDS = constant
where VGS is slightly less than VT)) CGS, CGD CGD vBS = 0
C1, C3 C4 Small
CGB
2.) For 0 < vGS ≤ VT, CGB ≈ 2C5 2C5
0 vGS
(C4 is small because of the thicker Off Saturation Non-
inversion layer in strong inversion) Saturation
VT vDS +VT Fig120-12

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 6 (4/15/02) Page 3.6-1

3.6 - TEMPERATURE AND NOISE MODELS FOR THE MOSFET

Large Signal Temperature Model
Transconductance parameter:
K’(T) = K’(T0) (T/T0)-1.5 (Exponent becomes +1.5 below 77°K)
Threshold Voltage:
VT(T) = VT(T0) + α(T-T0) + ···
Typically αNMOS = -2mV/°C to –3mV/°C from 200°K to 400°K (PMOS has a + sign)
Example
Find the value of ID for a NMOS transistor at 27°C and 100°C if VGS = 2V and W/L =
5µm/1µm if K’(T0) = 110µA/V2 and VT(T0) = 0.7V and T0 = 27°C and αNMOS = -2mV/°C.
Solution
At room temperature, the value of drain current is,
110µA/V2·5µm 2 = 465µA
ID(27°C) = 2·1µm (2-0.7)
-1.5
At T = 100°C (373°K), K’(100°C)=K’(27°C) (373/300) =110µA/V2·0.72=79.3µA/V2
and VT(100°C) = 0.7 – (.002)(73°C) = 0.554V
79.3µA/V2·5µm
∴ ID(100°C) = 2·1µm (2-0.554) 2 = 415µA (Repeat with VGS = 1.5V)

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 6 (4/15/02) Page 3.6-2

Experimental Verification of the MOSFET Temperature Dependence

NMOS Threshold:
1.6

1.4

1.2

VT(V) 0.8

0.6
Theory
0.4 matched
at 25°C
0.2

0
0 50 100 150 200 250 300
Temperature (°C) Fig. 3.6-1

Symbol Min. L NA (cm-3) ° )

tox (A α (mV/°C)
O 6µm 2x1016 1000 -3.5
❑ 5µm 1x1016 650 -2.5
∆ 4µm 2x1016 500 -2.3
∇ 2µm 3.3x1016 275 -1.8
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 6 (4/15/02) Page 3.6-3

Experimental Verification of the MOSFET Temperature Dependence

PMOS Threshold:
1.6

1.4

1.2

1
VT(V) 0.8

0.6
Theory
0.4 matched
at 25°C
0.2

0
0 50 100 150 200 250 300
Temperature (°C) Fig. 3.6-2

Symbol Min. L NA (cm-3) ° )

Tox (A α (mV/°C)
O 6µm 2x1015 1000 +3.5
❑ 5µm 2x1015 650 +2.5
∆ 4µm 2x1016 500 +2.3
∇ 2µm 1.1x1016 275 +2.0
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 6 (4/15/02) Page 3.6-6

Zero Temperature Coefficient (ZTC) Point for MOSFETs

For a given value of gate-source voltage, the drain current of the MOSFET will be
independent of temperature. Consider the following circuit:
Assume that the transistor is saturated and that:
ID
T 
µ = µoTo-1.5 and VT(T) = VT(To) + α(T-To)
  VGS
where α = -0.0023V/°C and To = 27°C Fig. 4.5-12
µoCoxW  T -1.5
∴ ID(T) = 2L T  [VGS – VT0 - α(T-To)]2
 o
dID -1.5µoCox  T -2.5 T 
  -1.5
dT = 2To T  [V GS -V T0 - α (T-T o )] 2 + αµ o C oxT  [V GS -V T0 - α (T-T o )] = 0
 o  o

-4Tα αΤ
∴ VGS – VT0 - α(T-To) = 3 ⇒ VGS(ZTC) = VT0 - αTo - 3

Let K’ = 10µA/V2, W/L = 5 and VT0 = 0.71V.

At T=27°C (300°K), VGS(ZTC)=0.71-(-0.0023)(300°K)-(0.333)(-0.0023)(300°K) = 1.63V
At T = 27°C (300°K), ID = (10µA/V2)(5/2)(1.63-0.71)2 = 21.2µA
At T=200°C (473°K), VGS(ZTC)=0.71-(-0.0023)(300°K)-(0.333)(-0.0023)(473°K)=1.76V
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 6 (4/15/02) Page 3.6-7

Experimental Verification of the ZTC Point

The data below is for a 5µm n-channel MOSFET with W/L=50µm/10µm, NA=1016 cm-3,
tox = 650Å, uoCox = 10µA/V2, and VT0 = 0.71V.

25°C
100 100°C
VDS = 6V 150°C
200°C
80 250°C
275°C

60
ID (µA)

300°C

40
150°C
275°C 250°C 200°C
Zero TC Point
20 25°C
100°C

0
0 0.6 1.2 1.8 2.4 3
VGS (V) Fig. 3.6-065

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 6 (4/15/02) Page 3.6-8

ZTC Point for PMOS

The data is for a 5µm p-channel MOSFET with W/L=50µm/10µm, ND=2x10-15cm-3, and
tox = 650Å.

25°C
300°C 100°C

40
VDS = -6V

30 150°C
ID (µA)

20
275°C
VSG(ZTC) ≈ -1.95V
10
150°C
250°C
100°C
25°C
0
0 -0.6 -1.2 -1.8 -2.4 -3.0
VGS (V) Fig. 3.6-066

Zero temperature coefficient will occur for every MOSFET up to about 200°C.
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 6 (4/15/02) Page 3.6-14

MOSFET NOISE
MOS Device Noise at Low Frequencies
D D
D
eN2
G B G in2 G * B

Noise Noise
S B Free
Free S
MOSFET MOSFET S
where
8kTgm(1+η) KF ID 


in2 = 
 3 + fSCoxL2 ∆f (amperes2)
∆f = bandwidth at a frequency, f
gmbs
η = gm
k = Boltzmann’s constant
KF = Flicker noise coefficient
S = Slope factor of the 1/f noise
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 6 (4/15/02) Page 3.6-15

Reflecting the MOSFET Noise to the Gate

Dividing in2 by gm2 gives
in2  8kT(1+η) KF 
 
en = g 2 =  3g
2 + 2fC WL K’ ∆f (volts2)
m  m ox 

KF
It will be convenient to use B = 2CoxK’ for model simplification.

in2

1/f noise Thermal noise

log10(f)

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 9 (4/15/02) Page 3.9-1

SEC. 3.9 – MODELS FOR SIMULATION OF MOS CIRCUITS

FET Model Generations
• First Generation – Physically based analytical model including all geometry
dependence.
• Second Generation – Model equations became subject to mathematical conditioning for
circuit simulation. Use of empirical relationships and parameter extraction.
• Third Generation – A return to simpler model structure with reduced number of
parameters which are physically based rather than empirical. Uses better methods of
mathematical conditioning for simulation including more specialized smoothing
functions.
Performance Comparison of Models (from Cheng and Hu, MOSFET Modeling & BSIM3
Users Guide)
Model Minimum Minimum Model iD Accuracy in iD Accuracy in Small signal Scalability
L (µm) Tox (nm) Continuity Strong Inversion Subthreshold parameter
MOS1 5 50 Poor Poor Not Modeled Poor Poor
MOS2 2 25 Poor Poor Poor Poor Fair
MOS3 1 20 Poor Fair Poor Poor Poor
BSIM1 0.8 15 Fair Good Fair Poor Fair
BSIM2 0.35 7.5 Fair Good Good Fair Fair
BSIM3v2 0.25 5 Fair Good Good Good Good
BSIM3v3 0.15 4 Good Good Good Good Good
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 9 (4/15/02) Page 3.9-2

First Generation Models

Level 1 (MOS1)
• Basic square law model based on the gradual channel approximation and the square law
for saturated drain current.
• Good for hand analysis.
• Needs improvement for deep-submicron technology (must incorporate the square law to
linear shift)
Level 2 (MOS2)
• First attempt to include small geometry effects
• Inclusion of the channel-bulk depletion charge results in the familiar 3/2 power terms
• Introduced a simple subthreshold model which was not continuous with the strong
inversion model.
• Model became quite complicated and probably is best known as a “developing ground”
for better modeling techniques.
Level 3 (MOS3)
• Used to overcome the limitations of Level 2. Made use of a semi-empirical approach.
• Added DIBL and the reduction of mobility by the lateral field.
• Similar to Level 2 but considerably more efficient.
• Used binning but was poorly implemented.
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 9 (4/15/02) Page 3.9-3

Second Generation Models

BSIM (Berkeley Short-Channel IGFET Model)
• Emphasis is on mathematical conditioning for circuit simulation
• Short channel models are mostly empirical and shifts the modeling to the parameter
extraction capability
• Introduced a more detailed subthreshold current model with good continuity
• Poor modeling of channel conductance
HSPICE Level 28
• Based on BSIM but has been extensively modified.
• More suitable for analog circuit design
• Uses model binning
• Model parameter set is almost entirely empirical
• User is locked into HSPICE
• Model is proprietary
BSIM2
• Closely based on BSIM
• Employs several expressions developed from two dimensional analysis
• Makes extensive modifications to the BSIM model for mobility and the drain current
• Uses a new subthreshold model
• Output conductance model makes the model very suitable for analog circuit design
• The drain current model is more accurate and provides better convergence
• Becomes more complex with a large number of parameters
• No provisions for variations in the operating temperature
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 9 (4/15/02) Page 3.9-4

Third Generation Models

BSIM3
• This model has achieved stability and is being widely used in industry for deep
submicron technology.
• Initial focus of simplicity was not realized.
MOS Model 9
• Developed at Philips Laboratory
• Has extensive heritage of industrial use
• Model equations are clean and simple – should be efficient
Other Candidates
• EKV (Enz-Krummenacher-Vittoz) – fresh approach well suited to the needs of analog
circuit design

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 9 (4/15/02) Page 3.9-8

BSIM2 Model used in Subthreshold

BSIM Model Parameters used in Subthreshold
VDS 1 0 DC 3.0
M1 1 1 0 0 CMOSN W=5UM L=2UM
.MODEL CMOSN NMOS LEVEL=4
+VFB=-7.92628E-01 LVFB= 1.22972E-02 WVFB=-1.00233E-01
+PHI= 7.59099E-01 LPHI= 0.00000E+00 WPHI= 0.00000E+00
+K1= 1.06705E+00 LK1= 5.08430E-02 WK1= 4.72787E-01
+K2=-4.23365E-03 LK2= 6.76974E-02 WK2= 6.27415E-02
+ETA=-4.30579E-03 LETA= 9.05179E-03 WETA= 7.33154E-03
+MUZ= 5.58459E+02 DL=6.86137E-001 DW=-1.04701E-001
+U0= 5.52698E-02 LU0= 6.09430E-02 WU0=-6.91423E-02
+U1= 5.38133E-03 LU1= 5.43387E-01 WU1=-8.63357E-02
+X2MZ= 1.45214E+01 LX2MZ=-3.08694E+01 WX2MZ= 4.75033E+01
+X2E=-1.67104E-04 LX2E=-4.75323E-03 WX2E=-2.74841E-03
+X3E= 5.33407E-04 LX3E=-4.69455E-04 WX3E=-5.26199E-03
+X2U0= 2.45645E-03 LX2U0=-1.46188E-02 WX2U0= 2.63555E-02
+X2U1=-3.80979E-04 LX2U1=-1.71488E-03 WX2U1= 2.23520E-02
+MUS= 5.48735E+02 LMUS= 3.28720E+02 WMUS= 1.35360E+02
+X2MS= 6.72261E+00 LX2MS=-3.48094E+01 WX2MS= 9.84809E+01
+X3MS=-2.79427E+00 LX3MS= 6.31555E+01 WX3MS=-1.99720E-01
+X3U1= 1.18671E-03 LX3U1= 6.13936E-02 WX3U1=-3.49351E-03
+TOX=4.03000E-002 TEMP= 2.70000E+01 VDD= 5.00000E+00
+CGDO=4.40942E-010 CGSO=4.40942E-010 CGBO=6.34142E-010
+XPART=-1.00000E+000
+N0=1.00000E+000 LN0=0.00000E+000 WN0=0.00000E+000
+NB=0.00000E+000 LNB=0.00000E+000 WNB=0.00000E+000
+ND=0.00000E+000 LND=0.00000E+000 WND=0.00000E+000
+RSH=0 CJ=4.141500e-04 CJSW=4.617400e-10 JS=0 PB=0.8
+PBSW=0.8 MJ=0.4726 MJSW=0.3597 WDF=0 DELL=0
.DC VDS 5.0 0 0.01
.PRINT DC ID(M1)
.PROBE
.END
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 9 (4/15/02) Page 3.9-10

BSIM3 Model
The background for the BSIM3 model and the equations are given in detail in the text
MOSFET Modeling & BSIM3 User’s Guide, by Y. Cheng and C. Hu, Kluwer Academic
Publishers, 1999.
The short channel effects included in the BSIM3 model are:
• Normal and reverse short-channel and narrow-width effects on the threshold.
• Channel length modulation (CLM).
• Drain induced barrier lowering (DIBL).
• Velocity saturation.
• Mobility degradation due to the vertical electric field.
• Impact ionization.
• Band-to-band tunnelling.
• Velocity overshoot.
• Self-heating.
1.) Channel quantiztion.
2.) Polysilicon depletion.

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 9 (4/15/02) Page 3.9-13

0.25µm BSIM3v3.1 NMOS Parameters

.MODEL CMOSN NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.7E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.4273342
+K1 = 0.3922983 K2 = 0.0185825 K3 = 1E-3
+K3B = 2.0947677 W0 = 2.171779E-7 NLX = 1.919758E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 7.137212E-3 DVT1 = 6.066487E-3 DVT2 = -0.3025397
+U0 = 403.1776038 UA = -3.60743E-12 UB = 1.323051E-18
+UC = 2.575123E-11 VSAT = 1.616298E5 A0 = 1.4626549
+AGS = 0.3136349 B0 = 3.080869E-8 B1 = -1E-7
+KETA = 5.462411E-3 A1 = 4.653219E-4 A2 = 0.6191129
+RDSW = 345.624986 PRWG = 0.3183394 PRWB = -0.1441065
+WR =1 WINT = 8.107812E-9 LINT = 3.375523E-9
+XL = 3E-8 XW =0 DWG = 6.420502E-10
+DWB = 1.042094E-8 VOFF = -0.1083577 NFACTOR = 1.1884386
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 4.914545E-3 ETAB = 4.215338E-4
+DSUB = 0.0313287 PCLM = 1.2088426 PDIBLC1 = 0.7240447
+PDIBLC2 = 5.120303E-3 PDIBLCB = -0.0443076 DROUT = 0.7752992
+PSCBE1 = 4.451333E8 PSCBE2 = 5E-10 PVAG = 0.2068286
+DELTA = 0.01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL =0
+WLN = 1 WW = -1.22182E-16 WWN = 1.2127
+WWL = 0 LL =0 LLN = 1
+LW =0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 6.33E-10
+CGSO = 6.33E-10 CGBO = 1E-11 CJ = 1.766171E-3
+PB = 0.9577677 MJ = 0.4579102 CJSW = 3.931544E-10
+PBSW = 0.99 MJSW = 0.2722644 CF =0
+PVTH0 = -2.126483E-3 PRDSW = -24.2435379 PK2 = -4.788094E-4
+WKETA = 1.430792E-3 LKETA = -6.548592E-3 )
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 9 (4/15/02) Page 3.9-15

Adjustable Precision Analog Models – Table Lookup

y
High Circuit
Level x1
Level
Simulators Simulators
x2

x3

"Extraction" Methodology
Process
I-V characterisitcs Measurement
Simulators
Capacitances Methods
Transconductances

• Objective
Develop models having adjustable precision in ac and dc perfomrance using table
lookup models.
• Advantages
Usable at any level – device, circuit, or behavioral
Quickly developed from experiment or process simulators
Faster than analytical device models (BSIM)
• Disadvantages
Requires approximately 10kbytes for a typical MOS model
Can’t be parameterized easily
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 9 (4/15/02) Page 3.9-16

Summary of MOSFET Models for Simulation

• Models are much improved for efficient computer simulation
• Output conductance model is greatly improved
• Poor results for narrow channel transistors
• Can have discontinuities at bin boundaries
• Fairly complex model, difficult to understand in detail

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 10 (4/15/02) Page 3.10-1

SEC. 3.10 – EXTRACTION OF A LARGE SIGNAL MODEL FOR HAND

CALCULATIONS
Objective
Extract a simple model that is useful for design from the computer models such as
BSIM3.
Extraction for Short Channel Models
Procedure for extracting short channel models:
1.) Extract the square-law model parameters for a transistor with length at least 10
times Lmin.
2.) Using the values of K’, VT , λ, and γ extract the model parameters for the following
model:
K’ W
iD = 2[1 + θ(v -V )] L [ vGS – VT]2(1+λvDS)
GS T

Adjust the values of K’, VT , and λ as needed.

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 10 (4/15/02) Page 3.10-2

EXTRACTION OF THE SIMPLE, SQUARE-LAW MODEL

Characterization of the Simple Square-Law Model
Equations for the MOSFET in strong inversion:
 Weff 
iD = K  (vGS - VT) 2(1 + λvDS) (1)
 2Leff

 2 
Weff  vDS
iD = K   (vGS - VT)vDS - 2 (1 + λvDS) (2)
 Leff 
where
V T = V T0 + γ [ 2|φF| + vSB − 2|φF| ] (3)

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 10 (4/15/02) Page 3.10-3

Extraction of Model Parameters:

First assume that vDS is chosen such that the λvDS term in Eq. (2) is much less than one
and vSB is zero, so that VT = VT0.
Therefore, Eq. (2) simplifies to
 Weff 
 
iD = K’2Leff (vGS - VT0) 2 (6)
 

This equation can be manipulated algebraically to obtain the following

1/2  K' Weff  K' Weff
  1/2   1/2
iD =  2Leff  vGS =  2Leff  VT0 (7)
   

which has the form

y = mx + b (8)
This equation is easily recognized as the equation for a straight line with m as the slope
and b as the y-intercept. Comparing Eq. (7) to Eq. (8) gives
1/2
y= iD (9)
x= vGS (10)
K' Weff1/2


m = 2Leff 
 (11)
 
and
K' Weff1/2


b = - 2Leff 
 VT0 (12)
 
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 10 (4/15/02) Page 3.10-4

Illustration of K’ and VT Extraction

1/2
(iD) Mobility degradation
region

vDS >VDSAT

Weak inversion
region 1/2
 K ′ Weff 
m=  
2L eff 

0 vGS
0 b′ =VT0 AppB-01
Comments:
• Stay away from the extreme regions of mobility degradation and weak inversion
• Use channel lengths greater than Lmin

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 10 (4/15/02) Page 3.10-5

Example 3.10-1 – Extraction of K’ and VT Using Linear Regression

Given the following transistor data shown in Table 3.10-1 and linear regression formulas
based on the form,
y = mx + b (13)
and
∑xi yi - (∑ xi∑ yi)/n
m= 2 (14)
∑xi - (∑xi)2/n
1/2
determine VT0 and K W/2L. The data in Table B-1 also give ID as a function of VGS.
Table 3.10-1 Data for Example 3.10-1
VGS (V) ID (µA) ID (µA)1/2 VSB (V)
1.000 0.700 0.837 0.000
1.200 2.00 1.414 0.000
1.500 8.00 2.828 0.000
1.700 13.95 3.735 0.000
1.900 22.1 4.701 0.000

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 10 (4/15/02) Page 3.10-6

Example 3.10-1 – Continued

Solution
The data must be checked for linearity before linear regression is applied. Checking
slopes between data points is a simple numerical technique for determining linearity.
Using the formula that
∆y ID2 - ID1
Slope = m = =
∆x VGS2 - VGS1
Gives
1.414 - 0.837 2.828 - 1.414
m1 = 0.2 = 2.885 m2 = 0.3 = 4.713
3.735 - 2.828 4.701 - 3.735
m3 = 0.2 = 4.535 m4 = 0.2 = 4.830
These results indicate that the first (lowest value of VGS) data point is either bad, or at a
point where the transistor is in weak inversion. This data point will not be included in
subsequent analysis. Performing the linear regression yields the following results.
K'Weff
VT0 = 0.898 V and = 21.92 µA/V 2
2Leff

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 10 (4/15/02) Page 3.10-7

Extraction of the Bulk-Threshold Parameter γ

Using the same techniques as before, the following equation
V T = V T0 + γ [ 2|φF| + vSB − 2|φF| ]
is written in the linear form where
y = VT (18)
x= 2|φF| + vSB − 2|φF| (19)
m=γ (20)
b = VT0 (21)
The term 2|φF| is unknown but is normally in the range of 0.6 to 0.7 volts.
Procedure:
1.) Pick a value for 2|φF|.
2.) Extract a value for γ.
2εsi q NSUB
3.) Calculate NSUB using the relationship, γ = Cox
kT NSUB
4.) Calculate φF using the relationship, φF = − q ln  ni 
5.) Iterative procedures can be used to achieve the desired accuracy of γ and 2|φF|.
Generally, an approximate value for 2|φF| gives adequate results.
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 10 (4/15/02) Page 3.10-8

Illustration of the Procedure for Extracting γ

A plot of iD versus vGS for different values of vSB used to determine γ is shown below.
1/2
(iD)

vGS
VT0 VT1 VT2 VT3
FigAppB-02
By plotting VT versus x of Eq. (19) one can measure the slope of the best fit line from
which the parameter γ can be extracted. In order to do this, VT must be determined at
various values of vSB using the technique previously described.

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 10 (4/15/02) Page 3.10-9

Illustration of the Procedure for Extracting γ - Continued

Each VT determined above must be plotted against the vSB term. The result is shown
below. The slope m, measured from the best fit line, is the parameter γ.
VSB =3V
VSB =2V
VT
VSB =1V m= γ

VSB =0V

0.5 0.5
(vSB +2 φF ) − (2 φF ) FigAppB-03

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 10 (4/15/02) Page 3.10-10

Example 3.10-2 – Extraction of the Bulk Threshold Parameter

Using the results from Ex. B-1 and the following transistor data, determine the value of γ
using linear regression techniques. Assume that 2|φF| is 0.6 volts.
Table 3.10-2 Data for Example 3.10-2.
VSB (V) VGS (V) ID (µA)
1.000 1.400 1.431
1.000 1.600 4.55
1.000 1.800 9.44
1.000 2.000 15.95
2.000 1.700 3.15
2.000 1.900 7.43
2.000 2.10 13.41
2.000 2.30 21.2
Solution
Table B-2 shows data for VSB = 1 volt and V SB = 2 volts. A quick check of the data in this
table reveals that ID versus VGS is linear and thus may be used in the linear regression
analysis. Using the same procedure as in Ex. B-1, the following thresholds are
determined: VT0 = 0.898 volts (from Ex. B-1), V T = 1.143 volts (@VSB = 1 V), and V T =
1.322 V (@VSB = 2 V). Table B-3 gives the value of V T as a function of [(2|φF| + VSB)1/2 −
(2|φF|)1/2 ] for the three values of VSB.
CMOS Analog Circuit Design © P.E. Allen - 2002
Chapter 3 – Section 10 (4/15/02) Page 3.10-11

Example 3.10-2 - Continued

Table 3.10-3 Data for Example 3.10-2.
VSB (V) VT (V) [ 2|φF| + VSB - 2|φF| ] (V1/2)
0.000 0.898 0.000
1.000 1.143 0.490
2.000 1.322 0.838
With these data, linear regression must be performed on the data of VT versus [(2|φF| +
VSB)0.5 − (2|φF |)0.5]. The regression parameters of Eq. (13) are
Σxiyi = 1.668
Σxiyi = 4.466
2
Σxi = 0.9423
(Σxi)2 = 1.764
These values give m = 0.506 = γ.

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 10 (4/15/02) Page 3.10-12

Extraction of the Channel Length Modulation Parameter, λ

The channel length modulation parameter λ should be determined for all device lengths
that might be used. For the sake of simplicity, Eq. (2) is rewritten as
iD = i’D=λ’ vDS + i’D (22)
which is in the familiar linear form where
y = iD (Eq. (2)) 23)
x = vDS (24)
m = λi'D (25)
b = i'D (Eq. (2) with λ = 0) (26)
iD
By plotting iD versus vDS, measuring the slope
of the data in the saturation region, and Saturation region
Nonsaturation
dividing that value by the y-intercept, λ can be region
determined. The procedure is illustrated in the
figure shown. i'D m = λ i'D

vDS
AppB-03

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 10 (4/15/02) Page 3.10-13

Example 3.10-3 – Extraction of the Channel Length Modulation Parameter

Given the data of ID versus VDS in Table 10.3-4, determine the parameter λ.
Table 10.3-4 Data for Example 3.10-3.
ID (µA) 39.2 68.2 86.8 94.2 95.7 97.2 98.8 100.3
VDS (V) 0.500 1.000 1.500 2.000 2.50 3.00 3.50 4.00
Solution
We note that the data of Table 3.10-4 covers both the saturation and nonsaturation
regions of operation. A quick check shows that saturation is reached near V DS = 2.0 V. To
calculate λ, we shall use the data for VDS greater than or equal to 2.5 V. The parameters of
the linear regression are
xiyi = 1277.85 ∑xi∑yi = 5096.00
∑x2i = 43.5 (∑xi)2 = 169
These values result in m = λI'D = 3.08 and b = I'D = 88, giving λ = 0.035 V-1.
The slope in the saturation region is typically very small, making it necessary to be careful
that two data points taken with low resolution are not subtracted (to obtain the slope)
resulting in a number that is of the same order of magnitude as the resolution of the data
point measured. If this occurs, then the value obtained will have significant and
unacceptable error.

CMOS Analog Circuit Design © P.E. Allen - 2002

Chapter 3 – Section 11 (4/15/02) Page 3.11-1

SEC. 3.11 - SUMMARY

• Model philosophy for analog IC design
Use simple models for design and sophisticated models for verification
• Models have several parts
Large signal static (dc variables)
Small signal static (midband gains, resistances)
Small signal dynamic (frequency response, noise)
Large signal dynamic (slew rate)
• In addition models may include:
Temperature
Noise
Process variations (Monte Carlo methods)
• Computer models
Must be numerically efficient
Quickly derived from new technology
• Analog Design “Tricks”
Stay away from minimum channel length if possible
- Larger rds → larger gains
- Better agreement
Don’t use the computer models for design, rather verification of design
CMOS Analog Circuit Design © P.E. Allen - 2002