INTERNAL ASSESSMENT- I

Program Name: S.E. [CSE/CE]. Semester: IV

Marks: 20 Date: 12/03/25 Time: 10:00 to 11:00 am
Course: Microprocessors (CSC405)

B
Q.01) Attempt the following questions: Marks CO
L
a) Draw and explain the timing diagrams for read and write operations in [10] 2 CO1
the minimum mode of the 8086 processor.
Solution Timing 5
diagram m

Explain
tion 5m

The sequence of operations during the read machine cycle are as

follows :
Step 1 : The 8086 will make M/–––IO = 1 if the read is from memory
and M/–––IO = 0 if the read is from the I/O device.
Step 2 : At about the same time the ALE output is asserted to 1.
Step 3 : Make –––––BHE low/high and send out the desired address
on AD0 to AD15 and A16 to A19 lines.
Step 4 : Pull down ALE (make it 0). The address is latched into
external latch.
Step 5 : Remove the address from AD0 to AD15 lines and put them
in the input mode (float them).
Step 6 : Assert the –––RD (read) signal low. This will put the data
from the addressed memory location or I/O port on to the data bus.
Step 7 : Insert the “wait” T- states if the 8086 READY input is made
low before or during the T2 state of a machine cycle.
Step 8 : As soon as READY input goes high, 8086 comes out of the
wait T-states and completes the machine cycle.
Step 9 : Complete the “Read” cycle by making the –––RD line high
(inactive).
 Step 1 : The 8086 will make M/–––IO = 1 if the write is from
memory and M/–––IO = 0 if the write is from the I/O device.
Step 2 : At about the same time the ALE output is asserted to 1.
Step 3 : Make –––––BHE low/high and send out the desired address
on AD0 to AD15 and A16 to A19 lines.
Step 4 : Pull down ALE (make it 0). The address is latched into
external latch.
Step 5 : Remove the address from AD0 to AD15 lines and place the
data on them
Step 6 : Assert the ––––WR (write) signal low. This will put the data
from the addressed memory location or I/O port on to the data bus.

Q.02) Attempt the following questions.

a) Explain the following 8086 instructions with examples wherever [05] 2 CO2
necessary:
(i) DAA, (ii) STOSB
Solution DAA (Decimal Adjust Accumulator) Each
DAA instruction is used to convert the result of the addition of two instructi
packed BCD numbers into a packed BCD number. on with
DAA only works on AL register. So, DAA instruction must be a
used after the ADD/ADC instruction. relevant
The ADD/ADC instruction adds the two BCD number in exampl
hexadecimal format and DAA instruction convert this e = 2.5
hexadecimal result to BCD result. m
The working of DAA instruction is given below.
1.If the value of the lower nibble in AL accumulator is greater
than 9 or if AF flag is set, the DAA instruction adds 6 to the
lower nibble of AL accumulator.
2.If the value of the higher nibble in AL accumulator is greater
than 9 or if CF flag is set, the DAA instruction adds 60 to the
higher nibble of AL accumulator. Flag affected : CF, PF, AF, SF, ZF
and OF is undefined.
Operation
(a)If lower nibble of AL > 9 or AF = 1,then AL = AL + 06.
(b)If higher nibble of AL > 9 or CF = , then AL = AL + 60.
(c)If both above condition are satisfied, then AL = AL + 66.
 Example
If AL = 99 BCD and BL = 99 BCD
Then ADD AL, BL
1001 1001 = AL = 99 BCD
+ 1001 1001 = BL = 99 BCD
______________________________
0011 0010 = AL = 32 H and CF=1, AF=1
Now, in above example after addition, Carry and Auxiliary carry
flags are set. So DAA instruction adds 6 to higher as well as lower
nibble of AL register to get correct BCD result i.e. 198 BCD of which
98 in AL and Cy =1 as given below.
After the execution of DAA instruction, the result is
Cy =1 0011 0010 = AL = 32 H and AF = 1
+0110 0110
_______________
1001 1000 = AL = 98 in BCD form

STOSB : Store String Byte

The instruction STOSB transfers a byte from the AL register to
destination string pointed by DI in ES.
On execution of a string instruction, DI is automatically
updated to point next element of the source string.
If DF = 0, the register DI will be incremented by 1 for byte
and incremented by 2 for word.
If DF=1, the register DI will be decremented by 1 for byte and
decremented by 2 for word.
In the instruction STOS, the source must be explicitly
declared either with DB.
Another way to store a byte or word string is by using implicit
instruction STOSB and STOSW.
The instruction STOSB is used to transfer a byte from AL to
destination and the instruction STOSW is used to transfer a word
from AX to destination.
In multiple byte or word loads, the count must be loaded in
CX register which functions as a counter.
Operation
If byte movement ES:[DI] AL
For DF = 0 DI -> DI + 1
For DF = 1 DI -> DI – 1
Example
MOV AX, @data
MOV DS, AX
MOV ES, AX
CLD
MOV DI, OFFSET D_STRING
STOSB
b) Explain the initialization command words (ICWs) and operational [05] 2 CO3
command words (OCWs) of the 8259 PIC
Solution List all Command words and explain any 4 in detail 1m for
each
comma
nd word
and 1m
 for list
of
comma
nd
words

ICW1
ICW1 is compulsory. The address bit, A0 must be ‘0’ while giving
the Initialization control word 1 to the 8259 chip.
A7 to A5(D7 to D5) : The three MSBs i.e. D7 to D5 are required
when interfaced with 8085. In case of 8086, these bits are not required
for 8259 interfaced with 8086
D4 : This bit should always be kept at logic ‘1’
LTIM (D3) : This bit is used t indicate the interrupts are to be level
triggered or edge triggered. If this bit is kept at ‘1’ then the interrupts
IR0 to IR7 are level triggered else they are edge triggered.
ADI(D2) : This bit is again required for 8085 and not required for
8086
SNGL (D1) : This bit is used to indicate the 8259 is in single mode
or cascaded mode. If this bit is ‘1’, then 8259 is in single mode else it
is in cascaded mode. If in cascaded mode then ICW3 will be required.
IC4 (D0) : This bit indicates the requirement of ICW4.

ICW2
ICW2 is compulsory. The address bit, A0 must be ‘1’ while giving
the Initialization control word 2 to the 8259 chip.
T7 to T3 (D7 to D3) : The five bits of ICW2 are used to indicate the
interrupt type to be given to 8086 when an interrupt occurs on a pin of
8259. The last three bits to make the interrupt type eight bit value are
taken as 000 for IR0 to 111 for IR7. Hence the interrupt type
corresponding to a particular interrupt on 8259 pin is generated by
taking the five bits T7 to T3 and concatenated with the three bits
000 to 111.
D2 to D0 : These bits are not required when interfaced with 8086.

ICW3
ICW3 is required on in cascaded mode. The address bit, A0 must be
‘1’ while giving the Initialization control word 3 to the 8259 chip.
ICW3 has a different structure for both master 8259 as well as slave
8259
For master, each of the bit is used to indicate whether a slave is
connected of the corresponding interrupt request (IR) pin or not. A ‘1’
indicates that a slave is connected to the corresponding Interrupt
request pin, while a ‘0’ indicates no slave is connected.
For slave, the ICW3 contains the ID of the device. This is required
for the slave to compare when the acknowledgement is given by the
processor, to realize whether the acknowledgement is meant for the
same slave or another slave. The ID is provided by the master 8259 on
receipt of acknowledgement from the microprocessor on the cascaded
pins

ICW4 is required if IC4 bit of ICW1 was made ‘1’. The address bit,
A0 must be ‘1’ while giving the Initialization control word 4 to the
8259 chip.
D7 to D5 : The three MSBs i.e. D7 to D5 are not required for 8259
interfaced with 8086
SFNM(D4) : This bit indicates whether the 8259 has to operate in
SFNM mode or FNM mode. If this bit is ‘1’, then 8259 has to operate
in SFNM mode, else FNM mode.
BUF and M/S (D3) : These bits are used to indicate whether 8259 is
in buffered mode or not. In case of buffered mode, M/S indicates it’s a
master or a slave. If the BUF bit is ‘1’ and If the M/S bit is ‘1’, it
indicates buffered master, else buffered slave.
AEOI(D1) : This bit is used to indicate whether Automatic end of
interrupt (EOI) or normal end of interrupt
μPM (D0) : This bit is used to indicate the 8259 is connected to 8085
or 8086. If this bit is ‘1’ then 8259 is connected to 8086 else connected
to 8085
OCW1
The address bit, A0 must be ‘1’ while giving the operational control
word 1 to the 8259 chip.
M7 to M0 (D7 to D0) : These bits indicate masking or unmasking of
a particular interrupt request IR0 to IR7 of 8259. If a bit is set to ‘1’,
the corresponding interrupt is disabled or masked, else its enabled or
unmasked. The address bit, A0 must be ‘1’ while giving the
operational control word 2 to the 8259 chip.

OCW2
R, SL and EOI (D7 to D0) : These bits indicate different commands
programming for 8259.
L2 to L0 (D2 to D0) : These bits are used to indicate the level or
the interrupt request IR0 to IR7, when selecting a particular command
using the bits D7 to D0.
For example if the command is “specific EoI command”, then L2 to
L0 specify the interrupt level for which it is specific EoI. For certain
commands like non-specific EoI, the bit D2 to D0 are not required

OCW3
 The address bit, A0 must be ‘0’ while giving the operational control
word 3 to the 8259 chip.
D7 and D4 : These bits should always be 0.
ESMM and SMM (D6 and D5) : These bits are used to enable
and disable the Special mask mode.
D3 : This bit should always be ‘1’
P (D2) : This bit is used to indicate giving of poll command from
8259. If the number of interrupt sources are too many and they cannot
be interfaced using even cascaded mode, then the additional interrupt
sources can be connected to8259s connected in poll mode. In this
mode, the INTR pin of 8259 will not be connected to the INTR pin of
8086. This mode may also be required otherwise.
RR and RIS (D1 and D0) : These bits are used to indicate 8259
that the processor wants to read the registers IRR (Interrupt request
register) or ISR (In-service register).

Q.03) Attempt the following questions.

a) Draw and Explain IVT of the 8086 processor [05] 2 CO1
The interrupt vector (or interrupt pointer) table is the link between an IVT..
interrupt type code and the procedure that has been designated to service 3m
interrupts associated with that code. i.e. ISR
8086 supports total 256 types i.e. 00H to FFH. For each type it has to reserve Explain
four bytes i.e. double word. ation..
This double word pointer contains the address of the procedure that is to 2m
service interrupts of that type.
The higher addressed word of the pointer contains the base address of the
segment containing the procedure.
This base address of the segment is normally referred as NEW CS. The
lower addressed word contains the procedure’s offset from the beginning of
the segment.
This offset we normally refer as NEW IP.
Thus NEW CS : NEW IP provides NEW physical address from where user
ISR routine will start.
As for each type, four bytes (2 for NEW CS and 2 for NEW IP) are
required, therefore interrupt pointer table occupies upto the first 1k bytes
(i.e. 256 * 4 = 1024 bytes), of low memory.
Thus 00000 H to 003FF H, these locations of 8086 microprocessor is
reserved for interrupt vector table.
  Suppose for example type code is ‘3’. Then 3 * 4 = (12)10 = 0C H
then 0CH/0DH location will provide OFFSET IP (NEW IP) and 0EH/0FH
will provide base address of the segment (NEW CS).

total interrupt vector table is divided into three groups :

(1) Dedicated interrupt pointers (Type 0/1/2/3/4)
(2) Reserved interrupt pointers (Type 5 to Type 31)
(3) Available interrupt pointers (Type 32 to Type 225).
Type 0 to 4 are dedicated interrupt pointers by Intel for divide by zero
error, single step, NMI, 1-byte INT instruction and overflow.
Interrupt types from 5 to 31 are reserved by Intel for use in more complex
microprocessors, such as 80286, 80386, 80486.
Finally the types from 32 to 255 i.e. total 224, are available to user to
use for either hardware or software interrupt.
b) Write an ALP to arrange 10 numbers in ascending order. [05] 3 CO2
.model small
.data array dw 12h,11h,21h,9h,19h ,01h, 02h,03h,04h,05h
.code mov ax,@data ;Initialize data segment mov
ds,ax
mov bx,5 ;Initialize pass counter up1:
mov si,offset array ;Initialize memory pointer mov cx,4
;Initialize word counter up: mov ax,[si]
cmp ax,[si+2] ;Compare two number jc dn
;if number < next number ; then go to dn xchg ax,[si+2]
;interchange numbers xchg ax,[si]
dn: add si,2 ;increment memory pointer
loop up ;decrement word counter ; if cx=0 then up
dec bx ;decrement pass counter ;if bx=0 then up1
jnz up1
ends
end OR
.model small
.data
array db 12h,11h,21h,9h,19h ,01h, 02h,03h,04h,05h
.code
mov ax,@data ;Initialize data segment
mov ds,ax
mov bx,5 ;Initialize pass counter
up1: mov si,offset array ;Initialize memory pointer
mov cx,4 ;Initialize byte counter
up: mov al,[si]
cmp al,[si+1] ;Compare two number
jc dn ;if number < next number then
xchg al,[si+1] ;interchange numbers
xchg al,[si]
dn: inc si ;increment memory pointer
loop up ;decrement byte counter if 0 then up
dec bx ;decrement pass counter if 0 then up1
jnz up1
ends end