ELE 315 Electronics II

Hacettepe University

Dr. Umut Sezen

Dr. Dinçer Gökcen

09 December 2017

1. These lecture notes are not complete and regularly updated at the address below:
http://www.ee.hacettepe.edu.tr/∼usezen/ele315/.

2. These lecture notes use material from several other sources like Prof. Selçuk Geçim's lecture
notes, Electronic Devices and Circuit Theory, 8th ed." by Boylestad and Nashelsky and and
its instructor materials, Integrated Electronics: Analog and Digital Circuits and Systems" by
Millman and Halkias, and Digital Integrated Circuits" by DeMassa and Ciccone.
Contents

List of Figures xiii

List of Examples xv
List of Homeworks xvi
Textbook xvii
1 Analogue Electronics 1
1.1 Feedback and Feedback Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Amplier Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1.1 Voltage-Gain Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.1.2 Transresistance Amplier . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.1.3 Transconductance Amplier . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.1.4 Current-Gain Amplier . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.2 Negative Feedback Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.2.1 Closed-loop Gain, Af . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.2.2 Negative Feedback Improvements . . . . . . . . . . . . . . . . . . . . 7
1.1.2.3 Sampling and Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.2.4 Sampling Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.2.5 Mixing Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1.2.6 Negative Feedback Types . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1.3 Voltage-Series Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1.3.1 No-load Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1.3.2 Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1.3.3 Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1.4 Voltage-Shunt Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1.4.1 No-load Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.1.4.2 Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.1.4.3 Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.1.5 Current-Series Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.1.5.1 No-load Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1.5.2 Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.1.5.3 Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.1.6 Current-Shunt Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.1.6.1 No-load Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

i
 1.1.6.2 Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.1.6.3 Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.1.7 Summary of Closed-loop Input and Output Resistances . . . . . . . . . . . . . 30
1.1.8 Analysis of Negative Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.1.8.1 Recognize the type of feedback . . . . . . . . . . . . . . . . . . . . . 30
1.1.8.2 Derive open-loop circuit . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.1.8.3 Ensure suitability of the input signal source . . . . . . . . . . . . . . 35
1.1.8.4 Obtain open-loop small-signal equivalent circuit . . . . . . . . . . . . 35
1.1.8.5 Find feedback gain β . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.1.8.6 Summary of feedback amplier analysis . . . . . . . . . . . . . . . . 35
1.1.9 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.2 Dierential Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
1.2.0.1 Three Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . 48
1.2.1 DC Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1.2.2 Small-Signal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
1.2.3 Single-Ended Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.2.4 Common-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.2.5 Dierential-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.2.6 Linear Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.2.7 Common-Mode Rejection (Noise Rejection) . . . . . . . . . . . . . . . . . . . 55
1.2.8 Dierential Amplier with a Constant-Current Source . . . . . . . . . . . . . . 56
1.2.8.1 Constant-Current Source Circuits . . . . . . . . . . . . . . . . . . . . 56
1.2.8.2 Analysis of Dierential Amplier with a Constant-Current Source . . 59
1.2.9 Dierential Amplier Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.2.10 Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
1.2.11 FET Dierential Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
1.2.11.1 Small-Signal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 64
1.2.12 Uses of Dierential Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1.2.13 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
1.3 Operational Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
1.3.1 Ideal Op-Amp Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
1.3.2 MC1530 Operational Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . 70
1.3.2.1 DC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
1.3.2.2 Small-signal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
1.3.3 Op-Amp Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
1.3.4 Inverting Op-Amp Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
1.3.4.1 Virtual Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
1.3.4.2 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1.3.5 Practical Op-Amp Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1.3.5.1 Inverting Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1.3.5.2 Non-Inverting Amplier . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.3.5.3 Summing Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.3.5.4 Unity Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
1.3.5.5 Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
1.3.5.6 Dierentiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

ii
 1.3.5.7 Logarithmic Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.3.6 Op-Amp Specications - DC Bias and Oset Parameters . . . . . . . . . . . . 78
1.3.6.1 Input Bias and Oset Currents . . . . . . . . . . . . . . . . . . . . . 79
1.3.6.2 Input Oset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.3.6.3 Input Oset Voltage and Current Drifts . . . . . . . . . . . . . . . . 80
1.3.6.4 Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . 80
1.3.6.5 Open-loop voltage gain . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.3.6.6 Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.3.6.7 Common-Mode Rejection Ratio . . . . . . . . . . . . . . . . . . . . . 81
1.3.6.8 Open-Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 81
1.3.6.9 Op-Amp Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 82
1.3.7 Eects of Oset Voltage and Bias Currents . . . . . . . . . . . . . . . . . . . . 83
1.3.8 Multistage Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
1.3.9 Active Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
1.3.9.1 Lowpass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
1.3.9.2 Highpass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
1.3.9.3 Bandpass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
1.4 Power Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
1.4.1 Power Amplier Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
1.4.1.1 Class A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
1.4.1.2 Class B Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
1.4.1.3 Class AB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
1.4.1.4 Class C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
1.4.1.5 Class D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
1.4.1.6 Amplier Eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
1.4.1.7 Power Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
1.4.1.8 Power Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
1.4.1.9 Transistor Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 93
1.4.1.10 Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
1.4.2 Series-Fed Class A Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
1.4.2.1 AC-DC Load Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
1.4.2.2 Power Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
1.4.2.3 Power Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
1.4.2.4 Eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
1.4.2.5 Transistor Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 95
1.4.2.6 Maximum Eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
1.4.2.7 Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
1.4.3 Transformer-Coupled Class A Amplier . . . . . . . . . . . . . . . . . . . . . . 97
1.4.3.1 AC-DC Load Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
1.4.3.2 Power Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
1.4.3.3 Power Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
1.4.3.4 Eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
1.4.3.5 Transistor Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 99
1.4.3.6 Maximum Eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
1.4.3.7 Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

iii
 1.4.4 Class B Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
1.4.4.1 Phase Splitter Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 101
1.4.4.2 Transformer-Coupled Push-Pull Class B Amplier . . . . . . . . . . . 102
1.4.4.3 Complementary-Symmetry Push-Pull Class B Amplier . . . . . . . 103
1.4.4.4 Power Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
1.4.4.5 Power Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
1.4.4.6 Eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
1.4.4.7 Transistor Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 105
1.4.4.8 Maximum Eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
1.4.4.9 Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
1.4.4.10 Crossover Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
1.4.5 Class AB Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
1.4.6 Power Transistor Heat Sinking . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
1.4.6.1 Thermal-to-Electrical Analogy . . . . . . . . . . . . . . . . . . . . . 110
1.4.7 Class C Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
1.4.8 Class D Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
1.5 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
1.5.1 Types of Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
1.5.2 Phase-Shift Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
1.5.2.1 FET Phase-Shift Oscillator . . . . . . . . . . . . . . . . . . . . . . . 119
1.5.2.2 BJT Phase-Shift Oscillator . . . . . . . . . . . . . . . . . . . . . . . 120
1.5.2.3 Opamp Phase-Shift Oscillator . . . . . . . . . . . . . . . . . . . . . . 120
1.5.3 Wien-Bridge Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
1.5.4 Tuned Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
1.5.4.1 Colpitts Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . 123
1.5.4.2 Hartley Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . 125
1.5.5 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
1.5.6 Unijunction Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

2 Digital Electronics 133

2.1 Properties of Digital Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 133
2.1.1 Inverter and Non-Inverter Gates . . . . . . . . . . . . . . . . . . . . . . . . . . 133
2.1.2 Ideal Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
2.1.3 Inverter Voltage Transfer Characteristic . . . . . . . . . . . . . . . . . . . . . 134
2.1.4 Fan-In and Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
2.1.5 Transient Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
2.1.6 Average Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
2.1.7 Power-Delay Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
2.1.8 Logic Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
2.2 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
2.2.1 Diode Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
2.2.2 Clamping Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
2.2.3 Level-Shifting Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
2.3 BJT Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
2.3.1 Ebers-Moll BJT Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.3.2 BJT Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

iv
 2.3.2.1 Cuto (OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
2.3.2.2 Forward Active (FA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
2.3.2.3 Reverse Active (RA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
2.3.2.4 Saturation (SAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
2.3.2.5 Simplied NPN BJT Model . . . . . . . . . . . . . . . . . . . . . . . 155
2.3.2.6 IV Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
2.3.3 BJT Sub-Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
2.3.3.1 Input Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
2.3.3.2 Drive Splitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
2.3.3.3 Output-High Pull-Up Driver . . . . . . . . . . . . . . . . . . . . . . . 159
2.3.3.4 Output-Low Pull-Down Driver . . . . . . . . . . . . . . . . . . . . . 160
2.3.3.5 Discharge Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
2.3.3.6 Base Driving Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . 161
2.3.3.7 Power Dissipation of BJT Logic Circuits . . . . . . . . . . . . . . . . 162
2.4 Resistor-Transistor Logic (RTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
2.4.1 Basic RTL Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
2.4.2 Basic RTL NOR and NAND Gates . . . . . . . . . . . . . . . . . . . . . . . . 165
2.4.3 Basic RTL Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
2.4.4 Basic RTL Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
2.4.5 Basic RTL Non-Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
2.4.6 RTL with Active Pull-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
2.4.7 RTL with Active Pull-Up Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . 171
2.5 Diode-Transistor Logic (DTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
2.5.1 Basic DTL Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
2.5.2 Basic DTL NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
2.5.3 Diode Modied DTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
2.5.4 Transistor Modied DTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
2.5.5 DTL NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
2.5.6 DTL Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
2.5.6.1 DTL Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 178
2.6 Transistor-Transistor Logic (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
2.6.1 Basic TTL Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
2.6.2 Basic TTL NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
2.6.3 Standard TTL NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
2.6.4 TTL Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
2.6.4.1 TTL Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 185
2.6.5 Open-Collector TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
2.6.6 Low Power TTL (LTTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
2.6.7 High Speed TTL (HTTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
2.7 Other TTL Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
2.7.1 AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
2.7.2 NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
2.7.3 OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
2.7.4 AND-OR-INVERT (AOI) Gates . . . . . . . . . . . . . . . . . . . . . . . . . . 193
2.7.5 XOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

v
 2.7.6 Schmitt Trigger Inverters and NAND Gates . . . . . . . . . . . . . . . . . . . 198
2.7.6.1 Basic Emitter-Coupled Schmitt Trigger Noninverter . . . . . . . . . . 199
2.7.6.2 Schmitt Trigger NAND Gate . . . . . . . . . . . . . . . . . . . . . . 201
2.7.7 Tri-State Buers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
2.8 NMOS and CMOS Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

vi
List of Figures

1.1.1 Voltage-gain amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.1.2 Transresistance amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.3 Transconductance amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.4 Current-gain amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.5 Negative feedback block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.6 Amplier bandwidth example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.7 Sampling and mixing diagram in a negative feedback system . . . . . . . . . . . . . 11
1.1.8 Voltage-sampling example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1.9 Current-sampling example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1.10 Series-mixing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1.11 Shunt-mixing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1.12 Voltage-series feedback: Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1.13 Voltage-series feedback amplier model (i.e., closed-loop voltage-gain amplier) . . 14
1.1.14 Voltage-series feedback: Block diagram with open-loop amplier parameters . . . . . 15
1.1.15 Voltage-series feedback: No-load gain calculation diagram . . . . . . . . . . . . . . . 15
1.1.16 Voltage-series feedback: Input resistance calculation diagram . . . . . . . . . . . . . 16
1.1.17 Voltage-series feedback: Output resistance calculation diagram . . . . . . . . . . . . 17
1.1.18 Voltage-shunt feedback: Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1.19 Voltage-shunt feedback amplier model (i.e., closed-loop transresistance amplier) . 18
1.1.20 Voltage-shunt feedback: Block diagram with open-loop amplier parameters . . . . 19
1.1.21 Voltage-shunt feedback: No-load gain calculation diagram . . . . . . . . . . . . . . . 19
1.1.22 Voltage-shunt feedback: Input resistance calculation diagram . . . . . . . . . . . . . 20
1.1.23 Voltage-shunt feedback: Output resistance calculation diagram . . . . . . . . . . . . 21
1.1.24 Current-series feedback: Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.1.25 Current-series feedback amplier model (i.e., closed-loop transconductance amplier) 22
1.1.26 Current-series feedback: Block diagram with open-loop amplier parameters . . . . 23
1.1.27 Current-series feedback: No-load gain calculation diagram . . . . . . . . . . . . . . . 23
1.1.28 Current-series feedback: Input resistance calculation diagram . . . . . . . . . . . . . 24
1.1.29 Current-series feedback: Output resistance calculation diagram . . . . . . . . . . . . 25
1.1.30 Current-shunt feedback: Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.1.31 Current-shunt feedback amplier model (i.e., closed-loop current-gain amplier) . . 26
1.1.32 Current-shunt feedback: Block diagram with open-loop amplier parameters . . . . 27
1.1.33 Current-shunt feedback: No-load gain calculation diagram . . . . . . . . . . . . . . 27
1.1.34 Current-shunt feedback: Input resistance calculation diagram . . . . . . . . . . . . . 28
1.1.35 Current-shunt feedback: Output resistance calculation diagram . . . . . . . . . . . . 29
1.1.36 Summary table for closed-loop input and output resistance expressions . . . . . . . 30

vii
1.1.37 Obtaining the open-loop input circuitry under voltage-sampling . . . . . . . . . . . 31
1.1.38 Obtaining the open-loop input circuitry under current-sampling . . . . . . . . . . . 32
1.1.39 Obtaining the open-loop output circuitry under series-mixing . . . . . . . . . . . . . 32
1.1.40 Obtaining the open-loop output circuitry under shunt-mixing . . . . . . . . . . . . . 33
1.1.41 Open-loop circuit diagram for voltage-series feedback . . . . . . . . . . . . . . . . . 33
1.1.42 Open-loop circuit diagram for voltage-shunt feedback . . . . . . . . . . . . . . . . . 34
1.1.43 Open-loop circuit diagram for current-series feedback . . . . . . . . . . . . . . . . . 34
1.1.44 Open-loop circuit diagram for current-shunt feedback . . . . . . . . . . . . . . . . . 34
1.1.45 Summary table for negative feedback amplier analysis . . . . . . . . . . . . . . . . 35
1.1.46 A source follower circuit (a voltage-series feedback example). . . . . . . . . . . . . 36
1.1.47 Initial open-loop circuit of the circuit given in Figure 1.1.46. . . . . . . . . . . . . . 37
1.1.48 Open-loop small-signal equivalent circuit of Figure 1.1.46. . . . . . . . . . . . . . . 37
1.1.49 Equivalent closed-loop amplier block diagram of the circuit given in Figure 1.1.46. 38
1.1.50 A multistage amplier system (a voltage-series feedback example). . . . . . . . . . 38
1.1.51 Open-loop circuit of the circuit given in Figure 1.1.50. . . . . . . . . . . . . . . . . 39
1.1.52 A collector feedback circuit (a voltage-shunt feedback example) . . . . . . . . . . . 39
1.1.53 Initial open-loop circuit of the circuit given in Figure 1.1.52. . . . . . . . . . . . . . 40
1.1.54 Equivalent closed-loop amplier block diagram of the circuit given in Figure 1.1.52. 41
1.1.55 A common emitter circuit (a current-series feedback example). . . . . . . . . . . . 42
1.1.56 Initial open-loop circuit of the circuit given in Figure 1.1.55. . . . . . . . . . . . . . 42
1.1.57 Open-loop small-signal equivalent circuit of Figure 1.1.55. . . . . . . . . . . . . . . 43
1.1.58 Equivalent closed-loop amplier block diagram of the circuit given in Figure 1.1.55. 44
1.1.59 A multistage BJT circuit (a current-shunt feedback example). . . . . . . . . . . . . 44
1.1.60 Initial open-loop circuit of the closed-loop circuit given in Figure 1.1.59. . . . . . . 45
1.1.61 Small-signal open-loop circuit of the closed-loop circuit given in Figure 1.1.59. . . . 45
1.1.62 Equivalent closed-loop amplier block diagram of the circuit given in Figure 1.1.59. 47
1.2.1 Dierential amplier model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
1.2.2 Dierential amplier with a common emitter resistance . . . . . . . . . . . . . . . . 48
1.2.3 Dierential amplier DC biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1.2.4 Dierential amplier small-signal analysis circuit. . . . . . . . . . . . . . . . . . . . 50
1.2.5 Single-ended dierential amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.2.6 Two out-of-phase outputs of the single-ended dierential amplier. . . . . . . . . . . 52
1.2.7 Dierential output of the single-ended dierential amplier. . . . . . . . . . . . . . . 52
1.2.8 Common-mode dierential amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.2.9 Dierential-mode dierential amplier. . . . . . . . . . . . . . . . . . . . . . . . . . 54
1.2.10 Dierential amplier with a constant-current source. . . . . . . . . . . . . . . . . . 56
1.2.11 A BJT constant-current source with resistors. . . . . . . . . . . . . . . . . . . . . . 56
1.2.12 A BJT constant-current source with a Zener diode. . . . . . . . . . . . . . . . . . . 57
1.2.13 A current-mirror constant-current source. . . . . . . . . . . . . . . . . . . . . . . . . 57
1.2.14 Identical current-mirror constant-current sources (I1 = I2 = · · · = IN ). . . . . . . . . 58
1.2.15 An improved current-mirror constant-current source. . . . . . . . . . . . . . . . . . 58
1.2.16 Dierential amplier with a constant-current source. . . . . . . . . . . . . . . . . . 59
1.2.17 Diode IV characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
1.2.18 Ratio of the collector currents to the constant-current source. . . . . . . . . . . . . 61
1.2.19 A dierential amplier with constant-current source (a dierential amplier example) 62

viii
1.2.20 Dierential amplier with a transistor at the collector. . . . . . . . . . . . . . . . . . 63
1.2.21 Dierential amplier with a current mirror at the collector. . . . . . . . . . . . . . . 63
1.2.22 FET dierential amplier with a common source resistance. . . . . . . . . . . . . . . 64
1.2.23 FET dierential amplier small-signal analysis circuit. . . . . . . . . . . . . . . . . . 64
1.2.24 A dierential amplier measurement circuit . . . . . . . . . . . . . . . . . . . . . . . 65
1.2.25 Dierential amplier circuit for Example 1.8. . . . . . . . . . . . . . . . . . . . . . . 66
1.2.26 Dierential amplier circuit for Example 1.9. . . . . . . . . . . . . . . . . . . . . . . 68
1.2.27 Dierential amplier circuit for Example 1.10. . . . . . . . . . . . . . . . . . . . . . 69
1.3.1 Operational amplier block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
1.3.2 Operational amplier model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
1.3.3 Electronic circuit of the MC1530 op-amp . . . . . . . . . . . . . . . . . . . . . . . . 71
1.3.4 Block diagram of the MC1530 electronic circuit in Figure 1.3.3 . . . . . . . . . . . . 71
1.3.5 MC1530 DC analysis calculations - 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 72
1.3.6 MC1530 DC analysis calculations - 2: Output stage . . . . . . . . . . . . . . . . . . 72
1.3.7 MC1530 small-signal analysis calculations . . . . . . . . . . . . . . . . . . . . . . . . 73
1.3.8 Inverting op-amp amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
1.3.9 Simplied inverting amplier circuit for an ideal op-amp. . . . . . . . . . . . . . . . 74
1.3.10 Inverting amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1.3.11 Non-inverting amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.3.12 Summing Amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.3.13 Unity Follower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
1.3.14 Integrator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
1.3.15 Dierentiator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.3.16 Integrator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.3.17 Input bias currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
1.3.18 Input oset voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.3.19 Power supply rejection ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.3.20 Op-amp open-loop bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
1.3.21 Some op-amp performance graphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
1.3.22 Some characteristics of a 741 opamp. . . . . . . . . . . . . . . . . . . . . . . . . . . 82
1.3.23 Eects of oset voltages and bias currents. . . . . . . . . . . . . . . . . . . . . . . . 83
1.3.24 Opamp Oset Elimination Problem for Example 1.11. . . . . . . . . . . . . . . . . . 84
1.3.25 Opamp Oset Elimination Solution for Example 1.11. . . . . . . . . . . . . . . . . . 84
1.3.26 Opamp Oset Elimination Problem for Example 1.12. . . . . . . . . . . . . . . . . . 84
1.3.27 Opamp Oset Elimination Solution for Example 1.12. . . . . . . . . . . . . . . . . . 85
1.3.28 Opamp Oset Elimination Problem for Example 1.13. . . . . . . . . . . . . . . . . . 85
1.3.29 Opamp Oset Elimination Solution for Example 1.13. . . . . . . . . . . . . . . . . . 86
1.3.30 Opamp amplier with R2 resistor: (a) inverting (b) noninverting. . . . . . . . . . . 86
1.3.31 Multistage opamp ampliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
1.3.32 First-order lowpass lter (a) Circuit (b) Bode magnitude plot . . . . . . . . . . . . . 87
1.3.33 Second-order lowpass lter (a) Circuit (b) Bode magnitude plot . . . . . . . . . . . 88
1.3.34 First-order highpass lter (a) Circuit (b) Bode magnitude plot . . . . . . . . . . . . 88
1.3.35 First-order bandpass lter (a) Circuit (b) Bode magnitude plot . . . . . . . . . . . . 89
1.4.1 Class A amplier output (full-cycle operation) . . . . . . . . . . . . . . . . . . . . . 90
1.4.2 A Class B amplier output (half-cycle operation) . . . . . . . . . . . . . . . . . . . 91

ix
1.4.3 Comparison of amplier classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
1.4.4 Series-fed Class A large-signal amplier . . . . . . . . . . . . . . . . . . . . . . . . . 93
1.4.5 AC-DC load-line for the series-fed Class A amplier in Figure 1.4.4 . . . . . . . . . 94
1.4.6 Transformer-coupled Class A power amplier . . . . . . . . . . . . . . . . . . . . . . 97
1.4.7 Transformer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
1.4.8 AC-DC load-line of the transformer-coupled Class A amplier in Figure 1.4.6 . . . . 98
1.4.9 Class B amplier push-pull operation block diagram . . . . . . . . . . . . . . . . . . 101
1.4.10 Phase splitter circuit with a center-tapped transformer . . . . . . . . . . . . . . . . 101
1.4.11 Phase splitter circuit with a BJT transistor . . . . . . . . . . . . . . . . . . . . . . . 102
1.4.12 Phase splitter circuit with op-amp(s) . . . . . . . . . . . . . . . . . . . . . . . . . . 102
1.4.13 Transformer-coupled push-pull Class B power amplier . . . . . . . . . . . . . . . . 102
1.4.14 Complementary-symmetry push-pull Class B power amplier . . . . . . . . . . . . . 103
1.4.15 Operation on the positive half-cycle of the input . . . . . . . . . . . . . . . . . . . . 103
1.4.16 Operation on the negative half-cycle of the input . . . . . . . . . . . . . . . . . . . . 104
1.4.17 Cross-over distortion at the Class B amplier output . . . . . . . . . . . . . . . . . 106
1.4.18 Quasi-complementary push-pull Class AB power amplier . . . . . . . . . . . . . . . 107
1.4.19 Transformer-coupled push-pull Class AB power amplier. . . . . . . . . . . . . . . . 108
1.4.20 Complementary push-pull Class AB power amplier . . . . . . . . . . . . . . . . . . 108
1.4.21 Another complementary push-pull Class AB power amplier . . . . . . . . . . . . . 109
1.4.22 Heat-related gures: (a) heat sinks, (b) a typical power derating curve. . . . . . . . 110
1.4.23 Thermal-to-electrical analogy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
1.4.24 Class C amplier circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
1.4.25 Block diagram of a Class D amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . 112
1.4.26 Chopping of sinusoidal waveform to produce digital waveform. . . . . . . . . . . . . 112
1.4.27 Power amplier circuits for Example 1.15. . . . . . . . . . . . . . . . . . . . . . . . 113
1.4.28 Output for the circuit of Fig-A in Figure 1.4.27. . . . . . . . . . . . . . . . . . . . . 114
1.4.29 Output for the circuit of Fig-B in Figure 1.4.27. . . . . . . . . . . . . . . . . . . . . 115
1.5.1 Positive feedback circuit used as an oscillator. . . . . . . . . . . . . . . . . . . . . . 116
1.5.2 Build-up of steady-state oscillations. . . . . . . . . . . . . . . . . . . . . . . . . . . 117
1.5.3 Idealized phase-shift oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
1.5.4 FET phase-shift oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
1.5.5 BJT phase-shift oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
1.5.6 Op-amp phase-shift oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
1.5.7 Wien-bridge oscillator circuit using op-amp amplier. . . . . . . . . . . . . . . . . . 121
1.5.8 Wien-bridge oscillator circuit for Example 1.16. . . . . . . . . . . . . . . . . . . . . 122
1.5.9 Basic conguration of tuned (or resonant) circuit oscillator. . . . . . . . . . . . . . . 123
1.5.10 Resonant element selection for a tuned oscillator . . . . . . . . . . . . . . . . . . . . 123
1.5.11 FET Colpitts Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
1.5.12 BJT Colpitts Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
1.5.13 Op-amp Colpitts Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
1.5.14 FET Hartley Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
1.5.15 BJT Hartley Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
1.5.16 Crystal operation: (a) electrical equivalent circuit, (b) crystal impedance versus fre-
quency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
1.5.17 Crystal-controlled FET oscillator circuit using crystal in series-feedback path. . . . . 128

x
1.5.18 Crystal-controlled Opamp oscillator circuit using crystal in series-feedback path. . . 129
1.5.19 Crystal-controlled BJT oscillator operating in parallel-resonant mode. . . . . . . . . 129
1.5.20 Basic unijunction oscillator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
1.5.21 Unijunction oscillator waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
1.5.22 Some unijunction oscillator circuit congurations. . . . . . . . . . . . . . . . . . . . 132
1.5.23 Unijunction transistor(UJT): (a) basic construction, (b) equivalent circuit. . . . . . 132

2.1.1 Inverter symbols: (a) inverter symbol, (b) alternate inverter symbol. . . . . . . . . . 133
2.1.2 Non-inverter symbols: (a) non-inverter symbol, (b) alternate non-inverter symbol. . 134
2.1.3 Ideal inverter: (a) operates from a single power supply, (b) voltage transfer charac-
teristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
2.1.4 Linearized voltage transfer characteristic (VTC) of an inverter . . . . . . . . . . . . 135
2.1.5 A VTC example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
2.1.6 Fan-in and fan-out: (a) Fan-in (b) Fan-out . . . . . . . . . . . . . . . . . . . . . . . 137
2.1.7 Input and output impedance model of an inverter. . . . . . . . . . . . . . . . . . . . 138
2.1.8 Static driving of multiple (identical) inverters. . . . . . . . . . . . . . . . . . . . . . 138
2.1.9 Dynamic driving of multiple (identical) inverters. . . . . . . . . . . . . . . . . . . . 139
2.1.10 Inverter with input and output currents shown. . . . . . . . . . . . . . . . . . . . . 139
2.1.11 Ideal transient response of an inverter. . . . . . . . . . . . . . . . . . . . . . . . . . 140
2.1.12 Switching speed denitions: (a) input pulse (b) output pulse. . . . . . . . . . . . . . 140
2.1.13 Propagation delay denitions: (a) input waveform (b) output response. . . . . . . . 141
2.1.14 Power dissipation in a logic gate with two power supplies. . . . . . . . . . . . . . . . 142
2.1.15 A diagram of logic families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
2.2.1 Diode symbols: (a) PN junction diode, (b) MN Schottky barrier diode. . . . . . . . 145
2.2.2 Diode cross sections: (a) PN junction diode, (b) MN Schottky barrier diode. . . . . 145
2.2.3 IV characteristics of the simplied diode model. . . . . . . . . . . . . . . . . . . . . 146
2.2.4 SPICE diode model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
2.2.5 Varactor diode (voltage dependent capacitor for VD < 0). . . . . . . . . . . . . . . . 147
2.2.6 Input clamping diodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
2.2.7 A level-shifting diodes example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
2.3.1 Three-dimensional cross-section (without metallization). . . . . . . . . . . . . . . . . 149
2.3.2 Multi-emitter NPN transistor cross-sections with junction isolation technology: (a)
BJT, (b) Schottky-clamped BJT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
2.3.3 Notation and symbols used for BJT transistors: (a) NPN transistor, (b) PNP transistor.150
2.3.4 Ebers-Moll NPN BJT model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
2.3.5 Reduced NPN BJT models for the four modes of operation: (a) Cuto (OFF), (b)
Forward Active (FA), (b) Reverse Active (RA), (d) Saturation (SAT). . . . . . . . . 155
2.3.6 Output IV characteristics (IC vs. VCE ) of a common-emitter NPN BJT transistor
with IB as a parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
2.3.7 A simple circuit for unknown BJT state example. . . . . . . . . . . . . . . . . . . . 157
2.3.8 A digital sub-circuit for known BJT states example. . . . . . . . . . . . . . . . . . . 158
2.3.9 A saturated BJT example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
2.3.10 TTL family NAND super-circuitry block diagram. . . . . . . . . . . . . . . . . . . . 159
2.3.11 Pull-up driver sub-circuits: (a) Passive pull-up, (b) Active pull-up, (c) Darlington
pair active pull-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
2.3.12 Fan-out current sinking for output-low pull-down driver. . . . . . . . . . . . . . . . 160

xi
2.3.13 Pull-down driver sub-circuits: (a) Passive pull-down, (b) Active pull-down. . . . . . 160
2.3.14 Discharge (or stored charge removal) sub-circuits: (a) Passive, (b) Active. . . . . . . 161
2.3.15 Active base driving circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
2.3.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
2.3.17 Currents leaving the power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
2.3.18 BJT logic gate for a power dissipation example. . . . . . . . . . . . . . . . . . . . . 163
2.4.1 Basic RTL inverter: (a) Circuit, (b) Voltage transfer characteristics. . . . . . . . . . 164
2.4.2 Basic RTL NOR gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
2.4.3 Basic RTL NAND gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
2.4.4 RTL Inverter in output high state with n identical load gates. . . . . . . . . . . . . 167
2.4.5 Basic RTL non-inverter: (a) Circuit, (b) Voltage transfer characteristics. . . . . . . . 168
2.4.6 Basic RTL OR gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
2.4.7 Basic RTL NAND gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
2.4.8 RTL inverter with active pull-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
2.5.1 Basic DTL inverter: (a) Circuit, (b) Voltage transfer characteristics. . . . . . . . . . 173
2.5.2 Basic DTL NAND gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
2.5.3 Modied DTL inverter with additional level-shifting diode and discharge path: (a)
Circuit, (b) Voltage transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
2.5.4 Transistor modied DTL inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
2.5.5 DTL NAND gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
2.5.6 DTL NAND gate in output-low state driving N identical load gates. . . . . . . . . . 177
2.6.1 Basic TTL inverter: (a) Circuit, (b) Voltage transfer characteristics. . . . . . . . . . 179
2.6.2 Basic TTL NAND gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
2.6.3 Standard TTL 5400/7400 series NAND gate with totem-pole output. . . . . . . . . 181
2.6.4 Voltage transfer characteristics of a standard TTL inverter given in Figure 2.6.3. . . 182
2.6.5 TTL NAND gate in output-low state driving N identical load gates. . . . . . . . . . 184
2.6.6 Open-collector TTL gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
2.6.7 Low power TTL (LTTL) with increased resistances. . . . . . . . . . . . . . . . . . . 187
2.6.8 54H00/74H00 high-speed TTL (LTTL) with smaller resistances and Darlington pair
active pull-up driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
2.7.1 Block diagram of a TTL AND gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
2.7.2 Circuit schematic of a standard 5408/7408 TTL AND gate. . . . . . . . . . . . . . . 190
2.7.3 Circuit symbol of a TTL AND gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
2.7.4 Voltage transfer characteristics of a standard TTL AND gate given in Figure 2.7.2. . 190
2.7.5 Standard 5402/7402 TTL NOR gate: (a) Circuit schematic, (b) Circuit symbol. . . 192
2.7.6 Standard 5432/7432 TTL OR gate: (a) Circuit schematic, (b) Circuit symbol. . . . 193
2.7.7 AOI TTL gate performing VOU T = VA VB + VC VD in Example 2.20. . . . . . . . . . . 194
2.7.8 Circuit symbol for VOU T = VA VB + VC VD in Example 2.20. . . . . . . . . . . . . . . 194
2.7.9 AOI TTL gate performing VOU T = VA VB + VC + VD VE VF in Example 2.21. . . . . . 195
2.7.10 AOI TTL gate performing VOU T = VA VB + VC + VD VE VF in Example 2.22. . . . . . 196
2.7.11 Circuit symbol for an XOR gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
2.7.12 Standard 5486/7486 TTL XOR gate. . . . . . . . . . . . . . . . . . . . . . . . . . . 198
2.7.13 Schmitt trigger inverter: (a) Noisy input and the corresponding inverting output volt-
age waveforms, (b) VTC characteristics exhibiting hysteresis having dierent thresh-
old levels VID and VIU for high-to-low and low-to-high transitions, respectively. . . . 199

xii
2.7.14 Basic emitter-coupled noninverting Schmitt Trigger: (a) Circuit, (b) VTC. . . . . . 199
2.7.15 Standard 5424/7424 Schmitt Trigger NAND gate. . . . . . . . . . . . . . . . . . . . 201
2.7.16 Circuit symbol for a Schmitt Trigger NAND gate. . . . . . . . . . . . . . . . . . . . 201
2.7.17 An example VTC for a standard Schmitt Trigger NAND gate. . . . . . . . . . . . . 202
2.7.18 Circuit symbol for a low-enabled tri-state buer (or noninverter). . . . . . . . . . . . 202
2.7.19 Circuit schematic for a low-enabled tri-state buer (or noninverter). . . . . . . . . . 203
2.7.20 Example usage of high-enabled tri-state buers: (a) Four-buers connected to a single
bus, (b)Case of TA is enabled, TB , TC and TD are disabled. . . . . . . . . . . . . . . 204
2.7.21 8-bit data bus driven by four 8-bit register outputs where one enable signal enables
or disable all 8-bit register outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

xiii
List of Examples

Example 1.1 (Gain Stability) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Example 1.2 (Voltage-Series Feedback) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Example 1.3 (Voltage-Series Feedback) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Example 1.4 (Voltage-Shunt Feedback) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Example 1.5 (Current-Series Feedback) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Example 1.6 (Current-Shunt Feedback) . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Example 1.7 (Dierential Amplier with Current Source) . . . . . . . . . . . . . . . . . 61

Example 1.8 (Dierential Amplier Example 2) . . . . . . . . . . . . . . . . . . . . . . . 66

Example 1.9 (Dierential Amplier Example 3) . . . . . . . . . . . . . . . . . . . . . . . 68

Example 1.10 (Dierential Amplier Example 4) . . . . . . . . . . . . . . . . . . . . . . . 68

Example 1.11 (Opamp Oset Elimination Example 1) . . . . . . . . . . . . . . . . . . . . 83

Example 1.12 (Opamp Oset Elimination Example 2) . . . . . . . . . . . . . . . . . . . . 84

Example 1.13 (Opamp Oset Elimination Example 3) . . . . . . . . . . . . . . . . . . . . 85

Example 1.14 (Thermal-to-Electrical Analogy) . . . . . . . . . . . . . . . . . . . . . . . . 111

Example 1.15 (Class B Power Amplier) . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Example 1.16 (FET Phase-Shift Oscillator Example) . . . . . . . . . . . . . . . . . . . . 119

Example 1.17 (Wien-Bridge Oscillator Example 1) . . . . . . . . . . . . . . . . . . . . . . 122

Example 1.18 (Wien-Bridge Oscillator Example 2) . . . . . . . . . . . . . . . . . . . . . . 122

Example 2.1 (VTC Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Example 2.2 (Fan-Out Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Example 2.3 (Diode Level-Shifting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Example 2.4 (Unknown BJT State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Example 2.5 (Known BJT States) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Example 2.6 (BJT-Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Example 2.7 (Power Dissipation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Example 2.8 (Basic RTL NAND Fan-In) . . . . . . . . . . . . . . . . . . . . . . . . . . 166

xiv
Example 2.9 (Basic RTL Fan-Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Example 2.10 (Basic RTL Power Dissipation) . . . . . . . . . . . . . . . . . . . . . . . . 168

Example 2.11 (RTL with Active Pull-Up Fan-Out) . . . . . . . . . . . . . . . . . . . . . 172

Example 2.12 (DTL NAND Voltage Input) . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Example 2.13 (DTL Fan-Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Example 2.14 (DTL Power Dissipation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Example 2.15 (Standard TTL VTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Example 2.16 (TTL Fan-Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Example 2.17 (TTL Power Dissipation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Example 2.18 (LTTL Power Dissipation) . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Example 2.19 (TTL NOR Power Dissipation) . . . . . . . . . . . . . . . . . . . . . . . . 192

Example 2.20 (TTL AOI Example 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Example 2.21 (TTL AOI Example 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Example 2.22 (TTL AOI Example 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Example 2.23 (Basic Emitter-Coupled Schmitt Trigger) . . . . . . . . . . . . . . . . . . . 200

Example 2.24 (Standard NAND Schmitt Trigger) . . . . . . . . . . . . . . . . . . . . . . 202

xv
List of Homeworks

Homework 1.1 (Current Mirror) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Homework 1.2 (Dierential Amplier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Homework 1.3 (Opamp Homework 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Homework 1.4 (Opamp (+ Feedback) Homework 2) . . . . . . . . . . . . . . . . . . . . . 75

Homework 1.5 (Opamp (+ Feedback) Homework 3) . . . . . . . . . . . . . . . . . . . . . 75

Homework 1.6 (Opamp Homework 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

xvi
Textbook

Analogue Circuits:

1. Sedra and Smith, Microelectronic Circuits , Oxford Press, 2009 (6th ed.)
2. Millman and Grabel, Microelectronics , McGraw-Hill

3. Millman and Halkias, Integrated Electronics , McGraw-Hill

4. Boylestad and Nashelsky, Electronic Devices and Circuit Theory , Prentice Hall, 8th ed.

Digital Circuits:

1. DeMassa and Ciccone, Digital Integrated Circuits , John Wiley & Sons.

xvii
Chapter 1
Analogue Electronics

1.1 Feedback and Feedback Ampliers

Before continuing further, we are going to classify the ampliers according to their input and output
signals. Determining the amplier type is very important for feedback design and analysis.

1.1.1 Amplier Models

Let us rst classify the amplier models according to their input and output signal types.

1. Voltage-Gain Amplier

• voltage input (i.e., voltage source at input)

• voltage output (i.e., voltage-controlled voltage source at output)

2. Transresistance Amplier

• current input (i.e., current source at input)

• voltage output (i.e., current-controlled voltage source at output)

3. Transconductance Amplier

• voltage input (i.e., voltage source at input)

• current output (i.e., voltage-controlled current source at output)

4. Current-Gain Amplier

• current input (i.e., current source at input)

• current output (i.e., current-controlled current source at output)

1
1.1.1.1 Voltage-Gain Amplier

Figure 1.1.1: Voltage-gain amplier

Here, vs and Rs are the voltage source and internal resistance of the voltage source; Ri , Av and Ro are
the input resistance, no-load gain and output resistance of the amplier; and RL is the load resistance.

• As, no-load voltage gain, Av is dened as

vo
Av = (1.1.1)
vi RL =∞

• Voltage gain with load, AV will be given as

vo RL
AV = = Av (1.1.2)
vi Ro + RL

• No-load overall voltage gain, Avs will be given as

vo Ri
Avs = = Av (1.1.3)
vs RL =∞ Rs + Ri

• Overall voltage gain, AVs will be given as

vo Ri RL
AVs = = Av (1.1.4)
vs Rs + Ri Ro + RL

• Ideally we want overall voltage gain AVs should be equal to the no-load voltage gain Av . Thus,
ideal input resistance Ri and ideal output resistance Ro of a voltage-gain amplier should be
innity and zero, respectively.

(
Ri → ∞
AVs → Av ⇒
Ro → 0

• Thus, for a good voltage-gain amplier Ri should be large (i.e., Ri  Rs ) and Ro should be
small (i.e., Ro  RL ).

2
1.1.1.2 Transresistance Amplier

Figure 1.1.2: Transresistance amplier

Here, is and Rs are the current source and internal resistance of the current source; Ri , Rm and Ro are
the input resistance, no-load gain and output resistance of the amplier; and RL is the load resistance.

• As, no-load transresistance gain, Rm is dened as

vo
Rm = (1.1.5)
ii RL =∞

• Transresistance gain with load, RM will be given as

vo RL
RM = = Rm (1.1.6)
ii Ro + RL

• No-load overall gain, Rms will be given as

vo Rs
Rms = = Rm (1.1.7)
is RL =∞ Rs + Ri

• Overall transresistance gain, RMs will be given as

vo Rs RL
RMs = = Rm (1.1.8)
is Rs + Ri Ro + RL

• Ideally we want overall transresistance gain RMs should be equal to the no-load transresistance
gain Rm . Thus, ideal input resistance Ri and ideal output resistance Ro of a transresistance
amplier should be both zero.

(
Ri → 0
RMs → Rm ⇒
Ro → 0

• Thus, for a good transresistance amplier Ri should be small (i.e., Ri  Rs ) and Ro should be
small also (i.e., Ro  RL ).

3
1.1.1.3 Transconductance Amplier

Figure 1.1.3: Transconductance amplier

Here, vs and Rs are the voltage source and internal resistance of the voltage source; Ri , Gm and Ro are
the input resistance, no-load gain and output resistance of the amplier; and RL is the load resistance.

• As, no-load transconductance gain, Gm is dened as

io
Gm = (1.1.9)
vi RL =0

• Transconductance gain with load, GM will be given as

io Ro
GM = = Gm (1.1.10)
vi Ro + RL

• No-load overall transconductance gain, Gms will be given as

io Ri
Gms = = Gm (1.1.11)
vs RL =0 Rs + Ri

• Overall transconductance gain, GMs will be given as

io Ri Ro
GMs = = Gm (1.1.12)
vs Rs + Ri Ro + RL

• Ideally we want overall transconductance gain GMs should be equal to the no-load transconduc-
tance gain Gm . Thus, ideal input resistance Ri and ideal output resistance Ro of a transconduc-
tance amplier should be both innity.

(
Ri → ∞
GMs → Gm ⇒
Ro → ∞

• Thus, for a good transconductance amplier Ri should be large (i.e., Ri  Rs ) and Ro should
be large also (i.e., Ro  RL ).

4
1.1.1.4 Current-Gain Amplier

Figure 1.1.4: Current-gain amplier

Here, is and Rs are the current source and internal resistance of the current source; Ri , Ai and Ro are
the input resistance, no-load gain and output resistance of the amplier; and RL is the load resistance.

• As, no-load current gain, Ai is dened as

io
Ai = (1.1.13)
ii RL =0

• Current gain with load, AI will be given as

io Ro
AI = = Ai (1.1.14)
ii Ro + RL

• No-load overall current gain, Ais will be given as

io Rs
Ais = = Ai (1.1.15)
is RL =0 Rs + Ri

• Overall current gain, AIs will be given as

io Rs Ro
AIs = = Ai (1.1.16)
is Rs + Ri Ro + RL

• Ideally we want overall current gain AIs should be equal to the no-load current gain Ai . Thus,
ideal input resistance Ri and ideal output resistance Ro of a current-gain amplier should be
zero and innity, respectively.

(
Ri → 0
AIs → Ai ⇒
Ro → ∞

• Thus, for a good current-gain amplier Ri should be small (i.e., Ri  Rs ) and Ro should be
large (i.e., Ro  RL ).

5
1.1.2 Negative Feedback Concepts

Figure 1.1.5: Negative feedback block diagram

This block diagram is called negative feedback, because the feedback signal Xf subtracted from the
input signal X as seen in the gure above. Here, A is the open-loop gain (i.e., gain without feedback),
X, Y and Xf represents the input, output and feedback signals respectively, and Xi is the feedback
reduced input signal.
The eects of the negative feedback on an amplier can be summarized as follows.

Disadvantages:
◦ Lower gain

Advantages:
◦ More stable gain

◦ Reduced distortion

◦ Improved frequency response

◦ Improved input impedance

◦ Improved output impedance

◦ More linear operation

1.1.2.1 Closed-loop Gain, Af

Y
From the Figure 1.1.5 we can calculate the closed-loop gain (i.e., gain with feedback), Af = as
X
follows

Y = AXi (1.1.17)

Xf = βY (1.1.18)

X i = X − Xf (1.1.19)

6
From the three equations above, we can on obtain the gain with feedback Af as follows

Y A
Af = = (1.1.20)
X 1 + βA

If βA  1 then, above equation reduces to

1
Af ≈ . (1.1.21)
β

So, in order to have Af > 1, β < 1 is required.

1.1.2.2 Negative Feedback Improvements

We are going to investigate and prove the following three improvements of the negative feedback

1. Improved Gain Stability

2. Reduced Distortion

3. Increased Bandwidth

Improved Gain Stability

∆Af
We need to nd the closed-loop gain stability (relative change of the gain), i.e., the ratio . In
Af
dAf
order to derive this quantity, we need to rst nd the derivative .
dA
 
A
dAf d 1+βA
= (1.1.22)
dA dA
1
= . . . using the chain rule of derivatives (1.1.23)
(1 + βA)2
A 1
= . . . multiplying the numerator and denominator by A (1.1.24)
1 + βA A(1 + βA)
Af 1
= (1.1.25)
A 1 + βA
From the result above, we can obtain the following expression for the closed-loop gain stability in
terms of the open-loop gain stability

dAf 1 dA
= (1.1.26)
Af 1 + βA A

Thus, the closed-loop gain stability is improved by a factor of (1 + βA) compared to the open-loop
gain stability.

7
 Example 1.1: Assume a system where open-loop gain equals A = 1000 and changes by 20%
due to a temperature change. Consider a negative feedback closed-loop system with β = 0.1
and calculate the change for the closed-loop gain Af for the same conditions.

∆Af
Solution: We can nd from the equation derived previously. Thus,
Af
∆Af 1 ∆A
=
Af 1 + βA A
1
= 20%
1 + 0.1 × 1000
= 0.2%.
Thus, the closed-loop gain (although smaller) is much more stable than the open-loop gain.

A↑ ⇒ Y ↑ ⇒ Xf ↑ ⇒ Xi ↓ ⇒ Y ↓

Above gure explains the reason for the stability improvement. If open-loop gain A increases,
then output Y increases. If output Y increases, then feedback signal Xf increases. If feedback
signal Xf increases, then internal input signal Xi decreases. If internal input signal Xi decreases
the eventually the output signal Y decreases. Hence, this process provides stability.

Reduced Distortion
Here we are going to assume that we have some additive distortion D in the open-loop system, i.e.,

Y = AX + D (1.1.27)

We need to investigate the same problem when we employ a negative feedback for this system. Let
us start with writing the closed-loop equations from the Figure 1.1.5

Y = AXi + D (1.1.28)

Xf = βY (1.1.29)

Xi = X − X f (1.1.30)

From the three equations above, we can on obtain the output Y as follows

A D
Y = X+ (1.1.31)
1 + βA 1 + βA
Thus, distortion in the closed-loop system is reduced by a factor of (1 + βA).

8
Increased Bandwidth

Figure 1.1.6: Amplier bandwidth example

Bandwidth BW is the dierence between the higher cut-o frequency fH and the lower cut-o fre-
quency fL of the amplier, i.e.,

BW = fH − fL . (1.1.32)

So, if fH gets higher and/or fL gets lower, then the bandwidth increases.
We can consider both ends of the amplitude response in Figure 1.1.6 separately (as fH  fL ).
The lower end of the amplitude response is a high-pass lter, and the higher end of the amplitude
response is a low-pass lter.
Let us rst consider the lower-end high-pass system like a simple RC-lter and write down the
open-loop frequency response AH (f ) accordingly (f is the frequency of the input signal)

Am
AH (f ) = (1.1.33)
fL
1−j
f
where Am and fL are the midband gain and lower cut-o frequency of the open-loop system, respec-
tively. We know that the closed-loop gain AHf (f ) is given by

AH (f )
AHf (f ) = . (1.1.34)
1 + βAH (f )
By inserting AH (f ) into the equation and rearranging it, we arrive at

Amf
AHf (f ) = (1.1.35)
fLf
1−j
f

9
where Amf and fLf are the midband gain and lower cut-o frequency of the closed-loop system, and
given by
Am
Amf = (1.1.36)
1 + βAm
and
fL
fLf = (1.1.37)
1 + βAm
respectively. Thus, low-frequency fLf of the closed-loop system is reduced by a factor of (1 + βAm ).
Let us now consider the upper-end low-pass system like a simple RC-lter and write down the
open-loop frequency response AL (f ) accordingly (f is the frequency of the input signal)

Am
AL (f ) = (1.1.38)
f
1+j
fH
where Am and fH are the midband gain and higher cut-o frequency of the open-loop system, respec-
tively. We know that the closed-loop gain ALf (f ) is given by

AL (f )
ALf (f ) = . (1.1.39)
1 + βAL (f )

Similarly, by inserting AL (f ) into the equation and rearranging it, we arrive at

Amf
ALf (f ) = (1.1.40)
f
1+j
fHf

where Amf and fHf are the midband gain and higher cut-o frequency of the closed-loop system, and
given by
Am
Amf = (1.1.41)
1 + βAm
and
fHf = (1 + βAm ) fH (1.1.42)

respectively. Thus, high-frequency fHf of the closed-loop system is increased by a factor of (1 + βAm ).
Consequently, we have showed that negative feedback increases the bandwidth.
NOTE: The gain-bandwidth product stays (nearly) constant
Af × BWf ∼
= A × BW = constant (1.1.43)

as BWf ≈ fHf and BW ≈ fH .

10
1.1.2.3 Sampling and Mixing

Figure 1.1.7: Sampling and mixing diagram in a negative feedback system

The output signal is sampled and fed back to the system and mixed with the input signal. Here,
we are going to analyze the possible sampling and mixing types.

1.1.2.4 Sampling Types

As there two types of electrical signals, i.e., voltage and current, there are two types of sampling.
In order to sample output voltage we need to connect the feedback network in parallel (i.e., shunt
connection) with the output (like a voltmeter). Similarly, in order to sample output current we
need to connect the feedback network in series with the output (like an ammeter).

1. Voltage-sampling (Shunt-sampling or parallel-sampling)

2. Current-sampling (Series-sampling)
Voltage-Sampling Example

11
 Figure 1.1.8: Voltage-sampling example

Current-Sampling Example

Figure 1.1.9: Current-sampling example

1.1.2.5 Mixing Types

We can mix (i.e., connect) the feedback network output to the input in parallel or in series. In order to
mix voltage feedback signal we need to connect the feedback network in series to the input (remember
KVL). Similarly, in order to mix current feedback signal we need to connect the feedback network in
parallel (i.e., shunt connection) to the input (remember KCL).
1. Series-mixing (voltage-mixing)
2. Shunt-mixing (parallel-mixing or current-mixing)
Series-Mixing Example

12
 Figure 1.1.10: Series-mixing example

Shunt-Mixing Example

Figure 1.1.11: Shunt-mixing example

1.1.2.6 Negative Feedback Types

Negative feedback types are classied according to the Sampling-Mixing type pairs. As there are
two types of sampling and two types mixing, there four types feedback types.

1. Voltage-Series Feedback
2. Voltage-Shunt Feedback (voltage-parallel feedback)
3. Current-Series Feedback
4. Current-Shunt Feedback (current-parallel feedback)

13
1.1.3 Voltage-Series Feedback

Figure 1.1.12: Voltage-series feedback: Block diagram

Voltage-series feedback amplier is actually a closed-loop voltage-gain amplier as shown below. We

are going to nd the derive the no-load gain Avf , input resistance Rif and output resistance Rof of
this closed-loop system.

Figure 1.1.13: Voltage-series feedback amplier model (i.e., closed-loop voltage-gain amplier)

14
 Figure 1.1.14: Voltage-series feedback: Block diagram with open-loop amplier parameters

Let us derive no-load gain Avf , input resistance Rif and output resistance Rof of the voltage-series
feedback system in terms of the open-loop amplier parameters Av , Ri and Ro .
Avf =? Rif =? Rof =?

1.1.3.1 No-load Gain

Figure 1.1.15: Voltage-series feedback: No-load gain calculation diagram

From the above gure, we can quickly derive the closed-loop no-load gain Avf where

vo vo Av vi
Avf = = =
vif RL =∞ vi + vf (1 + βAv )vi

15
as
Av
Avf = (1.1.44)
1 + βAv

1.1.3.2 Input Resistance

Figure 1.1.16: Voltage-series feedback: Input resistance calculation diagram

From the above gure, we can quickly derive the closed-loop input resistance Rif
vif vi + vf (1 + βAv )vi vi
Rif = = = = (1 + βAv )
ii RL =∞ ii ii ii
as
Rif = (1 + βAv ) Ri (1.1.45)

Loading Eect of Negative Feedback

• If a load RL is connected, then the gain will drop due to the voltage divider conguration
between Ro and RL . Hence, closed-loop input resistance will be aected due to the feedback.

Consequently, closed-loop input resistance Rif will be given by

Rif = (1 + βAV ) Ri (1.1.46)

where
RL
AV = Av (1.1.47)
RL + Ro

16
1.1.3.3 Output Resistance

Figure 1.1.17: Voltage-series feedback: Output resistance calculation diagram

We can calculate the closed-loop output resistance (i.e., as a Thévenin equivalent resistance) by using
the test voltage method as shown in the gure above. Note that as the feedback network is ideal,
internal resistance of the feedback network is innity. So, ix = 0 and io = i1 + ix = i1 . Also as vif = 0,
vi = −vf = −βvo . Hence, output resistance Rof
vo vo vo Ro vo Ro vo
Rof = = = = =
io RL =vo ,vif =0 i1 vo − Av vi vo − Av (−βvo ) (1 + βAv )vo
Ro
is derived as
Ro
Rof = (1.1.48)
1 + βAv

Eect of Source Resistance under Negative Feedback

• If a voltage source vs with an internal resistance Rs is connected at the input, then the gain will
drop due to the voltage divider conguration between Ri and Rs . Hence, closed-loop output
resistance will be aected due to the feedback.

Consequently, closed-loop output resistance Rof will be given by

Ro
Rof = (1.1.49)
1 + βAvs

where
Ri
Avs = Av (1.1.50)
Rs + Ri

17
1.1.4 Voltage-Shunt Feedback

Figure 1.1.18: Voltage-shunt feedback: Block diagram

Voltage-shunt feedback amplier is actually a closed-loop transresistance amplier as shown below.

We are going to nd the derive the no-load gain Rmf , input resistance Rif and output resistance Rof
of this closed-loop system.

Figure 1.1.19: Voltage-shunt feedback amplier model (i.e., closed-loop transresistance amplier)

18
 Figure 1.1.20: Voltage-shunt feedback: Block diagram with open-loop amplier parameters

Let us derive no-load gain Rmf , input resistance Rif and output resistance Rof of the voltage-shunt
feedback system in terms of the open-loop amplier parameters Rm , Ri and Ro .
Rmf =? Rif =? Rof =?

1.1.4.1 No-load Gain

Figure 1.1.21: Voltage-shunt feedback: No-load gain calculation diagram

From the above gure, we can quickly derive the closed-loop no-load gain Rmf where

vo vo Rm ii
Rmf = = =
iif RL =∞ ii + if (1 + βRm )ii

19
as
Rm
Rmf = (1.1.51)
1 + βRm

1.1.4.2 Input Resistance

Figure 1.1.22: Voltage-shunt feedback: Input resistance calculation diagram

From the above gure, we can quickly derive the closed-loop input resistance Rif
vi vi vi
Rif = = =
iif RL =∞ ii + if (1 + βRm )ii
as
Ri
Rif = (1.1.52)
1 + βRm

Loading Eect of Negative Feedback

• If a load RL is connected, then the gain will drop due to the voltage divider conguration
between Ro and RL . Hence, closed-loop input resistance will be aected due to the feedback.

Consequently, closed-loop input resistance Rif will be given by

Ri
Rif = (1.1.53)
1 + βRM

where
RL
RM = Rm (1.1.54)
RL + Ro

20
1.1.4.3 Output Resistance

Figure 1.1.23: Voltage-shunt feedback: Output resistance calculation diagram

We can calculate the closed-loop output resistance (i.e., as a Thévenin equivalent resistance) by using
the test voltage method as shown in the gure above. Note that as the feedback network is ideal,
internal resistance of the feedback network is innity. So, ix = 0 and io = i1 + ix = i1 . Also as iif = 0,
ii = −if = −βvo . Hence, output resistance Rof
vo vo vo Ro vo Ro vo
Rof = = = = =
io RL =vo ,iif =0 i1 vo − Rm ii vo − Rm (−βvo ) (1 + βRm )vo
Ro
is derived as
Ro
Rof = (1.1.55)
1 + βRm

Eect of Source Resistance under Negative Feedback

• If a current source is with an internal resistance Rs is connected at the input, then the gain will
drop due to the current divider conguration between Ri and Rs . Hence, closed-loop output
resistance will be aected due to the feedback.

Consequently, closed-loop output resistance Rof will be given by

Ro
Rof = (1.1.56)
1 + βRms

where
Rs
Rms = Rm (1.1.57)
Rs + Ri

21
1.1.5 Current-Series Feedback

Figure 1.1.24: Current-series feedback: Block diagram

Current-series feedback amplier is actually a closed-loop transconductance amplier as shown below.

We are going to nd the derive the no-load gain Gmf , input resistance Rif and output resistance Rof
of this closed-loop system.

Figure 1.1.25: Current-series feedback amplier model (i.e., closed-loop transconductance amplier)

22
 Figure 1.1.26: Current-series feedback: Block diagram with open-loop amplier parameters

Let us derive no-load gain Gmf , input resistance Rif and output resistance Rof of the current-series
feedback system in terms of the open-loop amplier parameters Gm , Ri and Ro .

Gmf =? Rif =? Rof =?

1.1.5.1 No-load Gain

Figure 1.1.27: Current-series feedback: No-load gain calculation diagram

23
From the above gure, we can quickly derive the closed-loop no-load gain Gmf where

io io Gm vi
Gmf = = =
vif RL =0 vi + vf (1 + βGm )vi
as
Gm
Gmf = (1.1.58)
1 + βGm

1.1.5.2 Input Resistance

Figure 1.1.28: Current-series feedback: Input resistance calculation diagram

From the above gure, we can quickly derive the closed-loop input resistance Rif

vif vi + vf (1 + βGm )vi vi

Rif = = = = (1 + βGm )
ii RL =0 ii ii ii
as
Rif = (1 + βGm ) Ri (1.1.59)

Loading Eect of Negative Feedback

• If a load RL is connected, then the gain will drop due to the current divider conguration
between Ro and RL . Hence, closed-loop input resistance will be aected due to the feedback.

Consequently, closed-loop input resistance Rif will be given by

24
 Rif = (1 + βGM ) Ri (1.1.60)

where
Ro
GM = Gm (1.1.61)
RL + Ro

1.1.5.3 Output Resistance

Figure 1.1.29: Current-series feedback: Output resistance calculation diagram

We can calculate the closed-loop output resistance (i.e., as a Thévenin equivalent resistance) by using
the test voltage method as shown in the gure above. Note that as the feedback network is ideal,
internal resistance of the feedback network is zero. So, vx = 0 and vo = i1 Ro + vx = i1 Ro . Also as
vif = 0, vi = −vf = βio . Hence, output resistance Rof

vo i1 Ro (io + Gm vi )Ro (io + Gm βio )Ro

Rof = = = =
io RL =vo ,vif =0 io io io

is derived as
Rof = (1 + βGm ) Ro (1.1.62)

Eect of Source Resistance under Negative Feedback

• If a voltage source vs with an internal resistance Rs is connected at the input, then the gain will
drop due to the voltage divider conguration between Ri and Rs . Hence, closed-loop output
resistance will be aected due to the feedback.

25
 Consequently, closed-loop output resistance Rof will be given by

Rof = (1 + βGms ) Ro (1.1.63)

where
Ri
Gms = Gm (1.1.64)
Rs + Ri

1.1.6 Current-Shunt Feedback

Figure 1.1.30: Current-shunt feedback: Block diagram

Current-shunt feedback amplier is actually a closed-loop current-gain amplier as shown below. We

are going to nd the derive the no-load gain Aif , input resistance Rif and output resistance Rof of this
closed-loop system.

Figure 1.1.31: Current-shunt feedback amplier model (i.e., closed-loop current-gain amplier)

26
 Figure 1.1.32: Current-shunt feedback: Block diagram with open-loop amplier parameters

Let us derive no-load gain Aif , input resistance Rif and output resistance Rof of the current-shunt
feedback system in terms of the open-loop amplier parameters Ai , Ri and Ro .

Aif =? Rif =? Rof =?

1.1.6.1 No-load Gain

Figure 1.1.33: Current-shunt feedback: No-load gain calculation diagram

From the above gure, we can quickly derive the closed-loop no-load gain Aif where

io io Ai ii
Aif = = =
iif RL =0 ii + if (1 + βAi )ii

27
as
Ai
Aif = (1.1.65)
1 + βAi

1.1.6.2 Input Resistance

Figure 1.1.34: Current-shunt feedback: Input resistance calculation diagram

From the above gure, we can quickly derive the closed-loop input resistance Rif
vi vi vi
Rif = = =
iif RL =0 ii + if (1 + βAi )ii
as
Ri
Rif = (1.1.66)
1 + βAi

Loading Eect of Negative Feedback

• If a load RL is connected, then the gain will drop due to the current divider conguration
between Ro and RL . Hence, closed-loop input resistance will be aected due to the feedback.

Consequently, closed-loop input resistance Rif will be given by

Ri
Rif = (1.1.67)
1 + βAI

where
Ro
AI = Ai (1.1.68)
RL + Ro

28
1.1.6.3 Output Resistance

Figure 1.1.35: Current-shunt feedback: Output resistance calculation diagram

We can calculate the closed-loop output resistance (i.e., as a Thévenin equivalent resistance) by using
the test voltage method as shown in the gure above. Note that as the feedback network is ideal,
internal resistance of the feedback network is zero. So, vx = 0 and vo = i1 Ro + vx = i1 Ro . Also as
iif = 0, ii = −if = βio . Hence, output resistance Rof
vo i1 Ro (io + Ai ii )Ro (io + Ai βio )Ro
Rof = = = =
io RL =vo ,iif =0 io io io

is derived as
Rof = (1 + βAi ) Ro (1.1.69)

Eect of Source Resistance under Negative Feedback

• If a current source is with an internal resistance Rs is connected at the input, then the gain will
drop due to the current divider conguration between Ri and Rs . Hence, closed-loop output
resistance will be aected due to the feedback.

Consequently, closed-loop output resistance Rof will be given by

Rof = (1 + βAis ) Ro (1.1.70)

where
Rs
Ais = Ai (1.1.71)
Rs + Ri

29
1.1.7 Summary of Closed-loop Input and Output Resistances
Table below summarizes the closed-loop input and output resistances for each type of feedback.

Figure 1.1.36: Summary table for closed-loop input and output resistance expressions

1.1.8 Analysis of Negative Feedback

The following steps needs to be taken during the analysis of negative feedback.

1. Recognize the type of feedback

2. Derive open-loop circuit (i.e., circuit without feedback)

3. Ensure suitability of the input signal source

4. Obtain open-loop small-signal equivalent circuit

5. Find feedback gain β = Xf /Y

6. Calculate open-loop parameters A, Ri and Ro

7. Calculate closed-loop parameters Af , Rif and Rof

1.1.8.1 Recognize the type of feedback

a) Identify the common circuit elements (i.e., feedback network) in between the input and output
loops.

b) Determine input-mixing type (i.e., type of feedback signal Xf )

◦ Series-mixing (feedback signal is voltage, vf )

− If the input voltage source vs is connected to the output with an element in series

- e.g., when a circuit element, like RE or RS , present in the emitter/source terminal

of the rst transistor when the input is from the base/gate terminal.

◦ Shunt-mixing (feedback signal is current, if )

30
 − If the output-circuit is wired to the input circuit allowing the feedback current if to
ow

- e.g., collector-feedback conguration or drain-feedback conguration

c) Determine output-sampling type

− Voltage-sampling (shunt-connection)
? If Xf = 0 when vo = 0 V (i.e., RL = 0 Ω)
− Current-sampling (series-connection)
? If Xf = 0 when io = 0 A (i.e., RL = ∞ Ω)
NOTE 1: If both tests hold, then select the one where feedback gain β does not contain
the load (or eective load) in its expression.

NOTE 2: If the feedback network is connected in parallel to the output, then it is

voltage-sampling. Similarly, if the feedback network is connected in series to the output,
then it is current-sampling

1.1.8.2 Derive open-loop circuit

a) Obtain the open-loop input circuitry
◦ Voltage-sampling
− Make Xf = 0 by making vo = 0, i.e., short-circuit the output connection.

Figure 1.1.37: Obtaining the open-loop input circuitry under voltage-sampling

◦ Current-sampling
− Make Xf = 0 by making io = 0, i.e., open-circuit the output connection.

31
 Figure 1.1.38: Obtaining the open-loop input circuitry under current-sampling

b) Obtain the open-loop output circuitry

◦ Series-mixing
− Make the reverse feedback signal Yf = 0 by making ii =0 where Y f = βr i i and βr is the
reverse feedback gain, i.e., open-circuit the input connection.

Figure 1.1.39: Obtaining the open-loop output circuitry under series-mixing

◦ Shunt-mixing
− Make the reverse feedback signal Yf = 0 by making vi = 0 where Y f = βr v i and βr is
the reverse feedback gain, i.e., short-circuit the input connection.

32
 Figure 1.1.40: Obtaining the open-loop output circuitry under shunt-mixing

NOTE: According to the connection type, always short-circuit a shunt-connection (or

parallel-connection) and always open-circuit a series-connection in order to eliminate the
eect of the observable. This is true for both output and input connections of the feedback
network.

c) Then draw the open-loop circuit by putting the input circuitry and output circuitry together

i. Open-loop circuit diagram for voltage-series feedback

Figure 1.1.41: Open-loop circuit diagram for voltage-series feedback

ii. Open-loop circuit diagram for voltage-shunt feedback

33
 Figure 1.1.42: Open-loop circuit diagram for voltage-shunt feedback

iii. Open-loop circuit diagram for current-series feedback

Figure 1.1.43: Open-loop circuit diagram for current-series feedback

iv. Open-loop circuit diagram for current-shunt feedback

Figure 1.1.44: Open-loop circuit diagram for current-shunt feedback

34
1.1.8.3 Ensure suitability of the input signal source
If feedback signal Xf is a

◦ Voltage signal (in the case of series-mixing)

− Use a Thévenin voltage source,
◦ Current signal (in the case of shunt-mixing)
− Use a Norton current source.
NOTE: If necessary, perform source transformation (voltage source ↔ current source).
1.1.8.4 Obtain open-loop small-signal equivalent circuit
Replace each active device (e.g. BJT, JFET, MOSFET etc.) in the open-loop circuit by their
appropriate small-signal model and draw the open-loop small signal equivalent circuit.

1.1.8.5 Find feedback gain β

Xf
• Obtain feedback gain β=
Y
◦ Feedback circuit cannot include either the source resistance Rs or the load resistance RL .
− i.e., β 6= β(Rs , RL ), in other words, β cannot be a function of Rs or RL .
NOTE: Any external circuit element (or equivalent element) via which we obtain the output
voltage vo and output current io will be the eective load in the circuit, even though it was
not labelled explicitly as RL .

1.1.8.6 Summary of feedback amplier analysis

The table below shows the summary of the feedback amplier analysis

Figure 1.1.45: Summary table for negative feedback amplier analysis

35
1.1.9 Examples
Example 1.2: Determine the feedback type and derive the open-loop and closed-loop amplier
parameters (i.e., input resistance, output resistance and gain) for the source follower circuit
below.

Figure 1.1.46: A source follower circuit (a voltage-series feedback example).

Solution: Output and input networks have one common element R which provides feedback
in this circuit. It is connected in series to the input circuitry. The feedback signal vf is the
voltage across resistor R. Output signal sampled is output voltage vo (because if output current
was sampled, then the feedback gain β will be equal to the value of resistor R, but R is the
eective load in this circuit and feedback network cannot include the load). So, this circuit has
voltage-series feedback.
Feedback network's input connection is between the JFET source terminal and the ground.
Similarly, feedback network's output connection is also between the JFET source terminal and
the ground terminal. In order to obtain the open-loop input circuitry we short circuit the output
connection terminals of the feedback network. Then, to obtain the open-loop output circuitry
we disconnect the input connection terminals of the feedback network (so, resistor R becomes
part of the open-loop output circuitry). Then, as shown in Figure 1.1.41 e put the open-loop
input and output circuitries together and we obtain the initial open-loop circuit (i.e., circuit
without feedback) below. Note that, we have to indicate the feedback signal vf at the output
circuitry of the open-loop circuit with the correct polarity.

36
 Figure 1.1.47: Initial open-loop circuit of the circuit given in Figure 1.1.46.

Now, let us replace the JFET transistor with its small-signal equivalent model and obtain the
open-loop small-signal equivalent circuit below

Figure 1.1.48: Open-loop small-signal equivalent circuit of Figure 1.1.46.

vf
Now, the feedback gain β is given by β= =1.
vo

Note that, as output current ows through and output voltage is across R, R is the eective
load, i.e., RL ≡ R .

From the gure above let us calculate the open-loop amplier parameters Ri , Ro and Av .
vi vo vo
Ri = =∞ Ro = = rds Av = = gm rds
ii RL =∞ io RL =vo ,vs =0 vi RL =∞

Now, let us calculate the closed-loop amplier parameters Rif , Rof and Avf using the voltage-
series feedback formulas derived before.

37
 Rif = (1 + βAV ) Ri = [1 + gm (rds ||R)] · ∞ = ∞

Ro rds 1
Rof = = ≈
1 + βAvs 1 + gm rds gm

Av gm rds
Avf = = ≈1
1 + βAv 1 + gm rds

Figure 1.1.49: Equivalent closed-loop amplier block diagram of the circuit given in Figure 1.1.46.

From the closed-loop amplier diagram above, we can also nd the overall closed-loop voltage
gain AVsf , as

Rif RL
AVsf = Avf
Rs + Rif Rof + RL
R
= Avf
Rof + R

Example 1.3: Determine the feedback type, derive the open-loop circuit and nd feedback
gain β for the feedback amplier shown below.

Figure 1.1.50: A multistage amplier system (a voltage-series feedback example).

38
Solution: Feedback type is voltage-series feedback and feedback network, consisting of resistors
R1 and R2 , connects the output and input networks to each other. Consequently, open-loop
circuit is derived as shown below

Figure 1.1.51: Open-loop circuit of the circuit given in Figure 1.1.50.

vf R1
Thus, feedback gain β is found as β= = .
vo R1 + R2

Example 1.4: Determine the feedback type and derive the open-loop and closed-loop amplier
parameters (i.e., input resistance, output resistance and gain) for the collector feedback circuit
below.

Figure 1.1.52: A collector feedback circuit (a voltage-shunt feedback example)

Solution: Output and input network have one common element R0 which provides feedback
in this circuit. It is connected in parallel (i.e., shunt connection) to the input circuitry. The
feedback signal if is the current through resistor R0 . Output signal sampled is output voltage
vo . So, this circuit has voltage-shunt feedback.
39
Feedback network's input connection is between the BJT base terminal and the ground. Sim-
ilarly, feedback network's output connection is between the BJT collector terminal and the
ground. In order to obtain the open-loop input circuitry, we short circuit the output connection
terminals of the feedback network. Then, to obtain the open-loop output circuitry we short
circuit the input connection terminals of the feedback network. Then, as shown in Figure 1.1.42
e put the open-loop input and output circuitries together and we obtain the initial open-loop
circuit (i.e., circuit without feedback) below. Note that, we have transformed the input voltage
source to a current source as feedback signal is a current signal and also indicated the feedback
signal if at the output circuitry of the open-loop circuit with the correct direction.

Figure 1.1.53: Initial open-loop circuit of the circuit given in Figure 1.1.52.

if if 1
Now, the feedback gain β is given by β= = 0
=− 0 .
vo −if R R

Note that, as output current ows through and output voltage is across RC , RC is the eective
load, i.e., RL ≡ RC .

From the gure above let us calculate the open-loop amplier parameters Ri , Ro and Rm .
vi vo 1
Ri = = R0 ||hie Ro = = R0 ||
ii RL =∞ io RL =vo ,is =0 hoe

R0
 
vo 0 1
Rm = = −hfe R ||
ii RL =∞ hoe R0 + hie

Now, let us calculate the closed-loop amplier parameters Rif , Rof and Rmf using the voltage-
shunt feedback formulas derived before.

40
 Ri R0 ||hie hie
Rif = = ≈
1 + βRM hfe RC RC
1 + (R0 ||1/hoe ) 0 0
1 + hfe 0
R + hie (R ||1/hoe ) + RC R

R0 ||1/hoe Ri R0
 
Ro
Rof = = ≈ 1+
1 + βRms Rs hfe Rs hfe
1+ (R0 ||1/hoe ) 0
Rs + Ri R + hie

hfe R0
− (R0 ||1/hoe )
Rm R0 + hie
Rmf = = ≈ −R0
1 + βRm h fe
1 + (R0 ||1/hoe ) 0
R + hie

Figure 1.1.54: Equivalent closed-loop amplier block diagram of the circuit given in Figure 1.1.52.

From the closed-loop amplier diagram above, we can also nd the overall closed-loop transre-
sistance gain RMsf , as

vo Rs RC
RMsf = = Rmf
is Rs + Rif Rof + RC
vs
where is =
Rs
Thus, overall closed-loop voltage gain AVsf will be given by

vo vo 1
AVsf = = = RMsf
vs is Rs Rs

Example 1.5: Determine the feedback type and derive the open-loop and closed-loop amplier
parameters (i.e., input resistance, output resistance and gain) for the common emitter circuit
below.

41
 Figure 1.1.55: A common emitter circuit (a current-series feedback example).

Solution: Output and input networks have one common element RE which provides feedback
in this circuit. It is connected in series to the input circuitry. The feedback signal vf is the
voltage across resistor RE . Output signal sampled is output current io . So, this circuit has
current-series feedback.
Feedback network's input connection is between the BJT emitter terminal and the ground. Sim-
ilarly, feedback network's output connection is also between the BJT emitter terminal and the
ground. In order to obtain the open-loop input circuitry, we disconnect the output connection
terminals of the feedback network. Then, to obtain the open-loop output circuitry we also dis-
connect the input connection terminals of the feedback network. Then, as shown in Figure 1.1.43
e put the open-loop input and output circuitries together and we obtain the initial open-loop
circuit (i.e., circuit without feedback) below. Note that, have to indicate the feedback signal vf
at the output circuitry of the open-loop circuit with the correct polarity.

Figure 1.1.56: Initial open-loop circuit of the circuit given in Figure 1.1.55.

42
Now, let us replace the BJT transistor with its small-signal equivalent model and obtain the
open-loop small-signal equivalent circuit below

Figure 1.1.57: Open-loop small-signal equivalent circuit of Figure 1.1.55.

vf −RE io
Now, the feedback gain β is given by β= = = −RE .
io io

Note that, as output current ows through and output voltage is across RL , RL is the eective
load.

From the gure above let us calculate the open-loop amplier parameters Ri , Ro and Gm .
vi vo
Ri = = RE + hie Ro = = 1/hoe + RE
ii RL =0 io RL =vo ,vs =0

io 1/hoe hfe
Gm = =−
vi RL =0 1/hoe + RE RE + hie
−hfe
≈
RE + hie

Now, let us calculate the closed-loop amplier parameters Rif , Rof and Gmf using the current-
series feedback formulas derived before.

 
hfe RE 1/hoe + RE
Rif = (1 + βGM ) Ri = 1 + (RE + hie )
RE + hie 1/hoe + RE + RL
≈ (hfe + 1) RE + hie

 
RE + hie hfe RE
Rof = (1 + βGms ) Ro = 1 + (1/hoe + RE ) ≈ ∞
Rs + RE + hie RE + hie

−hfe
Gm RE + hie 1
Gmf = = ≈−
1 + βGm hfe RE RE
1+
RE + hie

43
Figure 1.1.58: Equivalent closed-loop amplier block diagram of the circuit given in Figure 1.1.55.

From the closed-loop amplier diagram above, we can also nd the overall closed-loop transcon-
ductance gain GMsf , as

io Rif Rof
GMsf = = Gmf
vs Rs + Rif Rof + RL

Thus, overall closed-loop voltage gain AVsf will be given by

vo io RL
AVsf = = = GMsf RL
vs vs

Example 1.6: Determine the feedback type and derive the open-loop and closed-loop amplier
parameters (i.e., input resistance, output resistance and gain) for the multistage BJT circuit
below.

Figure 1.1.59: A multistage BJT circuit (a current-shunt feedback example).

Solution: Output and input networks have two common elements R0 and RE which provide
feedback in this circuit. It is connected in parallel (i.e., shunt connection) to the input circuitry.
0
The feedback signal if is the voltage through resistor R . Output signal sampled is output
current io . So, this circuit has current-shunt feedback.
44
 Feedback network's input connection is between the base terminal of Q1 and the ground. Sim-
ilarly, feedback network's output connection is between the emitter terminal of Q2 and the
ground. In order to obtain the open-loop input circuitry, we disconnect the output connection
terminals of the feedback network. Then, to obtain the open-loop output circuitry we short
circuit the input connection terminals of the feedback network. Then, as shown in Figure 1.1.44
e put the open-loop input and output circuitries together and we obtain the initial open-loop
circuit (i.e., circuit without feedback) below. Note that, have to indicate the feedback signal if
at the output circuitry of the open-loop circuit with the correct direction.

Figure 1.1.60: Initial open-loop circuit of the closed-loop circuit given in Figure 1.1.59.

Figure 1.1.61: Small-signal open-loop circuit of the closed-loop circuit given in Figure 1.1.59.

if RE
Now, the feedback gain β is given by β= = 0 .
io R + RE

45
Note that, as output current ows through and output voltage is across RC2 , RC2 is the eective
load, i.e., RL ≡ RC2 .

From the gure above let us calculate the open-loop amplier parameters Ri , Ro and Ai . Note
that, for simplicity we take hoe1 = hoe2 = 0.
vi vo
Ri = = (R0 + RE )||hie1 Ro = =∞
ii RL =0 io RL =vo ,is =0

Before calculating the total gain Ai , let us rst calculate no-load gain of the second stage Ai2
and loaded gain of the rst stage AI1 as follows

io io
Ai2 = = = −hfe2
ii2 RL =0 ib2

Note that io1 = ii2 = ib2 .

i o1 ib RE + R0 RC1
AI1 = = 2 =− 0
hfe1
ii ii RE + R + hie1 RC1 + Ri2

where Ri2 is the input resistance of the second stage and given by

Ri2 = hie2 + (hfe2 +1 ) (R0 ||RE )

Thus, open-loop no-load current gain Ai is given by

io RE + R0 hfe1 hfe2 RC1

Ai = = AI1 · Ai2 =
ii RL =0 RE + R0 + hie1 RC1 + Ri2

Now, let us calculate the closed-loop amplier parameters Rif , Rof and Aif using the current-
series feedback formulas derived before.

Ri (R0 + RE )||hie1
Rif = =
1 + βAI RE hfe1 hfe2 RC1
1+ 0
RE + R + hie1 RC1 + Ri2

 
Rs RE
Rof = (1 + βAis ) Ro = 1 + Ai ∞ = ∞
Rs + Ri R0 + RE

RE + R0 hfe1 hfe2 RC1

Ai RE + R0 + hie1 RC1 + Ri2 R0
Aif = = ≈1+
1 + βAi RE hfe1 hfe2 RC1 RE
1+ 0
RE + R + hie1 RC1 + Ri2

46
Figure 1.1.62: Equivalent closed-loop amplier block diagram of the circuit given in Figure 1.1.59.

From the closed-loop amplier diagram above, we can also nd the overall closed-loop current
gain AIsf , as

io Rs Rof
AIsf = = Aif
is Rs + Rif Rof + RC2
vs
where is =
Rs
Thus, overall closed-loop voltage gain AVsf will be given by

vo io RC2 RC2
AVsf = = = AIsf
vs is Rs Rs

47
1.2 Dierential Ampliers
Dierential amplier circuits have 2 inputs and 2 outputs, as shown by the model below.

Figure 1.2.1: Dierential amplier model

Dierential ampliers are used to amplify the dierence between the two inputs. Thus, dierential
ampliers are high gain and low noise ampliers.
Dierential amplier can be realized by using two BJTs by connecting their emitter terminals
together, where inputs are given from the base terminals and outputs are taken from the collectors of
the two transistors, as shown below.

Figure 1.2.2: Dierential amplier with a common emitter resistance

It can be operated with a dual power supply: VCC to −VEE ; or with a single supply: VCC to
GN D.

1.2.0.1 Three Modes of Operation

There are three modes of operation for dierential ampliers:

1. Single-ended mode
48
 - an input signal is applied to one of the inputs and the other input is grounded.

2. Common-mode
- the same input signal is applied to both inputs.
3. Dierential-mode
- two opposite polarity input signals are applied to its inputs.

1.2.1 DC Biasing
Both inputs are grounded (no AC input) and we assume that both transistors are well matched
(Q1 ≡ Q2 ).

Figure 1.2.3: Dierential amplier DC biasing

VEQ = 0 − VBE(ON ) = −VBE(ON ) . . . (as VBE1 (ON ) = VBE2 (ON ) ) (1.2.1)

VEQ − (−VEE ) VEE − VBE(ON )

IEQ = = (1.2.2)
RE RE
IEQ
ICQ = ICQ1 = ICQ2 = . . . (as IBQ1 = IBQ2 and β1 = β2  1) (1.2.3)
2

We can now calculate the DC voltages around the circuit as follows

VCQ = VCC − ICQ RC . . . VCQ1 = VCQ2 = VCQ (1.2.4)

VCEQ = VCC + VEE − ICQ (RC + 2RE ) . . . VCEQ1 = VCEQ2 = VCEQ (1.2.5)

49
 Note that as IBQ1 = IBQ2 and β1 = β2 (i.e., hfe1 = hfe2 ),

hie1 = hie2 = hie . (1.2.6)

1.2.2 Small-Signal Analysis

Figure 1.2.4: Dierential amplier small-signal analysis circuit.

Let us express the outputs in terms of the base currents assuming hoe1 = hoe2 = 0,

vo1 = −hfe ib1 RC (1.2.7)

vo2 = −hfe ib2 RC . (1.2.8)

Let us express the inputs in terms of the base currents where ve = [(hfe + 1)ib1 + (hfe + 1)ib2 ]RE ,

vi1 = vbe1 + ve = hie ib1 + [(hfe + 1)ib1 + (hfe + 1)ib2 ] RE

= [hie + (hfe + 1)RE ] ib1 + (hfe + 1)RE ib2 (1.2.9)

vi2 = vbe2 + ve = hie ib2 + [(hfe + 1)ib1 + (hfe + 1)ib2 ] RE

= (hfe + 1)RE ib1 + [hie + (hfe + 1)RE ] ib2 (1.2.10)

In order to obtain ib1 and ib2 in terms of let us rst express (1.2.9) and (1.2.10) using matrices and
take the inverse of the equation matrix (you can also obtain base currents using the classical variable
elimination method)
    
vi1 hie + (hfe + 1)RE (hfe + 1)RE ib1
= (1.2.11)
vi2 (hfe + 1)RE hie + (hfe + 1)RE ib2
Thus, base currents ib1 and ib2 are given by
    
ib1 1 hie + (hfe + 1)RE −(hfe + 1)RE vi1
= . (1.2.12)
ib2 hie [hie + 2(hfe + 1)RE ] −(hfe + 1)RE hie + (hfe + 1)RE vi2

50
Hence,

[hie + (hfe + 1)RE ] vi1 − (hfe + 1)RE vi2

ib1 = (1.2.13)
hie [hie + 2(hfe + 1)RE ]
[hie + (hfe + 1)RE ] vi2 − (hfe + 1)RE vi1
ib2 = . (1.2.14)
hie [hie + 2(hfe + 1)RE ]
Finally, the output voltages are expressed in terms of the input voltages as follows,

[hie + (hfe + 1)RE ] vi1 − (hfe + 1)RE vi2

vo1 = −hfe RC (1.2.15)
hie [hie + 2(hfe + 1)RE ]
[hie + (hfe + 1)RE ] vi2 − (hfe + 1)RE vi1
vo2 = −hfe RC . (1.2.16)
hie [hie + 2(hfe + 1)RE ]

1.2.3 Single-Ended Mode Operation

In this mode a signal is connected to one input and the other is grounded, i.e., vi2 = 0.

Figure 1.2.5: Single-ended dierential amplier.

By setting vi2 = 0 in (1.2.15), we obtain

vo1 −hfe RC [hie + (hfe + 1)RE ] ∼ −hfe RC

Av = = = (1.2.17)
vi1 [hie + 2(hfe + 1)RE ] hie 2hie

Note that if take the output from the opposite collector (see (1.2.16)), the gain becomes positive,

vo2 hfe RC [(hfe + 1)RE ] ∼ hfe RC

= = = −Av . (1.2.18)
vi1 [hie + 2(hfe + 1)RE ] hie 2hie

51
 • Input resistance of the single-ended mode is given as

vi1
Ris = (1.2.19)
ib1
[hie + 2(hfe + 1)RE ] hie
= . . . from (1.2.13) (1.2.20)
hie + (hfe + 1)RE
∼
= 2hie .

Consequently, input resistance of the single-ended mode is given by

Ris ∼
= 2hie . (1.2.21)
• Let us show the input and the two out-of-phase outputs in the gure below

Figure 1.2.6: Two out-of-phase outputs of the single-ended dierential amplier.

• Now, let us show the input and the dierential output in the gure below

Figure 1.2.7: Dierential output of the single-ended dierential amplier.

1.2.4 Common-Mode Operation

In this mode, the same signal is applied to both inputs, i.e., vi1 = vi2 = vi . As the dierential amplier
amplies the dierence between the inputs, common-mode gain should be quite small.

52
 Figure 1.2.8: Common-mode dierential amplier.

By setting vi1 = vi2 = vi in (1.2.15) and (1.2.16), we obtain

vo1 vo −hfe RC
Ac = = 2 = (1.2.22)
vi vi hie + 2(hfe + 1)RE

vi
• We see that input resistance of the common-mode, R ic = ib1 +ib2
, is

hie
Ric = + (hfe + 1)RE ≈ (hfe + 1)RE (1.2.23)
2

• As we dene the dierential output as

vo = vo1 − vo2 ,

if the dierential amplier is balanced, i.e.,

RC1 = RC2 = RC ,

then the dierential output common-mode gain is zero,

vo vo − vo2 −hfe (RC1 − RC2 ) −hfe (RC − RC )
= 1 = = = 0. (1.2.24)
vi vi hie + 2(hfe + 1)RE hie + 2(hfe + 1)RE

1.2.5 Dierential-Mode Operation

vd
In this mode, two opposite polarity signals vi1 = −vi2 = 2
are applied to the inputs

53
 Figure 1.2.9: Dierential-mode dierential amplier.
vd
By setting vi1 = 2
and vi2 = − v2d in (1.2.15), we obtain

vo1 −hfe RC
Ad = = (1.2.25)
vd 2hie
Here, vd is called the dierential input, i.e.,
vd = vi1 − vi2 .

• Note that if take the output from the opposite collector (see (1.2.16)), the gain becomes positive,

vo2 vo hfe RC
=− 1 = . (1.2.26)
vd vd 2hie
vd
• We see that, input resistance of the dierential-mode, Rid = i b1
, is

Rid = 2hie (1.2.27)

• As we dene the dierential output as

vo = vo1 − vo2 ,
if the dierential amplier is balanced, i.e.,

RC1 = RC2 = RC ,
then the dierential output dierential-mode gain is doubled,
vo vo − vo2 −hfe (RC1 + RC2 ) −hfe (2RC )
= 1 = = = 2Ad . (1.2.28)
vd vd 2hie 2hie

54
1.2.6 Linear Operation
vi1 + vi2
• Let us represent the two input signals vi1 and v i2 in terms of their average vavg = and
2
dierence vd = vi1 − vi2 ,

vd
vi1 = vavg + (1.2.29)
2
vd
vi2 = vavg − (1.2.30)
2
• If the system is linear then we can write the two outputs vo1 and vo2 as follows

vo1 = Ac vavg + Ad vd (1.2.31)

vo2 = Ac vavg − Ad vd (1.2.32)

• Similarly, the dierential output vo of a balanced dierential amplier becomes

vo = vo1 − vo2 = 2Ad vd (1.2.33)

NOTE: Dierential amplier with a common emitter resistance (see Figure 1.2.2) can always be
considered to be linear.

1.2.7 Common-Mode Rejection (Noise Rejection)

In common-mode, the signal common to both inputs will have a low gain (Ac ).

In dierential-mode (single-ended or double-ended), any signal that is common to both inputs

will have a low gain. In dierential-mode, any signal that is common to both inputs is noise.

The ability of the amplier to have a low common-mode gain, i.e., not amplify signals that are
common to both inputs, is called Common-Mode Rejection.
• Then, the Common-Mode Rejection Ratio (CMRR) is given by

Ad
CMRR = (1.2.34)
Ac
hie + 2(hfe + 1)RE
= (1.2.35)
2hie
• CMRR can be also represented in dBs, i.e.,

Ad
CMRR = 20 log10 (1.2.36)
Ac
• To improve common-mode rejection:

◦ Ad must increase

◦ Ac must decrease, i.e., RE must increase.

• One method is to increase the value of RE by replacing it with a constant-current source

circuit.

55
1.2.8 Dierential Amplier with a Constant-Current Source

Figure 1.2.10: Dierential amplier with a constant-current source.

This increases the AC impedance for RE .

Constant-current sources can be built using FETs, BJTs and a combination of these devices.

1.2.8.1 Constant-Current Source Circuits

Figure 1.2.11: A BJT constant-current source with resistors.

56
Collector current IC is independent of the load circuit connected to the collector and given by

IC ∼
= IE (1.2.37)

VB − VBE(ON ) − (−VEE )
= (1.2.38)
RE
R2
VEE − VBE(ON )
R + R2
≈ 1 . . . where (IR1 ∼
= IR2 )  IB . (1.2.39)
RE

Current source with a Zener diode

Figure 1.2.12: A BJT constant-current source with a Zener diode.

Collector current IC is independent of the load circuit connected to the collector and given by

IC ∼
= IE (1.2.40)

VZ − VBE(ON )
= . (1.2.41)
RE

Current Mirror

Figure 1.2.13: A current-mirror constant-current source.

57
Current-source current I is given by

I = IC2 (1.2.42)

= IC1 . . . as Q1 ≡ Q2 , i.e., VBE1 (ON ) = VBE2 (ON ) and β1 = β2 , (1.2.43)

∼
= IX . . . as IC1  2IB where IX = IC1 + 2IB , (1.2.44)

VCC − VBE(ON )
= . (1.2.45)
RX
Current-mirror circuits are used to provide constant current in integrated circuits.

Figure 1.2.14: Identical current-mirror constant-current sources (I1 = I2 = · · · = IN ).

Identical current-mirror constant-current sources (I1 = I2 = · · · = IN ) can be made as shown in

Figure 1.2.14.

Figure 1.2.15: An improved current-mirror constant-current source.

Homework 1.1: Consider Figure 1.2.15 above and nd I.

58
1.2.8.2 Analysis of Dierential Amplier with a Constant-Current Source

Figure 1.2.16: Dierential amplier with a constant-current source.

Let us analyse the dierential amplier with a constant-current source shown in Figure 1.2.16.
Note that sum of the emitter currents is constant due to the constant-current source, i.e.,

iE1 + iE2 = I0 (1.2.46)

Figure 1.2.17: Diode IV characteristics.

Before continuing any further, let us remember the pn-junction diode characteristic equation,

ID = IS eVD /γ


−1 , (1.2.47)

59
 kT
where IS is the saturation current and γ is the thermo-equivalent potential given by
q
γ=
, where k
is the Boltzman constant, T is the temperature in Kelvins and q is the Coulomb charge. At the room
◦
temperature, T = 300K (i.e., T = 27 C ), thermo-equivalent potential γ is given by

γ = 26 mV. (1.2.48)

Under forward bias, the diode current ID simplies to

ID ∼
= IS eVD /γ (1.2.49)

In a BJT, as BE -junction is as pn-junction, under forward bias we can write down the emitter currents
of a dierential amplier as follows

iE1 = IES evBE1 /γ (1.2.50)

vBE2 /γ
iE2 = IES e . . . Note that Q1 ≡ Q2 . (1.2.51)

Let us express the ratio of constant-current source current I0 to the emitter current IE1 using
(1.2.46) as follows

I0 iE
=1+ 2 (1.2.52)
iE1 iE1
IES evBE2 /γ
=1+ (1.2.53)
IES evBE1 /γ
= 1 + e(vBE2 −vBE1 )/γ (1.2.54)

= 1 + e(vi2 −vi1 )/γ (1.2.55)

where vBE1 = VBE(ON ) + vi1 and vBE2 = VBE(ON ) + vi2 .

iE1 iE2
We can now express the inverse ratios and as
I0 I0

iE1 1
= (1.2.56)
I0 1 + e(vi2 −vi1 )/γ

and
iE2 1
= (1.2.57)
I0 1 + e( i1 −vi2 )/γ
v

respectively. Note that

iE1 iE2
+ =1. (1.2.58)
I0 I0
As the collector currents are (almost) equal to the emitter currents, we can plot these ratios as
follows

60
 Figure 1.2.18: Ratio of the collector currents to the constant-current source.

From the gure Figure 1.2.18, we see that the linear region resides in between ±(1.15 γ).
Thus, if

|vi1 − vi2 | = |vd | ≤ 30 mV (1.2.59)

then, dierential amplier with constant-current source is in the linear region and the following linear
operations will hold,

vo1 = Ac vavg + Ad vd
vo2 = Ac vavg − Ad vd .

Example 1.7: For the circuit in Figure 1.2.19 below nd vo = vo1 − vo2 for

vi1 = 0 V and vi2 = 58.5 mV

61
Figure 1.2.19: A dierential amplier with constant-current source (a dierential amplier example)

Solution: Let us rst calculate the

iC1
I0
ratio

iC1 1
=
I0 1 + e(vi2 −vi1 )/γ
1
= (58.5m−0)/26m
1+e
1
=
1 + e2.25
∼
= 0.095.

Thus, iC1 and iC2 are given by

iC1
iC1 = I0 = (0.095)(10m) = 0.95 mA,
I0
iC2 = I0 − IC1 = 10m − 0.95m = 9.05 mA.

Consequently, vo is given by

vo = (VCC − iC1 RC ) − (VCC − iC2 RC )

= (iC2 − iC1 ) RC
= (9.05m − 0.95m) 1k
= 8.1 V.

1.2.9 Dierential Amplier Parameters

• Input oset voltage : VIO

62
 ◦ Input voltage dierence (VB1 − VB2 ) which makes vo = 0 V.
− Due to the VBE(ON ) dierence of the two BJTs, i.e., when VBE1 (ON ) 6= VBE2 (ON ) .
• Input oset current : IIO
◦ Input current dierence (IB1 − IB2 ) which makes vo = 0 V.
− Due to the hfe dierence of the two BJTs, i.e., when hfe1 6= hfe2 .

1.2.10 Improvements

Figure 1.2.20: Dierential amplier with a transistor at the collector.

The dierential amplier in Figure 1.2.14 has an improved output voltage swing.

Figure 1.2.21: Dierential amplier with a current mirror at the collector.

63
 Homework 1.2: Considering the circuit in Figure 1.2.21 above, nd the common-mode gain Ac
and dierential mode gain Ad during linear operation.
HINT: While performing small-signal analysis, consider RE = ∞ and employ current-mirroring.
You may start from DC analysis to understand the eect of the current mirror.

1.2.11 FET Dierential Amplier

Dierential amplier can also be realized by using two FETs by connecting their source terminals
together, where inputs are given from the gate terminals and outputs are taken from the drains of the
two transistors, as shown below.

Figure 1.2.22: FET dierential amplier with a common source resistance.

1.2.11.1 Small-Signal Analysis

Figure 1.2.23: FET dierential amplier small-signal analysis circuit.

Let us express the outputs in terms of the base currents assuming rds1 = rds2 = ∞,
vo1 = −gm vgs1 RD (1.2.60)

vo2 = −gm vgs2 RD . . . . As Q1 ≡ Q2 and IDQ1 = IDQ2 , gm = gm1 = gm2 . (1.2.61)

64
Let us express the inputs in terms of the gate-to-source voltages using matrices, where vs = [gm vgs1 + gm vgs2 ]RS
    
vi1 1 + gm RS gm RS vgs1
= (1.2.62)
vi2 gm R S 1 + gm RS vgs2

Thus, employing the linear algebra principles voltages we obtain vgs1 and vgs2 as the following
    
vgs1 1 1 + gm RS −gm RS vi1
= . (1.2.63)
vgs2 1 + 2gm RS −g R
m S 1 + g R
m S vi2
• Hence, by setting vi1 = vi2 = vi in (1.2.63) and employing (1.2.60) and (1.2.61), we obtain the
common-mode gain as
vo1 vo −gm RD
Ac = = 2 = . (1.2.64)
vi vi 1 + 2gm RS
vd
• Similarly, by setting vi1 = 2
and vi2 = − v2d in (1.2.63) and employing (1.2.60) and (1.2.61), we
obtain the dierential-mode gain as
vo1 −gm RD
Ad = = (1.2.65)
vd 2

• NOTE: FET dierential amplier with a common source resistance (see Figure 1.2.22) can be
always considered to be linear. Thus, the linear operation holds:

vo1 = Ac vavg + Ad vd
vo2 = Ac vavg − Ad vd .

1.2.12 Uses of Dierential Ampliers

1. Gain ampliers in operational ampliers

− Due to high voltage gain

2. Comparators

− Due to high sensitivity to the dierential input, e.g., measurement circuit below

Figure 1.2.24: A dierential amplier measurement circuit

65
 Here, RT h signies a thermistor whose resistance varies with temperature. Note that, the
output is zero, i.e., vo = 0 V, only when V1 = V2 .

1.2.13 Examples
Example 1.8: For the circuit below,

i. Calculate the value of RC in order to make vo = 0 V when vi = 0 V.

ii. Find vo when vi = 1 mV sin(ωt).
hfe = hF E = 100, α = 1, VBE(ON ) = 0.6 V

Figure 1.2.25: Dierential amplier circuit for Example 1.8.

Solution: i. Let us rst calculate the value of the constant-current source I0

VCC − VBE(ON ) − (−VEE )
I0 ∼
= . . . ignoring IB5 , IB4 and IB3
R4 + R5
20 − 0.6 − (−20)
=
2M + 1.94M
= 10 µA.

I0 10µ
Thus, ICQ1 = ICQ2 = 2
= 2
= 5 µA.

In order to nd IR6 , we need to write a KVL equation for the (R6 , R1 , R4 )-loop

VCC − R6 IR6 − VBE6 (ON ) + R1 IR1 + VBE3 (ON ) + R4 IR4 = VCC

66
Thus IR6 is given by

R1 IR1 + R4 IR4
IR6 =
R6
(0.1M )(5µ) + (2M )(10µ)
= . . . IR4 ∼
= I0 = 10 µA
1.25M
= 16.4 µA.
IR6 16.4µ
Thus, ICQ6 = ICQ7 = 2
= 2
= 8.2 µA.
Hence, IBQ8 = ICQ7 = 8.2 µA.
ICQ8 = hF E IBQ8 = (100)(8.2µ) = 0.82 mA.
Consequently, RC is given by

VCC − vo
RC =
ICQ8
20 − 0
=
0.82m
= 24.39 kΩ.

ii. First stage dierential amplier (with a constant-current source) is in the linear mode (as
vd = 1 mV < 30 mV), so let us calculate the hie values for the relevant transistors and the input
resistance Ri8 of the last stage as RC7 = Ri8

γ 25m
hie1 = hie2 = hfe = 500 kΩ,
= 100
ICQ1 5µ
γ 25m
hie6 = hie7 = hfe = 100 = 305 kΩ,
ICQ7 8.2µ
γ 25m
hie8 = hfe = 100 = 3.05 kΩ
ICQ8 0.82m
RC7 = Ri8 = hie8 + (hfe + 1)R7 = 3.05k + (101)(5k) = 508.05 kΩ.

Linear-mode dierential output of the rst stage, (vC2 − vC1 ), is given by

hfe 2RC ||2hie6 hfe RC ||hie6

vC2 − vC1 = vi = vi
2hie1 hie1
(100)(100k||305k)
= (1m)
500k
= 0.015 V.

Output of the second stage, vC7 , is given by

−hfe RC7
vC7 = (vB7 − vB6 )
2hie7
−(100)(508.05k)
= (0.015)
(2)(305k)
= −1.25 V.

67
Finally output vo is given by,

−hfe RC RC
vo = vC . . . vo ∼
=− vC
hie8 + (hfe + 1)R7 7 R7 7
−(100)(24.39k)
= (−1.67)
508.05k
= 6 V sin(ωt).

Example 1.9: For the circuit below, (HINT: Use forward bias diode equation for diodes)

i. Calculate the value of R in order to make vo = 0 V when vi = 0 V.

ii. Find vo when vi = 20 mV sin(ωt).
hfe = hF E = 20, α = 1, VBE(ON ) = 0.6 V, γ = 25 mV

Figure 1.2.26: Dierential amplier circuit for Example 1.9.

Example 1.10: For the circuit below, calculate the value of R2 /R1 in order to make vo = 0 V
when vi = 0 V.

hfe = hF E = 100, α = 1, VBE(ON ) = 0.6 V

68
Figure 1.2.27: Dierential amplier circuit for Example 1.10.

69
1.3 Operational Ampliers
Operational amplier or op-amp, is avery high gain dierential amplier with a high input
impedance (typically a few mega ohms) and low output impedance (less than 100 ohms).

Figure 1.3.1: Operational amplier block diagram

Note the op-amp has two inputs and one output, and op-amp amplier model is shownin Fig-
ure 1.3.2 below.

Vd = V+ − V− = Vi2 − Vi1

Figure 1.3.2: Operational amplier model

1.3.1 Ideal Op-Amp Properties

1. Innite Input Resistance: Ri = ∞

2. Zero Output Resistance: Ro = 0

3. Innite Voltage Gain: Ad = ∞

4. Innite Bandwidth: BW = ∞

5. Innite output current

6. Perfect Balance, i.e., vo = 0 when vi2 = vi1

7. Above characteristics do not drift with temperature

1.3.2 MC1530 Operational Amplier

Let us perform DC and AC analysis on the electronic circuit of the MC1530 op-amp shown below.

70
 Figure 1.3.3: Electronic circuit of the MC1530 op-amp

Amplier stages in Figure 1.3.3 can be identied as shown in Figure 1.3.4 below.

Figure 1.3.4: Block diagram of the MC1530 electronic circuit in Figure 1.3.3

1.3.2.1 DC Analysis
Let us perform DC analysis calculations on the MC1530 opamp internal circuitry.

71
 hfe = hFE = 100, α = 1, VBE(ON ) = VD(ON ) = 0.7 V

R5
VB1 ∼


= −VEE + 2VD(ON ) = −3.14 V
R4 + R5
VEE + VB1 − VBE(ON )
I0 ∼
= I1 = = 0.99 mA
R1
I0
IC2 = IC3 ∼
= = 0.495 mA
2
VB4 ∼
= VCC − IC2 R2 = 2.18 V
VE VB − VBE(ON )
I6 = 4 = 4 = 0.986 mA
R6 R6
I6
IC5 ∼
= = 0.493 mA
2
V3 ∼
= VCC − IC5 R7 = 4.52 V
V4 = V3 − VBE(ON ) = 3.82 V
VEE − VD3 (ON )
I8 ∼
= IC7 = = 1.56 mA
R8

Figure 1.3.5: MC1530 DC analysis calculations - 1

Let us continue with the DC calculations on the output stage consisting of Q8 , Q9 and Q10
transistors

VB8 = −VEE + 2VBE(ON ) = −4.6 V

V4 − VB8
I9 = = 1.4 mA
R9
I10 = IC7 + IB8 − I9 ∼
= IC7 − I9 = 0.16 mA
Vo = VB + I10 R10 = 200 mV ∼
8 = 0 V.

Figure 1.3.6: MC1530 DC analysis calculations - 2: Output stage

72
1.3.2.2 Small-signal Analysis
Let us perform small-signal analysis calculations on the MC1530 opamp internal circuitry.

hfe γ
hie2 = hie3 ∼
= hie4 = hie5 = = 5.2 kΩ
IC2
2R20 = 2R2 ||2hie4 = 6.22 kΩ
R70 = R7 ||Ri6 ∼
= R7 = 3 kΩ

v2 hfe 2R20
A∗v1 = = = 59.81
v1 2hie2
v3 −hfe R70
A∗v2 = = = −28.85
v2 2hie5
v4 ∼
A∗v3 = =1
v3
vo ∼ −R10
Av4 = = = −5
v4 R9
Av = A∗v1 A∗v2 A∗v3 Av4 = 8628

Figure 1.3.7: MC1530 small-signal analysis calculations

1.3.3 Op-Amp Gain

Op-Amps have a very high open-loop gain. They can be connected open- or closed loop.

Open-loop refers to a conguration where there is no feedback from output back to the input.
In the open-loop conguration the gain can exceed 10000.

Closed-loop conguration reduces the gain. In order to control the gain of an op-amp it must
have feedback. This feedback is a negative feedback. A negative feedback will reduce the gain
and improve many characteristics of the op-amp

73
1.3.4 Inverting Op-Amp Amplier

Figure 1.3.8: Inverting op-amp amplier.

The input is applied to the inverting (−)-input; the non-inverting (+)-input is grounded. The
resistor Rf is the feedback resistor; it is connected from the output to the negative (inverting)
input. This is negative feedback.
1.3.4.1 Virtual Ground
An understanding of the concept of virtual ground provides a better understanding of how an
ideal op-amp operates.

◦ The non-inverting input pin is at ground. The inverting input pin is also at 0V for an AC
signal. This is because ideal op-amp open-loop gain is innity. As A = ∞,
vo vo
v+ − v− = = = 0.
A ∞
Thus, v+ = v− .
◦ As the ideal op-amp input resistance is innity, i.e., Ri = ∞, no current goes through
the terminals of the op-amp, i.e.,

v+ − v−
i+ = −i− = = 0.
Ri
Thus, all of the current is through Rf .
Consequently, the inverting op-amp circuit simplies to the following circuit below

Figure 1.3.9: Simplied inverting amplier circuit for an ideal op-amp.

74
1.3.4.2 Gain
From the simplied inverting amplier circuit,shown in Figure 1.3.9, gain can be determined by
external resistors: Rf and R1 .
vo Rf
Av = =− (1.3.1)
vi R1
Thenegative sign denotes a 180◦ phase shift between input and output.
Homework 1.3: Derive the gain when A 6= ∞ using normal KVL and KCL equations and
observe that when A→∞ it gives the result above.

Homework 1.4: Derive the same gain using feedback analysis, i.e., determine the feedback
type, draw the open-loop circuit, nd the open-loop gain, obtain the closed-loop gain and then
obtain the voltage gain vo /vi . Observe that the result is exactly same as the one derived in
Homework 1 above.

Homework 1.5: Repeat Homework 1.3 and Homework 1.4 above for the noninverting
amplier conguration.

1.3.5 Practical Op-Amp Circuits

Most commonly used opamp circuits are given below:

1. Inverting Amplier

2. Non-inverting Amplier

3. Summing Amplier

4. Unity Follower

5. Integrator

6. Dierentiator

1.3.5.1 Inverting Amplier

Figure 1.3.10: Inverting amplier.

Rf
vo = − vi (1.3.2)
R1

75
1.3.5.2 Non-Inverting Amplier

Figure 1.3.11: Non-inverting amplier.

 
Rf
vo = 1+ vi (1.3.3)
R1

1.3.5.3 Summing Amplier

Figure 1.3.12: Summing Amplier.

 
Rf Rf Rf
vo = − v1 + v2 + v3 (1.3.4)
R1 R2 R3

76
1.3.5.4 Unity Follower

Figure 1.3.13: Unity Follower.

vo = vi (1.3.5)

Any amplier with no gain (or loss) is called a unity gain amplier or a voltage buer. Realistically
these circuits will be designed using resistors that are equal (R1 = Rf ) to void out problems with
oset voltages.
The advantages of using a unity gain amplier:

• very high input impedance

• very low output impedance

1.3.5.5 Integrator

Figure 1.3.14: Integrator.

The output is the integral of the input. Integration is the operation of summing the area under a
waveform or curve over a period of time. This circuit is useful in low-pass lter circuits and sensor
conditioning circuits. Z
1
vo = − v1 (t)dt (1.3.6)
RC

77
1.3.5.6 Dierentiator

Figure 1.3.15: Dierentiator.

The dierentiator takes the derivative of the input. This circuit is useful in high-pass lter circuits.

dv1 (t)
vo = −RC (1.3.7)
dt

1.3.5.7 Logarithmic Amplier

Figure 1.3.16: Integrator.

Homework 1.6: Derive Vo .

HINT: Use the diode characteristic equation under forward bias.

1.3.6 Op-Amp Specications - DC Bias and Oset Parameters

Even though the input voltage is zero, i.e., vi1 = vi2 = 0, there will be an output, i.e., vo 6= 0. This is
called oset. Some of the following can cause this oset.

1. Input Bias Current

2. Input Oset Current

78
 3. Input Oset Voltage

4. Input Oset Voltage and Current Drifts

5. Power Supply Rejection Ratio

6. Open-Loop Voltage Gain

7. Slew Rate

8. Common-Mode Rejection Ratio

9. Input Resistance

10. Output Resistance

11. Open-Loop Bandwidth

12. Power Consumption (no input, no load)

13. Power Dissipation (with input, with load)

1.3.6.1 Input Bias and Oset Currents

Figure 1.3.17: Input bias currents.

Even though the input voltage is zero, i.e., vi1 = vi2 = 0, sometimes the output is not zero, i.e., vo 6= 0.
Then, bias currents IB1 and IB2 are supplied to the opamp to make the output zero, i.e., vo = 0.

• Input Bias Current (IIB ) is dened as the average of the two bias currents:
IB1 + IB2
IIB = (1.3.8)
2

• Similarly, Input Oset Current (IIO ) is dened as the dierence of the two bias currents:
IIO = IB1 − IB2 (1.3.9)

79
1.3.6.2 Input Oset Voltage

Figure 1.3.18: Input oset voltage.

Even though the input voltage is zero, i.e., vi1 = vi2 = 0, sometimes the output is not zero, i.e., vo 6= 0.
Then, an oset voltage VIO is supplied to the opamp to make the output zero, i.e., vo = 0. This oset
voltage is called the Input Oset Voltage dened by
VIO = V1 − V2 (1.3.10)

1.3.6.3 Input Oset Voltage and Current Drifts

∆VIO ∆IIO
Input Oset Voltage Drift, , and Input Oset Current Drift, , where T denotes the tem-
∆T ∆T
perature, indicate the sensitivities of the input oset voltage and input oset currents to the change
in temperature.

1.3.6.4 Power Supply Rejection Ratio

∆VIO
S+ =
∆VS+ VS− =0

∆VIO
S− =
∆VS− VS+ =0

Figure 1.3.19: Power supply rejection ratio

1.3.6.5 Open-loop voltage gain

Open-loop voltage gain, Av , of an opamp is very high, e.g., for 741, Av ∼
= 2 × 105 .

1.3.6.6 Slew Rate

Slew rate is the time rate of change of the closed-loop amplier output voltage under large-signal
conditions, that is, the maximum rate at which an op-amp can change output without distortion.

∆Vo
SR =
∆t
80
 The SR rating is given in the specication sheets as V /µs rating.

Maximum Signal Frequency

The slew rate determines the highest frequency of the op-amp without distortion:

SR
f≤
2πVp
where Vp is the peak voltage.

1.3.6.7 Common-Mode Rejection Ratio

One rating worth mentioning that is unique to op-amps is CMRR or Common-Mode Rejection Ratio.
Because the op-amp has two inputs that are opposite in phase (inverting input and the non-
inverting input) any signal that is common to both inputs will be cancelled. A measure of the ability
to cancel out common signals is called CMRR and it is given by

Ad
CMRR (dB) = 20 log10 (1.3.11)
Ac

1.3.6.8 Open-Loop Bandwidth

Figure 1.3.20: Op-amp open-loop bandwidth.

The op-amp's high frequency response is limited by internal circuitry. The plot shown is for an
open loop gain (AOL or AVD ).

This means that the op-amp is operating at the highest possible gain with no feedback resistor.

In the open loop, the op-amp has a narrow bandwidth.

Gain-bandwidth product is constant. So, the bandwidth will widen in closed loop operation,
but then the gain will be lower.

81
1.3.6.9 Op-Amp Performance
The specication sheets will also include graphs that indicate the performance of the op-amp over a
wide range of conditions.

Figure 1.3.21: Some op-amp performance graphs.

The table in Figure 1.3.22 below shows some characteristics of a 741 opamp.

Figure 1.3.22: Some characteristics of a 741 opamp.

Note that, these ratings are for specic circuit conditions, and they often include minimum, max-
imum and typical values.

82
1.3.7 Eects of Oset Voltage and Bias Currents

Figure 1.3.23: Eects of oset voltages and bias currents.

Let us write down the two KVL equations (implicitly using KCL) available in Figure 1.3.23 above in
order to express output vo in terms of the input oset voltage, VIO , and input bias currents, IB1 and
IB2 when there is no input present, i.e., vi1 = vi2 = 0.

(IB1 − If )R1 − If Rf + vo = 0 (1.3.12)

(IB1 − If )R1 + VIO − IB2 R2 = 0 (1.3.13)

Thus, we obtain output vo by eliminating If in the KVL equations above as:

   
Rf Rf
vo = 1+ VIO + Rf IB1 − 1+ R2 IB2 . (1.3.14)
R1 R1

You can also obtain the result in Figure 1.3.14 above by applying the superposition theorem.
Note that, the value of R2 does not aect the gain equations. However, we can select a value of for
R2 in order to eliminate the eects of the oset voltage and bias currents. Hence, from the output
equation (1.3.14), the value of R2 which makes the output zero, i.e., vo = 0, is found to be:

VIO IB
R2 = + (Rf ||R1 ) 1 . (1.3.15)
IB2 IB2
Note that, as a rule of thumb we can always select R2 = Rf ||R1 . Then, the output equation
(1.3.14) reduces to
 
Rf
vo = 1+ VIO + Rf IIO . (1.3.16)
R1
So, the output will be zero if both the input oset voltage and current are zero, i.e., vo = 0 if VIO = 0
and IIO = 0.

Example 1.11: Change the circuit below, in order to eliminate the eect of input oset
voltage and current, i.e., make vo = 0, where VIO = 0 V and IB1 = IB2 = 100 nA.

83
 Figure 1.3.24: Opamp Oset Elimination Problem for Example 1.11.

Solution: Let us rst show that vo 6= 0 when there is no resistor the non-inverting terminal, i.e.,
when R2 = 0, as vo = Rf IB1 = (0.3M )(0.1µ) = 30 mV. Thus, the value of R2 which eliminates
the oset is R2 = R1 ||Rf = 100k||300k = 75 kΩ.

Figure 1.3.25: Opamp Oset Elimination Solution for Example 1.11.

Example 1.12: Change the circuit below, in order to eliminate the eect of input oset
voltage and current, i.e., make vo = 0, where VIO = 0 V, IB1 = 100 nA and IB2 = 80 nA.

Figure 1.3.26: Opamp Oset Elimination Problem for Example 1.12.

84
Solution: Let us rst show that vo 6= 0 R2 = 75 kΩ, as vo = Rf IIO = (0.3M )(0.02µ) =
when
I
6 mV. Thus, the value of R2 which eliminates the oset is R2 = (R1 ||Rf ) IBB1 = 75k(100n/80n) =
2
93.75 kΩ.

Figure 1.3.27: Opamp Oset Elimination Solution for Example 1.12.

Example 1.13: Change the circuit below, in order to eliminate the eect of input oset
voltage and current, i.e., make vo = 0, where VIO = 2 mV, IB1 = 100 nA and IB2 = 80 nA.

Figure 1.3.28: Opamp Oset Elimination Problem for Example 1.13.

 
Rf
Solution: Let us rst show that vo 6= 0 when R2 = 75 kΩ, as vo = 1 + VIO + Rf IIO =
R1
(1 + 0.3M/0.1M )(2m) + (0.3M )(0.02µ) = 14 mV. Thus, the value of R2 which eliminates the
V IB
oset is R2 = IO + (R1 ||Rf ) 1 = 25k + 93.75k = 118.75 kΩ.
IB 2
IB 2

85
 Figure 1.3.29: Opamp Oset Elimination Solution for Example 1.13.

Figure 1.3.30: Opamp amplier with R2 resistor: (a) inverting (b) noninverting.

Figure 1.3.30a and Figure 1.3.30b above show inverting and noninverting ampliers both with
an oset compensation R2 resistors, respectively.

As a rule of thumb, always use an R2 resistor in your opamp circuit, at least with a value of
R2 = R1 ||Rf .

1.3.8 Multistage Gains

Figure 1.3.31: Multistage opamp ampliers.

86
As a voltage-gain amplier, the input resistance of op-amp ampliers are high and the output resis-
tances are small. So, when cascaded we can ignore the loading eects and multiply the gains of each
stage in order to nd overall gain, i.e.,

vo
Av = = AV1 AV2 Av3 (1.3.17)
vi
  
Ri2 Ri3
= Av1 Av2 Av3 (1.3.18)
Ri2 + Ro1 Ri3 + Ro2
∼
= Av1 × Av2 × Av3 (1.3.19)
   
Rf Rf Rf
= 1+ − − (1.3.20)
R1 R2 R3

1.3.9 Active Filters

Adding capacitors to op-amp circuits provides an external control for the cuto frequencies. The
op-amp active lter provides controllable cuto frequencies and controllable gain

• Lowpass Filter

• Highpass Filter

• Bandpass Filter

1.3.9.1 Lowpass Filter

• First-order lowpass lter

Figure 1.3.32: First-order lowpass lter (a) Circuit (b) Bode magnitude plot

• The upper (or higher) cuto frequency fOH is

1
fOH = (1.3.21)
2πR1 C1

87
 • Low frequency gain Av is
RF
Av = 1 + (1.3.22)
RG

• Second-order lowpass lter

Figure 1.3.33: Second-order lowpass lter (a) Circuit (b) Bode magnitude plot

• By adding more RC networks the roll-o can be made steeper. Each RC network adds and
additional 20 dB/decade (or 6 dB/octave) slope.

1.3.9.2 Highpass Filter

• First-order highpass lter

Figure 1.3.34: First-order highpass lter (a) Circuit (b) Bode magnitude plot

• The lower cuto frequency fOL is

1
fOL = (1.3.23)
2πR1 C1

88
 • High frequency gain Av is
RF
Av = 1 + (1.3.24)
RG

1.3.9.3 Bandpass Filter

Figure 1.3.35: First-order bandpass lter (a) Circuit (b) Bode magnitude plot

• There are two cuto frequencies: upper and lower. They can be calculated using the same
low-pass cuto and high-pass cuto frequency formulas given in the previous sections.

89
1.4 Power Ampliers
So far we have dealt with only small-signal ampliers. In small-signal ampliers the main factors were

• amplication

• linearity

• gain

Large-signal or power ampliers function primarily to provide sucient power to drive the
output device. These amplier circuits will handle large voltage signals and high current levels. The
main factors are

• eciency

• maximum power capability

• impedance matching to the output device

1.4.1 Power Amplier Types

Main classes of power ampliers are given below

1. Class A

2. Class B

3. Class AB

4. Class C

5. Class D

1.4.1.1 Class A Operation

The output of a Class A amplier conducts for the full 360◦ of the cycle as shown below.

Figure 1.4.1: Class A amplier output (full-cycle operation)

90
 The Q-point (bias level) must be biased towards the middle of the load line so that the AC signal
can swing a full cycle. Remember that the DC load line indicates the maximum and minimum limits
set by the DC power supply.

The eciency is low, because the transistor is always on, even when there is no AC input.
1.4.1.2 Class B Operation
A Class B amplier output only conducts for 180◦ or half-cycle of the input signal as shown below.

Figure 1.4.2: A Class B amplier output (half-cycle operation)

The Q-point (bias level) is at cut-o (i.e., current is zero) on the load line, so that the AC signal
can only swing for one half of a cycle.

The eciency is high, because the transistor is o, when there is no AC input. However, we will
need two transistor in order to produce a full cycle-output.

1.4.1.3 Class AB Operation

A Class AB amplier output conducts between 180◦ and 360◦ of the AC input signal.

This amplier is in between the Class A and Class B. The Q-point (bias level) is above the Class
B but below the Class A.

1.4.1.4 Class C Operation

The output of the Class C conducts for less than 180◦ of the AC cycle and will operate only with a
tuned (resonant) circuit. The Q-point (bias level) is at cuto, the output signal is very small.

1.4.1.5 Class D Operation

The Class D output is more like pulse signals which are on for a short interval and o for a longer
interval. It does not resemble the AC sine wave input, however it is possible to obtain full sine wave
output using digital signal processing techniques.

91
1.4.1.6 Amplier Eciency
Eciency refers to the ratio of output to input power. The lower the amount of conduction of the
amplier the higher the eciency, so the eciency improves (gets higher) going from Class A to Class
D.

Figure 1.4.3: Comparison of amplier classes

Eciency η is dened as the ratio of the power output to the power input, i.e.,

PL
η% = × 100 (1.4.1)
PCC

where PL is the power output and PCC is the power input.

1.4.1.7 Power Input
The power into the amplier is from the DC supply. With no input signal, the DC current drawn is
the collector bias current, ICQ .
Thus, power input PCC is dened as the power drawn from the power supply

PCC = VCC ICQ (1.4.2)

1.4.1.8 Power Output

PL = vo(rms) io(rms) (1.4.3)

vo io
= peak peak
2
vo2peak
= (1.4.4)
2RL
vo2
= peak−peak
8RL

92
1.4.1.9 Transistor Power Dissipation
Power dissipated as heat across a transistor is given as

1
PQ = (PCC − PL ) (1.4.5)
NQ

where NQ is the number of transistors used in the power amplier conguration.

NOTE: The larger the output signal, the lower the heat dissipation.
1.4.1.10 Figure of Merit
Figure of Merit (FoM) is a quantity used to characterize the cost performance of the power amplier in
terms of the ratio of the maximum power dissipated by a transistor and the maximum power delivered
to the load, i.e.,
PQmax
FoM = (1.4.6)
PLmax
NOTE: The lower the FoM, the better the cost performance. Because the higher the maximum
power rating of a transistor, the higher the price.

1.4.2 Series-Fed Class A Amplier

This is similar to the small-signal amplier except that it will handle higher voltages. The Q-point
(bias level) is biased in the middle of the load line for maximum eciency.

Figure 1.4.4: Series-fed Class A large-signal amplier

The transistor used is a high power transistor. The current gain β of a power transistor is generally
less than 100. Power transistors are capable of handling large power or current while not providing
much voltage gain.

93
1.4.2.1 AC-DC Load Lines
As overall resistances of DC and AC output-loops are equal to each other, i.e., RDC = Rac = RC , AC
load line is equal to the DC load line (VCE = VCC − IC RC )as shown in Figure 1.4.5 below.

Figure 1.4.5: AC-DC load-line for the series-fed Class A amplier in Figure 1.4.4

For maximum undistorted output swing, we need to set the Q-point at the middle of the AC load
line, i.e.,
VCC
VCEQ =
2
and
VCC
ICQ = .
2RC
Thus, peak value of the maximum output voltage swing is given by

VCC
vo(max)peak = vce(max)peak = . (1.4.7)
2

Then, we can choose a value for RB in order to obtain the desired Q-point values, i.e.,

VCC − VBE(ON ) VCC − VBE(ON )

RB = = (1.4.8)
IBQ ICQ /β

NOTE: Once the value of RB is given, it means that the Q-point is already set. Then, we have to
make (or adjust) our calculations according to the given Q-point. For example, according to a given

94
Q-point maximum undistorted output voltage swing will be the minimum of VCEQ and VCC − VCEQ ,
i.e.,
vce(max)peak Q-point
= min (VCEQ , VCC − VCEQ ) (1.4.9)

1.4.2.2 Power Input

PCC = VCC ICQ

1.4.2.3 Power Output

vo2peak
PL = (1.4.10)
2RC
vo2peak−peak
=
8RC

1.4.2.4 Eciency
PL
η% = × 100
PCC
vo2peak /(2RC )
= × 100 (1.4.11)
VCC ICQ

1.4.2.5 Transistor Power Dissipation

Power dissipated as heat across a transistor is given as

PQ = PCC − PL
vo2peak
= VCC ICQ − (1.4.12)
2RC

1.4.2.6 Maximum Eciency

Maximum eciency ηmax is achieved at the maximum output power PL(max) , i.e., at the maximum
output swing vo(max)peak = VCC
2
. Thus,

2
vo(max) (VCC /2)2 V2
PL(max) = peak
= = CC (1.4.13)
2RC 2RC 8RC
Similarly, the input power at the maximum undistorted swing is given as

2
 
VCC VCC
PCC |PL(max) = VCC ICQ |vo(max) = VCC = (1.4.14)
2RC 2RC

95
Thus, maximum eciency ηmax is given as

PL(max)
ηmax % = × 100 (1.4.15)
PCC |PL(max)
2
VCC /(8RC )
= 2
× 100 (1.4.16)
VCC /(2RC )
1
= × 100 (1.4.17)
4
= 25%. (1.4.18)

1.4.2.7 Figure of Merit

As transistor power dissipation is given by (1.4.12), maximum transistor power is dissipated when
there is no AC input and output, i.e., PL = 0
2
VCC
PQ(max) = PCC |PL(max) − 0 = PCC |PL(max) = . (1.4.19)
2RC
Thus, gure of merit (FoM) is given as

PQ(max)
FoM = (1.4.20)
PL(max)
2
VCC /(2RC )
= 2 (1.4.21)
VCC /(8RC )
= 4. (1.4.22)

This FoM value shows that a series-fed Class A amplier is not a good choice as a power amplier.
Because, if we want to deliver 10 W to the load, we need to select a 40 W-transistor.

96
1.4.3 Transformer-Coupled Class A Amplier

Figure 1.4.6: Transformer-coupled Class A power amplier

This circuit uses a transformer to couple to the load. This improves the eciency of the Class A to
50%.

1.4.3.1 AC-DC Load Lines

DC Load-Line
In DC operation, transformer action is not present we only have the DC resistance of the primary
winding which is taken as zero. So, the overall DC resistance of the output-loop, RDC is also zero,
i.e.,
RDC = 0. (1.4.23)

Thus, the DC load-line equation is given by

VCE = VCC . (1.4.24)

AC Load-Line
In AC operation, transformer action is present as shown in Figure 1.4.7 below. Transformers
transform voltage, current and impedance.

97
 N1
a= N2
, V1 = aV2 , I2 = aI1 and

RL0 = a2 RL

Figure 1.4.7: Transformer operation

So, overall AC resistance of the output-loop, Rac is equal to the equivalent primary-side load RL0 ,
i.e.,
Rac = RL0 (1.4.25)

where
RL0 = a2 RL , (1.4.26)

and a is the turns ratio of the transformer, i.e., a = N1

N2
. Thus, AC load-line equation is then given
by
−1 VCEQ
iC = v + ICQ +
0 CE
. (1.4.27)
RL RL0
Finally, we can plot the AC-DC load-lines together as shown in below.

Figure 1.4.8: AC-DC load-line of the transformer-coupled Class A amplier in Figure 1.4.6

98
 For maximum undistorted output swing, we need to set the Q-point at the middle of the AC load
line, to satisfy
vo(max)peak = vce(max)peak = VCEQ = VCC (1.4.28)

with
VCEQ VCC
ICQ = 0
= 0
RL RL
.
Then, we can choose a value for RB in order to obtain the desired Q-point values, i.e.,

VCC − VBE(ON ) VCC − VBE(ON )

RB = = (1.4.29)
IBQ ICQ /β

NOTE: Once the value of RB is given, it means that the Q-point is already set. Then, we have to
make (or adjust) our calculations according to the given Q-point. For example, according to a given
Q-point maximum undistorted output voltage swing will be the minimum of VCEQ and ICQ RL0 , i.e.,

vce(max)peak Q-point
= min (VCC , ICQ RL0 ) (1.4.30)

1.4.3.2 Power Input

PCC = VCC ICQ

1.4.3.3 Power Output

vo2peak
PL = (1.4.31)
2RL0

1.4.3.4 Eciency
PL
η% = × 100
PCC
vo2peak /(2RL0 )
= × 100 (1.4.32)
VCC ICQ

1.4.3.5 Transistor Power Dissipation

Power dissipated as heat across a transistor is given as

PQ = PCC − PL
vo2peak
= VCC ICQ − (1.4.33)
2RL0

99
1.4.3.6 Maximum Eciency
Maximum eciency ηmax is achieved at the maximum output power PL(max) , i.e., at the maximum
output swing vo(max)peak = VCC . Thus,
2
vo(max) peak
2
VCC
PL(max) = = (1.4.34)
2RL0 2RL0
Similarly, the input power at the maximum undistorted swing is given as

2
 
VCC VCC
PCC |PL(max) = VCC ICQ |vo(max) = VCC = (1.4.35)
RL0 RL0
Thus, maximum eciency ηmax is given as

PL(max)
ηmax % = × 100
PCC |PL(max)
2
VCC /(2RL0 )
= × 100 (1.4.36)
2
VCC /RL0
1
= × 100 (1.4.37)
2
= 50%. (1.4.38)

1.4.3.7 Figure of Merit

As transistor power dissipation is given by (1.4.33), maximum transistor power is dissipated when
there is no AC input and output, i.e., PL = 0
2
VCC
PQ(max) = PCC |PL(max) − 0 = PCC |PL(max) = . (1.4.39)
RL0
Thus, gure of merit (FoM) is given as

PQ(max)
FoM = (1.4.40)
PL(max)
V 2 /R0
= 2 CC L0 (1.4.41)
VCC /(2RL )
= 2. (1.4.42)

This FoM value is not also very good. Because, if we want to deliver 10 W to the load, we need to
select a 20 W-transistor.

1.4.4 Class B Ampliers

In Class B the DC bias leaves the transistor biased just o (i.e., at cut-o ). The AC signal turns the
transistor on. This is essentially no bias. The transistor only conducts when it is turned on by half
of the AC cycle.

100
 In order to get a full AC cycle out of a Class B amplier, you need two transistors.
In a transformer-coupled push-pull arrangement, two npn-transistors are one works on the positive
half of the input signal and the other works on the inverted negative half of the input signal. In a
complementary-symmetry push-pull arrangement, one is an npn-transistor that provides the positive
half of the AC cycle and the other is a pnp transistor that provides the negative half.

Figure 1.4.9: Class B amplier push-pull operation block diagram

1.4.4.1 Phase Splitter Circuits

If the input is in the form of two opposite polarity signals, two similar stages could be used, each
operating on the alternate cycle because of the input signal. Figure 1.4.10 shows a center-tapped
transformer to provide opposite phase signals. If the transformer is exactly center-tapped, the two
signals are exactly opposite in phase and of the same magnitude. The circuit of Figure 1.4.10 uses a
BJT stage with in-phase output from the emitter and opposite phase output from the collector. If the
gain is made nearly 1 for each output, the same magnitude results. Probably most common would be
using op-amp stages similar to Figure 1.4.11, one to provide an inverting gain of unity and the other
a non-inverting gain of unity, to provide two outputs of the same magnitude but of opposite phase.

Figure 1.4.10: Phase splitter circuit with a center-tapped transformer

101
 Figure 1.4.11: Phase splitter circuit with a BJT transistor

Figure 1.4.12: Phase splitter circuit with op-amp(s)

1.4.4.2 Transformer-Coupled Push-Pull Class B Amplier

Figure 1.4.13: Transformer-coupled push-pull Class B power amplier

The center-tapped transformer on the input produces opposite polarity signals to the two transistor
inputs.
The center-tapped transformer on the output combines the two halves of the AC waveform
together.

102
Push-Pull Operation
• During the positive half of the AC input cycle:

− Transistor Q1 is conducting and Q2 is o.

• During the negative half of the AC input cycle:

− Transistor Q2 is conducting and Q1 is o.

Each transistor produces half of an AC cycle. The output transformer combines the two outputs
to form a full AC cycle.

1.4.4.3 Complementary-Symmetry Push-Pull Class B Amplier

Figure 1.4.14: Complementary-symmetry push-pull Class B power amplier

Using complementary transistors (npn and pnp), it is possible to obtain a full cycle output across a
load using half-cycles of operation from each transistor, as shown in Figure 1.4.14. While a single input
signal is applied to the base of both transistors, the transistors, being of opposite type, will conduct
on opposite half-cycles of the input. The npn-transistor will be biased into conduction by the positive
half-cycle of signal, with a resulting half-cycle of signal across the load as shown in Figure 1.4.15.
During the negative half-cycle of signal, the pnp transistor is biased into conduction when the input
goes negative, as shown in Figure 1.4.16. During a complete cycle of the input, a complete cycle of
output signal is developed across the load. One big advantage of this conguration is avoiding the
need for a transformer.

Figure 1.4.15: Operation on the positive half-cycle of the input

103
 Figure 1.4.16: Operation on the negative half-cycle of the input

1.4.4.4 Power Input

The power supplied to the load by an amplier is drawn from the power supply (or power supplies)
that provides the input or dc power. The amount of this input power can be calculated using

PCC = VCC ICC

where ICC is the average or DC current drawn from the power supplies. In Class B operation, the
current drawn from a single power supply has the form of a full-wave rectied signal, while that drawn
from two power supplies has the form of a half-wave rectied signal from each supply. In either case,
the value of the average current drawn can be expressed as

2 2 vopeak
ICC = iopeak = (1.4.43)
π π RL
where iopeak and vopeak are the peak values of the output current and voltage waveforms, respectively.
Thus, the power input equation becomes

2 VCC vopeak
PCC = (1.4.44)
π RL

1.4.4.5 Power Output

vo2peak
PL = (1.4.45)
2RL

1.4.4.6 Eciency
PL
η% = × 100
PCC
vo2peak /(2RL )
= × 100 (1.4.46)
(2/π)(VCC vopeak /RL )
π vopeak
= × 100 (1.4.47)
4 VCC
vo
= peak × 78.54 (1.4.48)
VCC

104
1.4.4.7 Transistor Power Dissipation
Power dissipated as heat across a transistor in a Class B push-pull conguration is given as

1
PQ = (PCC − PL ) (1.4.49)
2 !
2
V v
1 2 CC opeak vo
= − peak (1.4.50)
2 π RL 2RL
1 VCC vopeak vo2
= − peak (1.4.51)
π RL 4RL

1.4.4.8 Maximum Eciency

Maximum eciency ηmax is achieved at the maximum output power PL(max) , i.e., at the maximum
output swing
vo(max)peak = VCC . (1.4.52)

where each transistor provides half cycle of the output swing.

Thus, maximum eciency ηmax is given as

PL(max)
ηmax % = × 100
PCC |PL(max)
π vo(max)peak
= × 100 ... from (1.4.47) (1.4.53)
4 VCC
π VCC
= × 100 (1.4.54)
4 VCC
π
= × 100 (1.4.55)
4
= 78.54%. (1.4.56)

1.4.4.9 Figure of Merit

Let us nd the value of vopeak in (1.4.51) to give the maximum transistor power dissipation PQ(max) as
follows

dPQ
=0 (1.4.57)
dvopeak PQ(max)
VCC vo
− peak = 0 (1.4.58)
π 2
2
vopeak P = VCC . (1.4.59)
Q(max) π
Substituting (1.4.59) in (1.4.51) we obtain PQmax as follows

2
1 VCC
PQ(max) = . (1.4.60)
π 2 RL

105
 Using (1.4.45) and (1.4.52), we obtain the maximum output power as

2
VCC
PL(max) = .
2RL

Thus, gure of merit (FoM) is given as

PQ(max)
FoM = (1.4.61)
PL(max)
2
VCC /(π 2 RL )
= 2 (1.4.62)
VCC /(2RL )
2
= 2 (1.4.63)
π
∼ 1
= . (1.4.64)
5
This FoM value is quite good. Because, if we want to deliver 10 W to the load, we only need to
select two 2 W-transistors.
1.4.4.10 Crossover Distortion
One big disadvantage of the Class B ampliers is the crossover distortion produced at the
output as shown in below.

Figure 1.4.17: Cross-over distortion at the Class B amplier output

Crossover distortion refers to the fact that during the signal crossover from positive to negative
(or vice versa) there is some nonlinearity in the output signal. This results from the fact that
transistor turn-on voltage is not actually zero volts, i.e., VBE(ON ) 6= 0 V. Input voltage vi (t) itself
turns the transistors ON and OFF. So, during the time when the magnitude of the input signal
is less than the turn-on voltage, i.e., |vi (t)| < VBE(ON ) , both transistors are OFF producing
zero output and causing the crossover distortion.

Biasing the transistors just to the turn-on level VBEQ ∼

= VBE(ON ) , will be the solution. However,
this DC biasing causes static power dissipation, even when there is no AC input. So, the amplier
now becomes a Class AB amplier.

106
1.4.5 Class AB Ampliers

Figure 1.4.18: Quasi-complementary push-pull Class AB power amplier

Notice that transistors Q1 and Q3 in Figure 1.4.18 form a Darlington connection that provides output
from a low-impedance emitter-follower. The connection of transistors Q2 and Q4 forms a feedback-
pair, which similarly provides a low-impedance drive to the load. Resistor R2 can be adjusted to
minimize crossover distortion by adjusting the DC bias condition. The single input signal applied to
the push-pull stage then results in a full cycle output to the load. The quasi-complementary push-pull
amplier is presently the most popular form of power amplier. The voltage across over R2 is adjusted
to provide turn-on voltages for the Darlington and feedback pairs, i.e.,

R2
VR2 ∼
= VCC = 2VBE(ON ) + VEB(ON ) = 3VBE(ON ) . (1.4.65)
R1 + R2 + R3

107
Note that in this conguration we need the capacitor C3 at the output, because the DC bias-level at
VE3 = VE2 = VCC −GN
that point is not zero, i.e.,
2
D
= VCC2
.

Figure 1.4.19: Transformer-coupled push-pull Class AB power amplier.

Conguration in Figure 1.4.19 uses R1 and R2 resistors to bias the two transistors, as shown below

R2
VCC = VBE(ON ) . (1.4.66)
R1 + R2

Figure 1.4.20: Complementary push-pull Class AB power amplier

108
 Conguration in Figure 1.4.20 uses a diode (matched to the Q1 transistor, i.e., VD(ON ) =
VBE(ON ) ) and an adjustable R3 resistor to bias the two transistors, as shown below

R2
V R2 ∼


= VCC + VEE − VD(ON ) = VBE(ON ) . (1.4.67)
R1 + R2 + R3

As the diode is matched with one of the transistors, any changes on the turn-on voltage of this
transistor will be compensated by the change in the turn-on voltage of the diode, e.g., changes
due to temperature.

Figure 1.4.21: Another complementary push-pull Class AB power amplier

Conguration in Figure 1.4.21 uses variable R resistor (or potentiometer) to bias the transistors.
Note that, Q3 transistor increases the turn-o speeds of the power transistors Q1 and Q2 .

1.4.6 Power Transistor Heat Sinking

The maximum power handled by a particular device and the temperature of the transistor junctions
are related since the power dissipated by the device causes an increase in temperature at the junction
of the device. Rated power dissipation is allowed only up to a maximum temperature. Above this
temperature, the device power dissipation capacity gets reduced (or derated), so that at higher case
temperatures the power-handling capacity is reduced, down to 0W at the device maximum case
temperature. When the device is mounted on some form of heat sink, its power handling capacity
can approach the rated maximum value more closely. A few heat sinks are shown in Figure 1.4.22(a).
When the heat sink is used, the heat produced by the transistor dissipating power has a larger area
from which to radiate (transfer) the heat into the air, thereby holding the case temperature to a much
lower value than would result without the heat sink.
Figure 1.4.22(b) shows a typical power derating curve for a silicon transistor. The curve shows
that the manufacturer will specify an upper temperature point, after which a linear derating takes
place. For silicon, the maximum power that should be handled by the device does not reduce to 0W
◦
until the case temperature is 200 C.

109
 (b)
(a)

Figure 1.4.22: Heat-related gures: (a) heat sinks, (b) a typical power derating curve.

1.4.6.1 Thermal-to-Electrical Analogy

Figure 1.4.23: Thermal-to-electrical analogy.

A picture of how the junction temperature (TJ ), case temperature (TC ), and ambient (air) temperature
(TA ) are related by the device heat-handling capacitya temperature coecient usually called thermal
resistanceis presented in the thermal-electric analogy shown in Figure 1.4.23.
In providing a thermal-electrical analogy, the term thermal resistance is used to describe heat
eects by an electrical term. The terms in Figure 1.4.23 are dened as follows:

• θJC = transistor thermal resistance (junction to case)

• θCS = insulator thermal resistance (case to heat sink)

• θSA = heat-sink thermal resistance (heat sink to ambient)

• θJA = total thermal resistance (junction to ambient)

110
Using the electrical analogy for thermal resistances, we can write:

θJA = θJC + θCS + θSA (1.4.68)

The analogy can also be used in applying Kirchho 's law to obtain:

TJ = PD θJA + TA (1.4.69)

The last relation shows that the junction temperature oats on the ambient temperature and that
the higher the ambient temperature, the lower the allowed value of device power dissipation.

Example 1.14: ◦
A silicon power transistor is operated with a heat sink (θSA = 1.5 C/W).
◦ ◦
The transistor, rated at 150 W (25 C), has θJC = 0.5 C/W, and the mounting insulation has
θCS = 0.6 ◦ C/W. What maximum power can be dissipated if the ambient temperature is 40 ◦ C
◦
and TJmax = 200 C?

Solution:
TJ − TA 200 − 40
PD = = ≈ 61.5 W.
θJC + θCS + θSA 0.5 + 0.6 + 1.5

1.4.7 Class C Ampliers

Figure 1.4.24: Class C amplier circuit.

A Class C amplier, as that shown in Figure 1.4.24, is biased to operate for less than 180◦ of the input
signal cycle. The tuned circuit in the output, however, will provide a full cycle of output signal for
the fundamental or resonant frequency of the tuned circuit (L and C tank circuit) of the output. This
type of operation is therefore limited to use at one xed frequency, as occurs in a communications
circuit, for example.
Operation of a Class C circuit is not intended for large-signal or power ampliers.

111
1.4.8 Class D Ampliers

Figure 1.4.25: Block diagram of a Class D amplier.

A Class D amplier is designed to operate with digital or pulse-type signals in a conguration shown
in Figure 1.4.25. An eciency of over 90% is achieved using this type of circuit, making it quite
desirable in power ampliers. It is necessary, however, to convert any input signal into a pulse-type
waveform before using it to drive a large power load and to convert the signal back to a sinusoidal-type
signal to recover the original signal. Figure 1.4.26 shows how a sinusoidal signal may be converted
into a pulse-type signal using some form of sawtooth or chopping waveform to be applied with the
input into a comparator-type op-amp circuit so that a representative pulse-type signal is produced.
Figure 1.4.25 shows a block diagram of the unit needed to amplify the Class D signal and then
convert back to the sinusoidal-type signal using a low-pass lter. Since the amplier's transistor
devices used to provide the output are basically either o or on, they provide current only when they
are turned on. Since most of the power applied to the amplier is transferred to the load, the eciency
of the circuit is typically very high. Power MOSFET devices have been quite popular as the driver
devices for the Class D amplier.

Figure 1.4.26: Chopping of sinusoidal waveform to produce digital waveform.

112
Example 1.15: (2005-2006 MII) Consider the amplier circuits given in the gures belowwhere
VBE(ON ) = 0.7 V.

For the circuit shown in Fig-A with vi = 1 V sin(ωt)

a) Draw vo ,
b) Calculate the power PL dissipated over RL ,
c) Calculate the eciency of the power amplier consisting of transistors Q1 and Q2 .
For the circuit shown in Fig-B with vi = 1 V sin(ωt)
d) Draw vo ,
e) Compare the two amplier circuit designs given in Fig-A and Fig-B, and express which
design is more preferable. Briey explain your answer.

HINT: Consider your answers to items a) and d).

Fig-A Fig-B

Figure 1.4.27: Power amplier circuits for Example 1.15.

Solution: a) We can calculate the voltage gain Av as

vo 150k
Av = =1+ = 16.
vi 10k

So, the output vo is given by

vo = Av vi = 16 V sin(ωt).

113
 Figure 1.4.28: Output for the circuit of Fig-A in Figure 1.4.27.

2
vo(peak) 162
b) PL = = = 16 W
2RL 2(8)
c) As we know the output power let us calculate the total power PCC drawn from the voltage
supplies

PCC = VCC ICC

2 vo(peak)
= VCC
π RL
2 16
= 20
π 8
= 25.465 W.

Now, eciency η is given by

PL
η% = × 100
PCC
16
= × 100
25.465
= 62.83%.

d) There is a cross-over distortion at the output due to the 0.7 V turn-on voltage drop across the
base-emitter junctions of the transistors Q1 and Q2 . So, the output vo of Fig-B will be plotted
as below

114
 Figure 1.4.29: Output for the circuit of Fig-B in Figure 1.4.27.

e) In Fig-B, Class B power amplier (in a complementary push-pull structure) is connected

after a pre-amplier stage consisting of a non-inverting opamp amplier. This complementary
push-pull Class B amplier conguration acts like a voltage-buer amplier (i.e. like an emitter-
follower).

However the complementary (npn-pnp) BJT ampliers turn-on when sucient voltage dierence(≥
0.7 V) exists between their base-emitter terminals (BE-EB). Q1 is ON at the positive-half cycle
when (VB1 VE1 ) ≥ 0.7 V and similarly Q2 is ON at the negative-half cycle when (VB2 VE2 ) ≤
−0.7 V.

Due to this 0.7 V turn-on voltage drop across the base-emitter junctions of the complementary
BJT transistors, we observe a cross-over distortion at the output of Fig-B as shown in the
answer of item d)".

In Fig-A, negative feedback is connected to the output of the power amplier eliminating the
cross-over distortion by enforcing the suitable biasing voltage at the transistor bases. So, the
conguration in Fig-A is more preferable to the conguration in Fig-B.

115
1.5 Oscillators
How the feedback circuit provides operation as an oscillator is obtained by noting the denominator in
the basic negative feedback equation(1.1.20),
A(ω)
Af (ω) = . (1.5.1)
1 + β(ω)A(ω)
When β(ω)A(ω) = −1 or magnitude 1 at a phase angle of 180◦ , the denominator becomes 0 and the
gain with feedback, Af (ω), becomes innite. Thus, an innitesimal signal (noise voltage) can provide
a measurable output voltage, and the circuit will be unstable and have oscillations. So, this criterion

β(ω)A(ω) = −1 (1.5.2)

is known as the Barkhausen criterion for oscillation.

If we have the negative feedback loop-gain βA to be −1 only at a single frequency, i.e.,

β(ω0 )A(ω0 ) = −1, (1.5.3)

then we will have oscillations only at ω = ω0 .Thus, this circuit will act as an oscillator even without
an input signal (noise in the circuit acts as an input signal), will be called an oscillator circuit where
it produces a signal only at the frequency of ω = ω0 .
To understand how a feedback circuit performs as an oscillator, consider the positive feedback
circuit Figure 1.5.1 below.

Figure 1.5.1: Positive feedback circuit used as an oscillator.

When the switch at the amplier input is open, no oscillation occurs. Consider that we have a
ctitious voltage at the amplier input, vi . This results in an output voltage vo = Avi after the
amplier stage and in a voltage vf = βAvi after the feedback stage.Thus, we have a feedback voltage
vf = βAvi , where βA is referred to as the loop-gain. If the circuits of the base amplier and feedback
network provide βA of a correct magnitude and phase, vf can be made equal to vi . Then, when the
switch is closed and ctitious voltage vi is removed, the circuit will continue operating since the
feedback voltage is sucient to drive the amplier and feedback circuits resulting in a proper input
voltage to sustain the loop operation. The output waveform will still exist after the switch is closed
if the condition βA = 1 is met.
In reality, no input signal is needed to start the oscillator going. Only the condition βA = 1
must be satised for self-sustained oscillations to result. In practice, βA is made greater than 1 and

116
the system is started oscillating by amplifying noise voltage, which is always present. Saturation
factors in the practical circuit provide an average value of βA = 1. The resulting waveforms are never
exactly sinusoidal. However, the closer the value βA is to exactly 1, the more nearly sinusoidal is the
waveform.
Figure 1.5.2 below shows how the noise signal results in a buildup of a steady-state oscillation
condition.

Figure 1.5.2: Build-up of steady-state oscillations.

1.5.1 Types of Oscillator Circuits

Main classes of oscillator circuits are given below

1. Phase-Shift Oscillator

2. Wien-Bridge Oscillator

3. Tuned Oscillator Circuits

4. Crystal Oscillator

5. Unijunction Oscillator

117
1.5.2 Phase-Shift Oscillator

Figure 1.5.3: Idealized phase-shift oscillator.

• In this conguration (where A is negative), feedback gain is given by

1
β(ω) = (1.5.4)
1− 5α2 − j (6α − α3 )

where α = 1/(ωRC). The oscillation occurs at a frequency ω0 where ∠β(ω0 ) = 180◦ .

Thus, the oscillation frequency f0 which cancels the imaginary part is given by

1
f0 = √ (1.5.5)
2πRC 6
√
• As α|ω0 = 6, feedback gain at the oscillation frequency is given by

1
β(ω0 ) = − (1.5.6)
29

The amplier must supply enough gain to compensate for losses. The overall gain must be unity.
Thus, the absolute gain of the amplier stage must be greater than |1/β(ω0 )|, i.e.,

|A| > 29. (1.5.7)

• The RC networks provide the necessary phase shift for a positive feedback. They also determine
the frequency of oscillation.

118
1.5.2.1 FET Phase-Shift Oscillator

Figure 1.5.4: FET phase-shift oscillator.

Example 1.16: It is desired to design phase-shift oscillator(as in Figure 1.5.4) using an FET
having gm = 5 mS, rds = 40 kΩ, and feedback circuit resistor value of R = 10 kΩ. Select the
value of C for oscillator operation at 1 kHz and RD for A > 29 to ensure oscillator operation.

Solution: Since f0 = 1 √
2πRC 6
, we can solve for C as follows

1 1
C= √ = √
2πf0 R 6 2π(1k)(10k) 6
= 6.5 nF.

0 0
Next, we solve for RD where RD = rds ||RD to provide a gain of A = 40 (this allows for some
0
loading between RD and the feedback network input impedance):

0
|A| = gm RD = 40
0 |A| 40
RD = = = 8 kΩ.
gm 5 × 10−3

Finally, we solve for RD to be

0
rds RD
RD = 0
= 10 kΩ.
rds − RD

119
1.5.2.2 BJT Phase-Shift Oscillator

Figure 1.5.5: BJT phase-shift oscillator.

In Figure 1.5.5 above:

R0 = R − Ri = R − R1 ||R2 ||hie
.

For the loop-gain to be greater than unity, the requirement on the current gain of the transistor
is found to be
R RC
hf e > 23 + 29 +4 . (1.5.8)
RC R

1.5.2.3 Opamp Phase-Shift Oscillator

Figure 1.5.6: Op-amp phase-shift oscillator.

120
 In Figure 1.5.6 above, in order to sustain oscillation, i.e., β(ω0 )A(ω0 ) ≥ 1 we need to have

Rf
≥ 29 (1.5.9)
R1
.

1.5.3 Wien-Bridge Oscillator

Figure 1.5.7: Wien-bridge oscillator circuit using op-amp amplier.

Let us rst dene Z1 = R1 + ZC1 and Z2 = R2 ||ZC2 .

• Then, the positive feedback loop-gain is given as

   
Z2 R3 1 R3
β(ω)A(ω) = 1+ = 1+ (1.5.10)
Z1 + Z2 R4 1 + Z1 /Z2 R4
| {z } | {z }
β(ω) A(ω)

In order to have the loop-gain to be 1, the Z1 /Z2 needs to have zero phase, i.e., imaginary part
needs to be zero. Thus, the oscillation frequency f0 is found to be

1
f0 = √ (1.5.11)
2π R1 C1 R2 C2

• Hence, the positive feedback loop-gain at the oscillation frequency f0 becomes

 
1 R
β(ω0 )A(ω0 ) =   1+ 3 (1.5.12)
1+ R1
+C2 R4
R2 C1

In order to sustain the oscillation, i.e., β(ω0 )A(ω0 ) ≥ 1,

R3 R1 C2
≥ + (1.5.13)
R4 R2 C1

121
• Thus, when R1 = R2 = R and C1 = C2 = C , then

1
f0 = (1.5.14)
2πRC
R3
≥ 2. (1.5.15)
R4

Figure 1.5.8: Wien-bridge oscillator circuit for Example 1.16.

Example 1.17: Calculate the resonant frequency of the Wien bridge oscillator shown in
Figure 1.5.8 above.

Solution: Oscillation frequency is given by

1 1
f0 = = = 3120.7 Hz.
2πRC 2π(51k)(1n)

Example 1.18: Design the RC elements of a Wien bridge oscillatoras in Figure 1.5.7 for
operation at f0 = 10 kHz.

Solution: Using equal values of R and C, we can select R = 100 kΩ and calculate the required
value of C as
1 1
C= = = 159 pF.
2πf0 R 2π(10k)(100k)

We can use R3 = 300 kΩ and R4 = 100 kΩ to provide a ratio R3 /R4 greater than 2 for oscillation
to take place.

122
1.5.4 Tuned Oscillator Circuits

Figure 1.5.9: Basic conguration of tuned (or resonant) circuit oscillator.

Figure 1.5.10: Resonant element selection for a tuned oscillator

Tuned Oscillators use a parallel LC resonant circuit (LC -tank) to provide the oscillations.

There are two common types:

◦ Colpitts: The resonant circuit is an inductor and two capacitors.

◦ Hartley: The resonant circuit is a tapped inductor or two inductors and one capacitor.
1.5.4.1 Colpitts Oscillator Circuits
FET Colpitts Oscillator

123
 Figure 1.5.11: FET Colpitts Oscillator.

Oscillator frequency
1
f0 = p (1.5.16)
2π LCeq
C1 C2
where Ceq = .
C1 + C2

BJT Colpitts Oscillator

124
 Figure 1.5.12: BJT Colpitts Oscillator.

Opamp Colpitts Oscillator

Figure 1.5.13: Op-amp Colpitts Oscillator.

1.5.4.2 Hartley Oscillator Circuits

FET Hartley Oscillator
125
 Figure 1.5.14: FET Hartley Oscillator.
Oscillator frequency
1
f0 = p (1.5.17)
2π Leq C
where Leq = L1 + L2 + 2M with M denoting the mutual inductance.

BJT Hartley Oscillator

Figure 1.5.15: BJT Hartley Oscillator.

126
1.5.5 Crystal Oscillator
A crystal oscillator is basically a tuned-circuit oscillator using a piezoelectric crystal as a resonant
tank circuit. The crystal (usually quartz) has a greater stability in holding constant at whatever
frequency the crystal is originally cut to operate. Crystal oscillators are used whenever great
stability is required, such as in communication transmitters and receivers.

A quartz crystal (one of a number of crystal types) exhibits the property that when mechanical
stress is applied across the faces of the crystal, a dierence of potential develops across opposite
faces of the crystal. This property of a crystal is called the piezoelectric eect. Similarly, a
voltage applied across one set of faces of the crystal causes mechanical distortion in the crystal
shape.

When alternating voltage is applied to a crystal, mechanical vibrations are set up. These vi-
brations having a natural resonant frequency dependent on the crystal. Although the crystal
has electromechanical resonance, we can represent the crystal action by an equivalent electrical
resonant circuitas shown in Figure 1.5.16(a). The inductor L and capacitor C represent elec-
trical equivalents of crystal mass and compliance, while resistance R is an electrical equivalent
of the crystal structure's internal friction. The shunt capacitance CM represents the capacitance
due to mechanical mounting of the crystal. Because the crystal losses, represented by R, are
small, the equivalent crystal Q-value (quality factor) is high (typically 20000). Values of Q up
6
to almost 10 can be achieved by using crystals.

The crystal has two resonant frequencies as shown in Figure 1.5.16(b):

◦ Series resonant: RLC determine the resonant frequency. The crystal has a low impedance.
◦ Parallel resonant: RL and CM determine the resonant frequency. The crystal has a high
impedance.

The series and parallel resonant frequencies are very close, within 1% of each other.

127
 (b)
(a)

Figure 1.5.16: Crystal operation: (a) electrical equivalent circuit, (b) crystal impedance versus fre-
quency.

Series-Resonant Crystal FET Oscillator

Figure 1.5.17: Crystal-controlled FET oscillator circuit using crystal in series-feedback path.

Series-Resonant Crystal Opamp Oscillator

128
 Figure 1.5.18: Crystal-controlled Opamp oscillator circuit using crystal in series-feedback path.

Parallel-Resonant Crystal BJT Oscillator

Figure 1.5.19: Crystal-controlled BJT oscillator operating in parallel-resonant mode.

129
1.5.6 Unijunction Oscillator

Figure 1.5.20: Basic unijunction oscillator circuit.

Unijunction transistor (UJT) can be used in a single-stage oscillator circuit to provide a pulse
signal suitable for digital-circuit applications.
The unijunction transistor can be used in what is called a relaxation oscillator as shown by the
basic circuit in Figure 1.5.20 above. Resistor RT and capacitor CT are the timing components
that set the circuit oscillating rate.

The oscillating frequency may be calculated as

1
f0 =   (1.5.18)
1
RT CT ln 1−η

where η is the unijunction transistor intrinsic stand-o ratio.

Typically, a unijunction transistor has a stand-o ratio from 0.4 to 0.6, i.e., 0.4 ≤ η ≤ 0.6. Using
a value of η = 0.5 gives us
1.5
f0 ∼
= (1.5.19)
RT CT
Capacitor CT is charged through resistor RT toward supply voltage VBB . As long as the capacitor
voltage VE is below a stand-o voltage (VP ) given by

VP = η (VB2 − VB1 ) + VB1 + VD(ON ) ∼

= ηVBB + VD(ON ) (1.5.20)

the unijunction emitter lead appears as an open circuit. When the emitter voltage across ca-
pacitor CT exceeds this value (VP ), the unijunction circuit res, discharging the capacitor, after
which a new charge cycle begins.

130
 Figure 1.5.21: Unijunction oscillator waveforms.

When the unijunction res, a voltage rise is developed across R1 and a voltage drop is developed
across R2 sawtooth voltage
as shown in Figure 1.5.21 above. The signal at the emitter is a
waveform that at B1 is a positive-going pulse and at B2 is a negative-going pulse.

131
 Figure 1.5.22: Some unijunction oscillator circuit congurations.

A few circuit variations of the unijunction oscillator are provided in Figure 1.5.22 above.

(a) (b)

Figure 1.5.23: Unijunction transistor(UJT): (a) basic construction, (b) equivalent circuit.

Basic construction and equivalent circuit representation of the UJT is given in Figure 1.5.23
above.

132
Chapter 2
Digital Electronics

2.1 Properties of Digital Integrated Circuits

We are going to introduce the general properties and denitions common to all digital inte-
grated circuit families. These properties and denitions include voltage transfer charac-
teristic (output voltage vs. input voltage), Fan-in, Fan-out, power dissipation and
propagation delay.
Five basic logic operations, namely NOT, AND, OR, NAND and NOR, are used to investigate
the properties of digital circuits, because any complex logical operation can be implemented by
these ve logic operations. The electronic circuit which performs one of these logic functions is
called as a gate. The logic gates that perform one or more of the basic operations are called
combinational gates.In this part of the course, we are mostly investigate the properties of such
combinational gates.

The voltages (or currents) in digital logic circuits have two possible states corresponding to two
binary variables:0 and 1. We usually dene the LOW voltage to correspond to a binary 0 and
the HIGH voltage to correspond to a binary 1.
As we can obtain an inverter (or non-inverter) from NOR and NAND (or from OR and AND
gates), we are going to analyze the properties of digital circuit families mostly by starting with
the analysis of the inverter or non-inverter gate.

2.1.1 Inverter and Non-Inverter Gates

Figure 2.1.1(a) and Figure 2.1.1(b) below show the circuit symbols for the inverter gate. The
small circle denotes logical inversion (it makes no dierence whether the inverting circle is at the
input or output). That is, if the input voltage is low, the output voltage will be high and vice
versa. This gate is also referred to as a NOT gate, since it performs the logical NOT operation.

(a) (b)

Figure 2.1.1: Inverter symbols: (a) inverter symbol, (b) alternate inverter symbol.

133
 Figure 2.1.2(a) and Figure 2.1.2(b) below show the circuit symbols for the non-inverter gate,
or sometimes referred to as a buer.

(a) (b)

Figure 2.1.2: Non-inverter symbols: (a) non-inverter symbol, (b) alternate non-inverter symbol.

2.1.2 Ideal Inverter

Figure 2.1.3(a) below shows an ideal inverter gate operating with a single power supply, VCC .

(a)

(b)

Figure 2.1.3: Ideal inverter: (a) operates from a single power supply, (b) voltage transfer characteristic.

Figure 2.1.3(b) above shows the voltage transfer characteristic (VTC) of the ideal inverter gate,
where the logical 1 is ideally at the power supply voltage VCC and the logical 0 is ideally at
ground (0 V). Logic gates with output voltage transitions from ground to the power supply
voltage are called to operate rail-to-rail.
The transition between output logic states ideally occurs abruptly at an input value of VCC /2.
Thus, logical input 0 (or input LOW) is represented by the voltage range 0 ≤ VIN < VCC /2,
since an input in this range generates a logical 1 output (or output HIGH) state.

Similarly, logical input 1 (or input HIGH) is represented by the voltage range VCC /2 < VIN ≤
VCC .

The input voltage VIN = VCC /2 has an undened output and will cause unpredictable results,
and is therefore avoided.

2.1.3 Inverter Voltage Transfer Characteristic

Figure 2.1.4 below shows the linearized form of the voltage transfer characteristic (VTC) of an inverter.

134
 Figure 2.1.4: Linearized voltage transfer characteristic (VTC) of an inverter

Indicated on the output axis are the voltages VOH and VOL which correspond to the output
high and output low voltage levels, respectively.
On the input axis, VIL is the maximum input voltage that is considered as a LOW input (i.e.,
that provides a HIGH output), and VIH is the minimum input voltage that is considered as a
HIGH input (i.e., that provides a LOW output),i.e.,

LOW,

 if VIN ≤ VIL
VIN =

HIGH, if VIN ≥ VIH (2.1.1)

undened, if VIL < VIN < VIH



It is customary to indicate output voltages VOL and VOH also on the input axis. Because output
voltages VOL and VOH for the current inverter will be the inputs for the next inverter. If we
want these outputs VOL and VOH to be considered LOW and HIGH, respectively, for the next
inverter, then we must always have

VOL < VIL (2.1.2)

VOH > VIH . (2.1.3)

One of the critical points labelled on the VTC graph is the midpoint voltage, VM , which is
dened as the point on the transfer characteristic where VOU T = VIN and ideally should appear
at the center of the transition region. VM can be found graphically by drawing the VOU T = VIN
line (the unity slope line) on the VTC and nding its intersection with the VTC.

135
Logic swing, VLS , is dened as the magnitude of the voltage dierence between the output high
and low voltage levels, i.e.,

VLS = VOH − VOL (2.1.4)

Transition width, VT W , is dened as the magnitude of the voltage dierence between VIH and
VIL voltage levels, i.e.,

VT W = VIH − VIL (2.1.5)

The low and high voltage noise margins, VN M L and VN M H , represent a safety margin for low
and high voltage levels, respectively.

VN M L = VIL − VOL (2.1.6)

VN M H = VOH − VIH (2.1.7)

Extraneous noise voltages must have magnitudes less than the voltage noise margins.

The eects of input variations are also quantied in terms of the noise sensitivities. The low
and high noise sensitivities are dened as the dierence between the input and midpoint voltage
for VIN at VOL and VOH , respectively, i.e.,

VN SL = VM − VOL (2.1.8)

VN SH = VOH − VM (2.1.9)

The quantity noise immunity is the ability of a gate to reject noise, and dened as the ratio
of noise sensitivities and the logical swing, i.e.,

VN SL
VN IL = (2.1.10)
VLS
VN SH
VN IH = (2.1.11)
VLS

Example 2.1: For the circuit in Figure 2.1.5 below, determine VOL , VOH , VIL , VIH , VM , VT W ,
VLS , VN M L , VN M H , VN SL , VN SH , VN IL and VN IH .

136
 Figure 2.1.5: A VTC example

2.1.4 Fan-In and Fan-Out

A general logic gate has multiple inputs and multiple outputs. By multiple outputs, we mean
the output of a given gate is connected to (i.e., driving) the inputs of several load gates.

The term fan-in is used to describe the number of inputs of a gate, as shown in Figure 2.1.6(b)
below. Similarly, the term fan-out is used to describe the number of outputs of a gate, as shown
in Figure 2.1.6(a) below.

(a)

(b)

Figure 2.1.6: Fan-in and fan-out: (a) Fan-in (b) Fan-out

Figure 2.1.7 below shows the input and output impedance model of an inverter.

137
 Figure 2.1.7: Input and output impedance model of an inverter.

Figure 2.1.8: Static driving of multiple (identical) inverters.

Maximum fan-out of a digital logic circuit is the maximum number of load gates that can be
connected to the output of a gate in parallel as shown in Figure 2.1.8 above. From the static
behaviour point of view, it is restricted by its input and output currents,

Nmax = min NOL(max) , NOH (max) (2.1.12)

where
 
IOL(max)
NOL(max) = 0
(2.1.13)
IIL
 
IOH (max)
NOH (max) = 0
(2.1.14)
IIH

and b·c denotes the oor function.

138
 Figure 2.1.9: Dynamic driving of multiple (identical) inverters.

As input current of MOSFET's is the innitesimal gate current, this might suggest that logic
circuits with MOSFETs will have an innite fan-out. However, this is not the case. Fan-out
of MOSFET digital circuits is limited by the input capacitance of the gate which is the gate
oxide capacitance due to dynamic behaviour. As you see in Figure 2.1.9 above, equivalent load
capacitance will be higher (parallel capacitances are added together) limiting the maximum
operating frequency. In other words, maximum required operating frequency will limit the
maximum number of load gates.

Example 2.2: For the circuit in Figure 2.1.10 below, calculate the maximum fan-out.

Figure 2.1.10: Inverter with input and output currents shown.

2.1.5 Transient Characteristics

Digital circuits have niteswitching speeds, i.e., switching a voltage from high to low (or low
to high) requires a nite amount of time called turn-on tON and turn-o tOF F time.

Additionally, when the input voltage changes from one level to another, the output voltage is
delayed in time, which is referred to as propagation delay.
For digital circuits employing BJTs, these time limitations are caused by the time required to
store and remove charge from the base region.

139
Similarly, transient characteristics of digital circuits employing MOSFETs are limited by the
gate oxide capacitance.

Ideally, turn-on, turn-o and propagation delay times are zero, as shown in the ideal transient
response of the inverter in Figure 2.1.11 below.

Figure 2.1.11: Ideal transient response of an inverter.

Figure 2.1.12: Switching speed denitions: (a) input pulse (b) output pulse.

Figure 2.1.12 above shows an input pulse and output response of an inverter. Here, td is the
delay time, tr is the rise time, ts is the storage time, tf is the fall time, tON = td + tr is the
turn-on time and tOF F = ts + tf is the turn-o time.

140
The 10% VOH and 90% VOH points are marked on both the rising and falling edges of the output
voltage. The rise time tr and fall time tf are the times associates with charging and discharging
load capacitances.

The delay time td and storage time ts are associated with the storage charge of PN junctions.

Figure 2.1.13: Propagation delay denitions: (a) input waveform (b) output response.

Figure 2.1.13 above shows an input waveform and output response of an inverter. Here, tP LH
is the low-to-high propagation delay timereferring to the low-to-high transition of the output
and tP HL is the high-to-low propagation delay timereferring to the high-to-low transition of the
output.

The 50% points are labelled on the rising and falling edges of both the input and output wave-
forms.The 50% points are used to dened the time required for the output to respond to the
input.

The overall propagation delay time tp(avg) is dened as the average of low-to-high and high-to-low
propagation delay times, i.e.,
tP LH + tP HL
tp(avg) = . (2.1.15)
2

141
2.1.6 Average Power Dissipation

Figure 2.1.14: Power dissipation in a logic gate with two power supplies.

A logic circuit with two power supplies is shown in Figure 2.1.14 above. As the power dissi-
pated in this gate for the output high and output low states are dierent, the average power
dissipation PD(avg) for this gate with two possible states are given as
PD(avg) = PCC(avg) + PEE(avg) (2.1.16)

PCC(OH) + PCC(OL) PEE(OH) + PEE(OL)

= + (2.1.17)
2 2
ICC(OH) + ICC(OL) IEE(OH) + IEE(OL)
= VCC + VEE (2.1.18)
2 2

As we will see later, static power dissipation will be zero in CMOS circuits. Hence, we have to
consider the dynamic power dissipation as given below

2
PD(dynamic) = CL f VLS . (2.1.19)

[]where CL is the load capacitance, f is the frequency of switching and VLS is the voltage swing
over the load. In CMOS circuits operate rail-to-rail, so VLS = VDD , where VDD is value of the
DC power supply.

2.1.7 Power-Delay Product

Low power dissipation and short propagation delay times are both desirable for digital logic cir-
cuits. However, faster propagation times are achieved at the cost of increased power dissipation.
Conversely, lower power dissipation results in longer propagation delays

A practical gure of merit used for digital logic gates is the power-delay product or speed-
power product given by
P D = PD(avg) × tp(avg) (2.1.20)

The unit of power-delay product is in terms of joules and the lower the value of the power-delay
product the better.

For a logic family, this power-delay product can be considered as constant. In other words, if
you want to decrease power dissipation by increasing resistor values, the propagation delay will
increase accordingly. You can change the power-delay product by redesigning the whole digital
circuit (using dierent design and/or dierent components).

142
2.1.8 Logic Families
A summary of logic families are shown as a diagram in Figure 2.1.15 below.

Figure 2.1.15: A diagram of logic families.

All logic families have dierent properties. For example, CMOS logic circuits have very low
power dissipations.

For another example, propagation delay and power dissipation characteristics for TTL and STTL
families are given in Table 2.1 below.

143
Table 2.1: Power dissipation and propagation delay characteristics of TTL and STTL families

Family Power Prop. Delay

TTL 10 mW 9 ns
STTL 20 mW 3 ns
LSTTL 2 mW 9 ns
ASTTL 10 mW 2 ns
ALSTTL 1 mW 4 ns
FAST 4 mW 2 ns

144
2.2 Diodes
2.2.1 Diode Model
Diodes are important elements in digital electronic circuits, as well as they are used to perform
various logic operations, they are also used as variable capacitors, DC voltage level shifters and
clamping diodes at logic circuit inputs.

Symbols for PN junction diodes and MN junction diodes are shown in Figure 2.2.1(a) and
Figure 2.2.1(b) below, respectively.

(a) (b)

Figure 2.2.1: Diode symbols: (a) PN junction diode, (b) MN Schottky barrier diode.

PN junction diodes are formed from the combination of P-type and N-type regions. Usually,
PN junctions in integrated circuits (ICs) are usually formed by utilizing the two out of the three
regions of a bipolar junction transistor, instead of a separate device structure. Turn-on voltage
for a PN junction diode is VD(ON ) = 0.7 V.

MN junction (Schottky Barrier) diodes are formed from the combination of a metal and an
−
N -type semiconductor. Metal used in MN junction diodes is mostly platinum silicide (Pt5 Si2 ).
As there are no holes present, MN junction diodes are much faster than PN junction diodes.
Turn-on voltage for a Schottky Barrier (MN junction) diode is VSBD(ON ) = 0.3 V.

Cross sections of some example PN and MN junction diodes as shown in Figure 2.2.2(a) and
Figure 2.2.2(b) below, respectively, in order to highlight some of the fabrication properties.

(a) (b)

Figure 2.2.2: Diode cross sections: (a) PN junction diode, (b) MN Schottky barrier diode.

Diode current-voltage (IV) characteristics are normally governed by the well-known Shockley's
diode equation,
ID = IS eVD /γ − 1


(2.2.1)

145
where IS is the reverse saturation current (typically pA for PN junction diodes and µA for MN
junction diodes) and γ = φT = kT /q is the thermal voltage (typically γ = 26 mV at 300 K)
with k representing the Boltzman constant, T representing the temperature in kelvins and q
representing the elementary charge.

In the analysis of digital circuits, we are going to use the simplied diode model as shown in
Figure 2.2.3 and summarized in Table 2.2 below

Figure 2.2.3: IV characteristics of the simplied diode model.

The transition point from cuto mode to conduction mode (i.e., when the current is not yet
owing) is called as edge of conduction (EOC).
Table 2.2: Diode modes of operation

Junction Bias Mode of Operation

Reverse Cuto (OFF)

Forward Conducting (ON)

The large signal diode model used in SPICE in shown in Figure 2.2.4 below.

Figure 2.2.4: SPICE diode model.

146
 PN Junction capacitance can be utilized in ICs by applying a negative bias to a diode. Diodes
used for this purpose are referred to as varactor diodes and have the modied circuit symbol
presented in Figure 2.2.5 below.

Figure 2.2.5: Varactor diode (voltage dependent capacitor for VD < 0).

2.2.2 Clamping Diodes

When the input to a gate is switched from high-to-low, the input voltage sometimes swings well
beyond 0 V. This is called as ringing and may cause physical damage to the gate.

Connecting clamping diodes to each input of a gate, as shown in Figure 2.2.6 below, eliminates
this problem by preventing inputs from falling below −0.7 V. The diodes will not aect the
operation of the gate, as the diodes are open circuit for positive inputs.

Figure 2.2.6: Input clamping diodes.

Clamping diodes can be also connected to the output(s) of a gate.

Most TTL/STTL families employ clamping diodes at their inputs and sometimes also at their
outputs.

2.2.3 Level-Shifting Diodes

It is often required to change the voltage level across particular portions of digital circuits, e.g.,
to level shift the output voltage.

Another use of the diode forward voltage is to ensure that sub-circuits with complementary
objectives are not conducting simultaneously. For example, TTL circuits employ two output
drivers. Only one driver should be working for the output-low state, while only the other driver
should be working for the output-high state. Placement of a voltage level-shifting device between
the two drivers ensures the desired operation by allowing only one driver to be on at a time.

147
Example 2.3: For the circuit in Figure 2.2.7 below, determine the level-shifting voltage Vshift .

Figure 2.2.7: A level-shifting diodes example.

148
2.3 BJT Transistors
Bipolar junction transistors (BJTs) are very important in digital circuits, e.g., TTL circuits are
based on BJTs. Figure 2.3.1 below shows a 3D cross-section (without metallization) of an NPN
BJT fabricated with the junction isolated technology.

Figure 2.3.1: Three-dimensional cross-section (without metallization).

In some BJT logic families (e.g., TTL), multiple inputs are achieved by using multi-emitter BJTs
as shown in Figure 2.3.2(a) below.

(a) (b)

Figure 2.3.2: Multi-emitter NPN transistor cross-sections with junction isolation technology: (a) BJT,
(b) Schottky-clamped BJT.

A multi-emitter Schottky-clamped BJT (SBJT) is shown in Figure 2.3.2(b) above. The base
contact is extended over the N collector region, thus placing a Schottky Barrier (MN) diode in
parallel with the base-collector PN junction. This device operates much faster than a normal
BJT, and an SBJT does not go into saturation mode.

The most frequently used notation and symbols for BJT transistors are shown in Figure 2.3.3
below for the NPN and PNP transistors.

149
Figure 2.3.3: Notation and symbols used for BJT transistors: (a) NPN transistor, (b) PNP transistor.

2.3.1 Ebers-Moll BJT Model

Ebers-Moll model is a well-known BJT model, shown for an NPN BJT in Figure 2.3.4, can be used
to calculate the terminal currents for all modes of operation.

150
 ID,BE = IES eVBE /γ − 1


(2.3.1)

ID,BC = ICS eVBC /γ − 1

(2.3.2)

IES is the base-emitter reverse saturation current,

ICS is the base-collector reverse saturation current,

γ is the thermal voltage (kT /q = 26 mV at 300 K).

IE = ID,BE − αR ID,BC (2.3.3)

IC = αF ID,BE − ID,BC (2.3.4)

IB = IE − IC (2.3.5)

αF and αR are the common base forward and

reverse amplication factors. (typically αF ≈ 1
and 0.2 ≤ αR ≤ 0.6)

Reciprocity theorem:
IS = αF IES = αR ICS (2.3.6)

IS is known as the transport saturation current.

Figure 2.3.4: Ebers-Moll NPN BJT model.

2.3.2 BJT Modes of Operation

A BJT transistor has two PN junctions: the base-emitter PN junction (BE junction) and the
base-collector PN junction (BC junction), as depicted in Figure 2.3.3 and Figure 2.3.4 above.
As either junction can be forward or reverse biased, there are four modes of operation (or four
transistor states) as shown in Table 2.3 below.

151
 Table 2.3: BJT modes of operation

BE Junction BC Junction Mode of Operation

Bias Bias
Reverse Reverse Cuto (OFF)

Forward Reverse Forward Active (FA)

Reverse Forward Reverse Active (RA)

Forward Forward Saturation (SAT)

(Forward Saturation (FSAT) or

Reverse Saturation (RSAT) in reality)

In all modes of operation, Kircho 's Current Law (KCL) must be satised, i.e.,

IE = IC + IB (2.3.7)

2.3.2.1 Cuto (OFF)

In the cuto (OFF) mode, both PN junctions (BE and BC) of the BJT are reverse-biased. If
we assume simplied diode model for the PN junctions in the Ebers-Moll model, both ID,BE
and ID,BC are zero. Consequently,

IE(OF F ) = 0 (2.3.8)

IC(OF F ) = 0 and IB(OF F ) = 0 (2.3.9)

2.3.2.2 Forward Active (FA)

In the forward active (FA) mode, the base-emitter PN junction (BE) is forward biased and
the base-collector PN junction is reverse biased. In the Ebers-Moll model, ID,BC becomes zero.
Consequently,

VBE(F A) = 0.7 V (2.3.10)

IC(F A) = βF IB(F A) or IC(F A) = αF IE(F A) (2.3.11)

where βF is the common-emitter current amplication factor given by

αF
βF = (2.3.12)
1 − αF

Similarly, αF can also be expressed in terms of βF as

βF
αF = (2.3.13)
βF + 1

152
2.3.2.3 Reverse Active (RA)
In the reverse active (RA) mode, the base-emitter PN junction (BE) is reverse biased and
the base-collector PN junction is forward biased. In the Ebers-Moll model, ID,BE becomes zero.
Consequently,

VBC(RA) = 0.7 V (2.3.14)

−IC(RA) = (βR + 1) IB(RA) (IC(RA) < 0) (2.3.15)

or
IE(RA) = αR IC(RA) = −βR IB(RA) (IE(RA) < 0) (2.3.16)

where βR is the reverse active current amplication factor (typically 0.1 ≤ βR ≤ 2.0) given by

αR
βR = (2.3.17)
1 − αR

Similarly, αR can also be expressed in terms of βR as

βR
αR = (2.3.18)
βR + 1

Note that, negative values for currents mean that currents ow in the reverse directions than
the directions shown in Figure 2.3.3. In other words, negative IE and IC mean that the current
is owing into the emitter and out of the collector for an NPN transistor, and into the collector
and out of the emitter for a PNP transistor.

2.3.2.4 Saturation (SAT)

In the saturation (SAT) mode, both PN junctions (BE and BC) are forward biased. Normally, we
only consider the case called forward saturation where base-emitter junction has a stronger bias
(i.e., VBE ≥ VBC for NPN transistors). The opposite case (VBC > VBE for NPN transistors) is called
reverse saturation and rarely occurs in digital circuits.
Forward Saturation (FSAT): In this mode, base current is large and collector and emitter
IC < βF IB . Note that, in this mode IC and IE are positive.
currents are saturated such that

IC(F SAT ) < βF IB(F SAT ) (2.3.19)

VBE(F SAT ) = 0.8 V (2.3.20)

VBC(F SAT ) = 0.6 V (2.3.21)

VCE(F SAT ) = 0.2 V (2.3.22)

A saturation parameter σ is dened to indicate the relationship between IC and IB as

IC
σ= (2.3.23)
βF IB

153
 where σ ≤ 1. Note that σ is not constant, it changes according to the operating point, and
σ=1 denotes forward active operation and/or edge of saturation operation. If it is not given,
you may assume σmax = 1.

Reverse Saturation (RSAT): In this mode, base-collector junction has a stronger bias, i.e.,
VBC > VBE for NPN transistors, and collector and emitter currents are saturated such that
−IE < βR IB . Note that, in this mode IC and IE are negative.
−IE(RSAT ) < βR IB(RSAT ) (2.3.24)

−IC(RSAT ) < (βR + 1) IB(RSAT ) (2.3.25)

VCE(RSAT ) < 0 (for NPN transistors) (2.3.26)

In this course, we are going to refer forward saturation (FSAT) mode as the only saturation (SAT)
mode, i.e.,

SAT = F SAT. (2.3.27)

In all operation modes (FSAT, RSAT etc.) the following must hold:

1. IC and IE always have the same sign, i.e., always in the same direction,

2. Base current is always nonnegative, i.e., IB ≥ 0,

3. KCL is satised, i.e., IE = IC + IB ,

4. KVL is satised, i.e., VCE = VBE − VBC .

154
2.3.2.5 Simplied NPN BJT Model
We can show the simplied models for the four modesnamely cuto (OFF), forward active (FA),
reverse active (RA) and saturation (SAT)of operation of NPN transistors in Figure 2.3.5 below.

(a) OFF (b) FA

(c) RA (d) SAT

Figure 2.3.5: Reduced NPN BJT models for the four modes of operation: (a) Cuto (OFF), (b)
Forward Active (FA), (b) Reverse Active (RA), (d) Saturation (SAT).

We can summarize the simplied NPN BJT model with its state and circuit behaviour with
Table 2.4 below.

155
 Table 2.4: Simplied NPN BJT models for the all modes of operation

Simplied NPN BJT Model

State Circuit Behaviour Test Condition
IC = 0, VBE < VBE(F A) ,
Cuto (OFF)
IE = 0, IB = 0 VBC < VBC(RA)
VBE = VBE(F A) , VBC < VBC(RA) ,
Forward Active (FA)
IC = βF IB VCE > VCE(F SAT ) > 0
VBC = VBC(RA) , VBE < VBE(F A) ,
Reverse Active (RA)
IC = −(βR + 1)IB VCE < VCE(RSAT ) < 0
VCE = VCE(F SAT ) , IC < βF IB ,
Forward Saturation (FSAT)
VBE = VBE(F SAT ) IC > 0, IE > 0,
[ Saturation (SAT) ]
VBC = VBC(F SAT ) VCE > 0, IB > 0.
VCE = VCE(RSAT ) , −IC < (βR + 1)IB ,
Reverse Saturation (RSAT) VBE = VBE(RSAT ) IC < 0, IE < 0,
VBC = VBC(RSAT ) VCE < 0, IB > 0.

156
2.3.2.6 IV Characteristics

Figure 2.3.6: Output IV characteristics (IC vs. VCE ) of a common-emitter NPN BJT transistor with
IB as a parameter.

Figure 2.3.6 above shows a set of IC versus VCE characteristics for changes in IB (of amount
∆) as predicted by the Ebers-Moll model. For equal increments in IB , the curves in the active
regions are approximately evenly spaced, although the curves in the reverse active region are
much closer than those in the forward active region.

Example 2.4: For the circuit in Figure 2.3.7 below, determine the state of the transistor and
nd currents IB , IC and IE , given βF = 65.

Figure 2.3.7: A simple circuit for unknown BJT state example.

157
Example 2.5: For the circuit in Figure 2.3.8 below, determine the voltages at the base and
emitter of each BJT.

Figure 2.3.8: A digital sub-circuit for known BJT states example.

Example 2.6: For the circuit in Figure 2.3.9 below, determine I and VB . Assume the BJT
base current is negligible.

Figure 2.3.9: A saturated BJT example.

158
2.3.3 BJT Sub-Circuits
In order to provide a preview to succeeding chapters, this subsection introduces sub-circuits
common to all TTL families summarized by the NAND block diagram in Figure 2.3.10 below.

Figure 2.3.10: TTL family NAND super-circuitry block diagram.

2.3.3.1 Input Section

For this NAND diagram, input section consists of ANDing of all inputs either with a parallel
diode conguration or with a multi-emitter BJT.

2.3.3.2 Drive Splitter

Depending on the result of ANDing, the drive splitter turns on one of the two output sections,
namely output low and output high driver sections. A typical drive splitter is a BJT acting as a
switch, when it is cuto mode it activate the output-high driver and when it is in saturation mode
it activates the output-low driver. Driver splitter section also provides an inversion operation.

2.3.3.3 Output-High Pull-Up Driver

As the output goes low-to-high, current is required to charge the equivalent input-capacitance of
the load gates. Output-high pull-up driver provides the current for this charging. Some example
pull-up driver sub-circuits are shown in Figure 2.3.11 below.

Figure 2.3.11: Pull-up driver sub-circuits: (a) Passive pull-up, (b) Active pull-up, (c) Darlington pair
active pull-up.

159
 A simple voltage driven resistor, also known as passive pull-up, would serve the purpose as
shown in Figure 2.3.11(a) above.

An emitter-follower shown in Figure 2.3.11(b) above is an active solution which provides a

higher output current and hence provides faster switching time for the load gates. For even
more sourcing current, a Darlington pair can be used as shown in Figure 2.3.11(c) above.

Active pull-up circuitry also provides greater fan-out.

2.3.3.4 Output-Low Pull-Down Driver

There are two purposes of output-low pull-down circuits: one is to discharge the capacitive load
by providing a large sinking current, and another is to provide larger fan-out by sinking currents
IIL from all the load gates as shown in Figure 2.3.12 below.

Figure 2.3.12: Fan-out current sinking for output-low pull-down driver.

Some example pull-down driver sub-circuits are shown in Figure 2.3.13 below.

Figure 2.3.13: Pull-down driver sub-circuits: (a) Passive pull-down, (b) Active pull-down.

A simple resistor connected to a negative power supply (or ground), also known as passive
pull-down, would serve the purpose as shown in Figure 2.3.13(a) above.
A BJT, as shown in Figure 2.3.13(b) above, will server as an active pull-down in saturation
mode.

Another advantage of active pull-down or pull-up circuits is that they can be activated and/or
deactivated, apart from increasing fan-out.

2.3.3.5 Discharge Paths

In order to turn o a saturated BJT, all of the stored charges in the base region must be removed.
A path must therefore be available for base discharge. Some example discharge sub-circuits are
shown in Figure 2.3.14 below.

160
 Figure 2.3.14: Discharge (or stored charge removal) sub-circuits: (a) Passive, (b) Active.

Figure 2.3.14(a) above displays a circuit with an additional resistor RD that provides passive
charge removal.

Figure 2.3.14(b) above shows an active conguration for stored charge removal, which provides
a much faster discharge (i.e., higher discharge current) than RD itself.

2.3.3.6 Base Driving Circuitry

On the other hand, the turn-on time of a BJT is dependent on the time required to charge
the base of the BJT. Active base driving current is often supplied to BJTs to ensure a shorter
turn-on time.

An emitter-follower BJT conguration, as shown in Figure 2.3.15 below where QS drives base
driving current to QO , usually supplies this driving current.

Figure 2.3.15: Active base driving circuitry.

161
2.3.3.7 Power Dissipation of BJT Logic Circuits

Figure 2.3.16: .

When BJT logic circuits have a single power supply, as shown in Figure 2.3.16 above, the power
dissipation for a particular gate in a particular state is taken as the power supplied given by

PCC = ICC VCC (2.3.28)

where ICC is the current drawn from VCC and is obtained by summing all the currents leaving
the supply voltage source.

Figure 2.3.17: Currents leaving the power supply.

For example, for Figure 2.3.17 above, the current supplied by VCC is

ICC = IRB + IRC + IRCP . (2.3.29)

Consequently, the average power dissipated in a logic circuit with two output states (output-low
and output-high) is dened as

ICC(OL) + ICC(OH)
PCC(avg) = VCC (2.3.30)
2

Example 2.7: For the circuit in Figure 2.3.18 below, calculate the average power dissipation
for this gate, ifIRB(OH) = 1.55 mA, IRC(OH) = 24.7 µA, IRCP (OH) = 1.21 mA, IRB(OL) = 1.14 mA,
IRC(OL) = 4.48 mA and IRCP (OL) = 104 µA.

162
Figure 2.3.18: BJT logic gate for a power dissipation example.

163
2.4 Resistor-Transistor Logic (RTL)
2.4.1 Basic RTL Inverter
Resistor-Transistor Logic (RTL) which is introduced in 1962, is constructed from resistors and
BJTs as shown in Figure 2.4.1(a) below.

(a)
(b)

Figure 2.4.1: Basic RTL inverter: (a) Circuit, (b) Voltage transfer characteristics.

A basic RTL inverter and its VTC are shown in Figure 2.4.1(a) and Figure 2.4.1(b) above,
respectively.

Here, QO is in cuto (OFF) state when the input voltage is zero, i.e., VIN = 0, consequently
output is HIGH as VOU T = VCC (because IC = 0).

When the input voltage is enough, i.e., VIN = VBE(F A) , to turn on QO into the forward active
(FA) mode, then current IC will start to ow.

Hence, VOU T starts to drop with increasing VIN as VOU T = VCC − IC RC , IC = βF IB and
V −V
IB = IN RBE,O(F
B
A)
.

If we increase VIN further, at some point (i.e., when VIN = VIH ) QO goes into saturation.
Consequently, output becomes LOW and remains constant at VOU T = VCE(SAT ) .

We can summarize the state of the BJT transistor QO for output-high and output-low states as
indicated in Table 2.5 below.

Table 2.5: State of active elements for output-high and output-low states in a basic RTL inverter.

Element VOH VOL

QO Cuto (OFF) Saturated (SAT)

164
 Thus,

VOH = VCC (2.4.1)

VOL = VCE(SAT ) (2.4.2)

VIL = VBE(F A) (2.4.3)

VIH = IB(EOS) RB + VBE(EOS) (2.4.4)

IC(EOS)
= RB + VBE(EOS) (2.4.5)
βF
VCC − VCE(EOS)
= RB + VBE(EOS) (2.4.6)
βF RC

where EOS is edge of saturation, and hence VBE(EOS) = VBE(SAT ) and VCE(EOS) = VCE(SAT ) .

2.4.2 Basic RTL NOR and NAND Gates

Figure 2.4.2: Basic RTL NOR gate.

Figure 2.4.2 above shows a basic RTL NOR gate.

165
 Figure 2.4.3: Basic RTL NAND gate.

Figure 2.4.3 above shows a basic RTL NAND gate.

Example 2.8: For the basic RTL NAND gate in Figure 2.4.3 above, determine the maximum
fan-in if all stack BJTs have VCE(SAT ) = 0.17 V and all load gates have VBE(F A) = 0.7 V.

2.4.3 Basic RTL Fan-Out

When a basic RTL inverter is in output-low state, any load gate would be in cuto mode and
draw no input current.

Thus, maximum fan-out will be determined by the output-high state as shown in Figure 2.4.4
below.

166
 Figure 2.4.4: RTL Inverter in output high state with n identical load gates.

Output voltage is given by VOH = VCC − IOH RC where IOH = IRC and VOU T = VOH . So, VOH
is not constant and decreases with each added load gates, as the output current IOH increases
by each added load gate.

0
Thus, output current IOH which is the sum of the identical input currents IIH of N load gates,
is given by
VCC − VOH 0
IOH = = N IIH (2.4.7)
RC
0
where IIH is given by
0
0
VOH − VBE(SAT )
IIH = 0
. (2.4.8)
RB

Then, number of load gates, i.e., fan-out, (dropping the prime signs) is given by

VCC − VOH RB
N= (2.4.9)
VOH − VBE(SAT ) RC

Consequently, maximum fan-out is given by

VCC − VOH(min) RB
 
Nmax = (2.4.10)
VOH(min) − VBE(SAT ) RC

167
 As VOH(min) = VIH ,
 
VCC − VIH RB
Nmax = (2.4.11)
VIH − VBE(SAT ) RC
Example 2.9: Determine the maximum fan-out for a basic RTL inverter with VCC = 5 V,
RB = 10 kΩ, RC = 1 kΩ, βF = 25, VBE(SAT ) = 0.8 V and VCE(SAT ) = 0.2 V.

2.4.4 Basic RTL Power Dissipation

As VOL = VCE(SAT ) all load gates will be in cuto mode. So, output-low current supplied is
independent of load gates and given by

VCC − VCE,O(SAT )
ICC(OL) = (2.4.12)
RC
However, output-high current supplied depends on the number of load gates connected and
given by
0
VCC − VBE(SAT )
ICC(OH) = (2.4.13)
RC + R0 B/N
If there is no load, ICC(OH) = 0.
Consequently, average power dissipation is given by
ICC(OL) + ICC(OH)
PCC(avg) = VCC (2.4.14)
2
Example 2.10: Consider a basic RTL inverter with VCC = 5 V, RB = 10 kΩ, RC = 1 kΩ,
βF = 25, VBE(SAT ) = 0.8 V and VCE(SAT ) = 0.2 V. Find the average power dissipated

a) no load

b) a fan-out of 1.

2.4.5 Basic RTL Non-Inverter

(a)
(b)

Figure 2.4.5: Basic RTL non-inverter: (a) Circuit, (b) Voltage transfer characteristics.

168
For the basic RTL non-inverter shown in Figure 2.4.5 above

VOH = VCC − VCE(SAT ) (2.4.15)

VOL = 0V (2.4.16)

VIL = VBE(F A) (2.4.17)

VIH = IB(EOS) RB + VBC(EOS) + VCC (2.4.18)

IE(EOS)
= RB + VBC(EOS) + VCC (2.4.19)
βF + 1
VCC − VCE(EOS) RB
= + VBC(EOS) + VCC (2.4.20)
βF + 1 RE

where EOS is edge of saturation, and hence VBC(EOS) = VBC(SAT ) and VCE(EOS) = VCE(SAT ) .

Figure 2.4.6: Basic RTL OR gate.

Figure 2.4.6 above shows a basic RTL OR gate.

169
 Figure 2.4.7: Basic RTL NAND gate.

Figure 2.4.7 above shows a basic RTL AND gate.

2.4.6 RTL with Active Pull-Up

Figure 2.4.8: RTL inverter with active pull-up.

A method to increase the fan-out of RTL gates is to have an active pull-up conguration as shown
in Figure 2.4.8 above, where the purpose of each element in the circuit is listed in Table 2.6 below.

170
 Table 2.6: Purpose of each element for an RTL inverter with active pull-up

Element Purpose
RBS ,RBO Matched input resistors

QS Drive splitter and pull-down of QP

RC Along with QS provides logic-inversion to output-high driver

RBP Limits base current to QP

QO Output inverting BJT and active pull-down for output-low driver

QP Provides active pull-up for output-high driver

RCP Part of active pull-up

The states of active elements are given in Table 2.7 below.

Table 2.7: State of active elements for output-high and output-low states in an RTL inverter with

active pull-up.

Element VOH VOL

QO Cuto (OFF) Saturated (SAT)

QS Cuto (OFF) Saturated (SAT)

QP Saturated (SAT) (for fan-out ≥ 1) Cuto (OFF)

Edge of conduction (EOC) (for no load)

2.4.7 RTL with Active Pull-Up Fan-Out

Maximum fan-out will be determined by the output-high state.
Output current IOH = IE,P (SAT ) = IC,P (SAT ) + IB,P (SAT ) which is the sum of the identical input
0
currents IIH of N load gates, is given by

VCC − VCE,P (SAT ) − VOH VCC − VBE,P (SAT ) − VOH 0

IOH = + = N IIH (2.4.21)
RCP RC + RBP
0
where IIH is

0
0
VOH − VBE(SAT )
IIH = 0
. (2.4.22)
RB /2

Then, number of load gates, i.e., fan-out, (dropping the prime signs) is given by

171
 VCC − VCE(SAT ) − VOH RB VCC − VBE(SAT ) − VOH RB
N= + (2.4.23)
VOH − VBE(SAT ) 2RCP VOH − VBE(SAT ) 2 (RC + RBP )

As VOH(min) = VIH , maximum fan-out is given by

VCC − VCE(SAT ) − VIH RB VCC − VBE(SAT ) − VIH

 
RB
Nmax = + (2.4.24)
VIH − VBE(SAT ) 2RCP VIH − VBE(SAT ) 2 (RC + RBP )

If we ignore IB,P (SAT ) (i.e., (RC + RBP )  RCP ), maximum fan-out simplies to

VCC − VCE(SAT ) − VIH RB

 
Nmax ≈ (2.4.25)
VIH − VBE(SAT ) 2RCP

Example 2.11: Compare the maximum fan-out for the RTL inverter with active pull-up
with that of basic RTL inverter where VCC = 5 V, RBP = RBS = RBO = 10 kΩ, RC = 1 kΩ,
RCP = 100 Ω, VBE(SAT ) = 0.8 V, VCE(SAT ) = 0.2 V and βF = 25.

172
2.5 Diode-Transistor Logic (DTL)
2.5.1 Basic DTL Inverter
Diode-Transistor Logic (DTL) which is introduced in 1964 in order to overcome the low fan-out
of RTL, is constructed from diodes and BJTs as shown in Figure 2.5.1(a) below.

(a)
(b)

Figure 2.5.1: Basic DTL inverter: (a) Circuit, (b) Voltage transfer characteristics.

A basic DTL inverter and its VTC are shown in Figure 2.5.1(a) and Figure 2.5.1(b) above,
respectively.

When the input is low, e.g., VIN = 0 V, input diode DI is forward biased so the voltage Vx
between the diodes will be Vx = VIN + VD,I(ON ) and thus as VBE,O = Vx − VD,L(ON ) = VIN ,
output transistor QO will be in cuto mode. Consequently, output is HIGH as VOU T = VCC
(because IC = 0)

Vx = VIN + VD,I(ON ) (while VIN < VBE(SAT ) ) (2.5.1)

VBE,O = Vx − VD,L(ON ) (2.5.2)

VBE,O = VIN (2.5.3)

When the input voltage is high enough, i.e., VIN = VBE(F A) , to turn on QO into the forward
active (FA) mode, then current IC will start to ow.

Hence, VOU T starts to drop with increasing VIN as VOU T = VCC − IC RC .

If we increase VIN further, at some point (i.e., when VIN = VBE(SAT ) ), QO goes into saturation
and DI starts to turn o. As a result, VOU T becomes LOW and remains constant at VOU T =
VCE,O(SAT ) .

We can summarize the state of the active elements for output-high and output-low states as
indicated in Table 2.8 below.

173
Table 2.8: State of active elements for output-high and output-low states in a basic DTL inverter.

Element VOH VOL

QO Cuto (OFF) Saturated (SAT)

DL Edge of Conduction (EOC) Conducting (ON)

DI Conducting (ON) Cuto (OFF)

Thus,

VOH = VCC (2.5.4)

VOL = VCE(SAT ) (2.5.5)

VIL = VBE(F A) (2.5.6)

VIH = VBE(SAT ) (2.5.7)

2.5.2 Basic DTL NAND Gate

NAND function is inherently provided by the DTL logic family by adding diodes in parallel
at the input pointing outward (i.e., towards the input) as shown in Figure 2.5.2 below for a
two-input basic DTL NAND gate.

Figure 2.5.2: Basic DTL NAND gate.

Example 2.12: Consider the DTL NAND gate in Figure 2.5.2 above, and determine

a) Truth table for VIN A , VIN B and VOU T (using LOW-HIGH states),

b) States of DIA , DIB and QO when VIN A = 0.4 V and VIN B = 0.7 V,
c) States of DIA , DIB and QO when VIN A = 0.3 V and VIN B = 0.4 V,
d) States of DIA , DIB and QO when VIN A = 0.53 V and VIN B = 0.55 V.

174
2.5.3 Diode Modied DTL

(a) (b)

Figure 2.5.3: Modied DTL inverter with additional level-shifting diode and discharge path: (a)
Circuit, (b) Voltage transfer.

As shown in Figure 2.5.3(a) above, basic DTL inverter can be improved by

◦ by an additional diode DL2 to improve noise-margin-low VN M L .

◦ by an additional discharge path (consisting of RD and −VEE ) to the base of QO to improve
the switching time from saturation to cuto (i.e., to increase the low-to-high switching
speed).

2.5.4 Transistor Modied DTL

Figure 2.5.4: Transistor modied DTL inverter.

The fan-out of the modied DTL in Figure 2.5.3(a) can be further increased by replacing DL2
with a self-biased BJT QL (prevented from going into saturation mode by ensuring always

175
 VBC < 0) as shown in Figure 2.5.4 above, where the purpose of each element in the circuit is
listed in Table 2.9 below.

Table 2.9: Purpose of each element for a transistor-modied DTL inverter

Element Purpose
DI Input diode, provides ANDing and limits IIH
ρRB Limits IIL
(1 − ρ)RB Self-biases QL and prevents QL from saturation

QL Level shifting to improve VN M L and provides base driving current QO

DL Level-shifting diode for shifting transition width

RD Provides discharge path for saturation stored charge removal from base of QO
QO Output inverting BJT and active pull-down for output-low driver

RC Part of passive pull-up

The states of active elements in a transistor modied DTL inverter are given in Table 2.10 below.

Table 2.10: State of active elements for output-high and output-low states in a transistor modied

DTL inverter.

Element VOH VOL

QO Cuto (OFF) Saturated (SAT)

DL Cuto (OFF) Conducting (ON)

QL Cuto (OFF) Forward Active (FA)

DI Conducting (ON) Cuto (OFF)

Thus,

VOH = VCC (2.5.8)

VOL = VCE,O(SAT ) (2.5.9)

VIL = VBE,L(F A) + VBE,O(F A) (2.5.10)

VIH = VBE,L(F A) + VBE,O(SAT ) (2.5.11)

2.5.5 DTL NAND Gate

NAND function is inherently provided by the DTL logic family by adding diodes in parallel at
the input pointing outward as shown in Figure 2.5.5 below.

176
 Figure 2.5.5: DTL NAND gate.

2.5.6 DTL Fan-Out

Figure 2.5.6: DTL NAND gate in output-low state driving N identical load gates.

Maximum fan-out will be determined by the output-low state, as when output is high input
0 0
diode DI is cuto (i.e., IIH = 0).

177
 From Path 2 and Path 1,

IOL = IC,O(SAT ) − IRC(OL) (2.5.12)

VCC − VCE,O(SAT )
IRC(OL) = (2.5.13)
RC
IC,O(SAT ) = σβF IB,O(SAT ) (2.5.14)

Continuing,

IB,O(SAT ) = IE,L(F A) − IRD(OL) (2.5.15)

VBE,O(SAT )
IRD(OL) = (2.5.16)
RD
VCC − VBE,L(F A) − VD,L(ON ) − VBE,O(SAT )
IE,L(F A) = (2.5.17)
ρRB + (1 − ρ) RB / (βF + 1)
VCC − VBE,L(F A) − VD,L(ON ) − VBE,O(SAT )
≈ (2.5.18)
ρRB

From Path 1,
0 VCC − VD,I(ON ) − VCE,O(SAT )
IIL = (2.5.19)
RB
Thus, the maximum fan-out is given by
IC,O(SAT )(max) − IRC(OL)
   
IOL(max)
Nmax = 0
= 0
(2.5.20)
IIL IIL
σmax βF IB,O(SAT ) − IRC(OL)
 
= 0
(2.5.21)
IIL

Example 2.13: For the DTL gate in Figure 2.5.4, determine the maximum fan-out for βF = 49
and σmax = 0.85.

2.5.6.1 DTL Power Dissipation

Example 2.14: Calculate the average power dissipation for Example 2.13 above?

178
2.6 Transistor-Transistor Logic (TTL)
2.6.1 Basic TTL Inverter
Transistor-Transistor Logic (TTL) which is introduced in 1965 in order to provide increased
fan-out, improved transient response and reduced chip area.

(a)

(b)

Figure 2.6.1: Basic TTL inverter: (a) Circuit, (b) Voltage transfer characteristics.

A basic TTL inverter and its VTC are shown in Figure 2.6.1(a) and Figure 2.6.1(b) above,
respectively.

Compare the TTL inverter in Figure 2.6.1(a) with the DTL inverter in Figure 2.5.1(a) in order
to see how diodes DI and DL are represented by the base-emitter and base-collector junctions
of the input transistor QI which replaced these two diodes.

When the input is low, e.g., VIN = 0 V, base-emitter junction of QI is forward biased, however
voltage at the base of QI is not enough to turn on both base-collector junction of QI and base-
emitter junction of QO , so QO is cuto. So, collector current of QI is zero, i.e., IC,I = 0. Thus,
QI is in saturation mode (as IC < βF IB ).
VBE,O = VIN + VCE,I(SAT ) (while VIN < VIH ) (2.6.1)

As QO is in cuto mode when VIN = 0 V, the output is HIGH as VOU T = VCC .

When the input voltage is high enough, i.e., VIN = VBE(F A) −VCE(SAT ) , QO goes into the forward
active (FA) mode and current IRC will start to ow. Then, VOU T starts to drop with increasing
VIN as VOU T = VCC − IRC RC .

If we increaseVIN further, at some point (i.e., when VIN = VBE(SAT ) − VCE(SAT ) ), QO goes into
saturation and QI goes into reverse-active mode. As a result, VOU T becomes LOW and remains
constant at VOU T = VCE,O(SAT ) .

179
 We can summarize the state of the active elements for output-high and output-low states as
indicated in Table 2.11 below.

Table 2.11: State of active elements for output-high and output-low states in a basic TTL inverter.

Element VOH VOL

QO Cuto (OFF) Saturated (SAT)

QI Saturated (SAT) Reverse Active (RA)

Thus,

VOH = VCC (2.6.2)

VOL = VCE,O(SAT ) (2.6.3)

VIL = VBE,O(F A) − VCE,I(SAT ) (2.6.4)

VIH = VBE,O(SAT ) − VCE,I(SAT ) (2.6.5)

2.6.2 Basic TTL NAND Gate

NAND function is inherently provided by the TTL logic family by using a multiple-emitter BJT
(ensuring a much-less chip area) as shown in Figure 2.6.2 below for a three-input basic TTL
NAND gate.

Figure 2.6.2: Basic TTL NAND gate.

180
2.6.3 Standard TTL NAND Gate

Figure 2.6.3: Standard TTL 5400/7400 series NAND gate with totem-pole output.

Basic TTL inverter can be improved by adding a totem-pole output (stacking of two BJTs,
a resistor and diode in the output branch) to provide active pull-up and pull-down sections, a
drive-splitter transistor QS , a discharge resistor RD and clamping diodes at the inputs as shown
in Figure 2.6.3 above. The purpose of each element in the circuit is listed in Table 2.12 below.

181
Table 2.12: Purpose of each element for a standard TTL NAND gate with totem-pole output

Element Purpose
QI Multi-emitter input BJT, level-shifting of transition width and pull-down of QS
RB Limits IIL
Drive splitter, provides base driving current QO , level-shifting of transition width
QS
and pull-down of QP
RC Along with QS provides logic inversion to output-high driver

QO Output inverting BJT and active pull-down for output-low driver

Diode level shifting to output-high output and ensuring output high driver is o
DL
in the output-low state

RD Provides discharge path for saturation stored charge removal from base of QO
QP Provides active pull-up for output-high driver

RCP Part of active pull-up and limits current-spikes during high-to-low transitions

DCA , DCB Input clamping diodes to limit the negative voltage swing of the inputs

Figure 2.6.4: Voltage transfer characteristics of a standard TTL inverter given in Figure 2.6.3.

When the input is low, e.g., VIN = 0 V, base-emitter junction of QI is forward biased, however
voltage at the base of QI is not enough to turn on both base-collector junction of QI and base-

182
 emitter junction of QS , so QS and QO are cuto. So, collector current of QI is zero and QI is
in saturation mode.
When VIN = 0 V, QS and QO are in cuto mode and QP is in edge-of-conduction (EOC) mode
(i.e., no current ows as there is no-load). So, as IRC(OH) = IB,P (EOC) = 0, the output is HIGH
and given as

VOU T = VCC − IRC(OH) RC − VBE,P (EOC) − VD,L(EOC) (2.6.6)

= VCC − VBE,P (F A) − VD,L(ON ) (2.6.7)

When the input voltage is high enough, i.e., VIN = VBE,S(F A) − VCE,I(SAT ) , QS goes into the
forward active (FA) mode and current IRC will start to ow. Then, VOU T starts to drop with
increasing VIN as VOU T = VCC − IRC RC − VBE,P (EOC) − VD,L(EOC) .

If we increase VIN further, then at some point (i.e., when VIN = VBE,O(F A) + VBE,S(F A) − VCE,I(SAT ) ),
QO turns into forward active mode. As a result, VOU T decreases more rapidly asIC,O also starts
to ow and more current starts to ow from RC . This point is called the break point. The
input and output voltages at the break point are labelled as VIB and VOB , respectively.

If VIN VIN = VBE,O(SAT ) + VBE,S(SAT ) − VCE,I(SAT ) ),

is kept increasing, then at some point (i.e., when
both QS and QO go into the saturation mode, QP goes into cuto mode and QI goes into
the reverse-active mode. As a result, VOU T becomes LOW and remains constant at VOU T =
VCE,O(SAT ) .

The states of active elements in a standard TTL inverter are given in Table 2.13 below.

Table 2.13: State of active elements for output-high and output-low states in a standard TTL inverter.

Element VOH VOB VOL

QO Cuto (OFF) Edge of conduction (EOC) Saturated (SAT)

QS Cuto (OFF) Forward active (FA) Saturated (SAT)

QI Saturated (SAT) Saturated (SAT) Reverse active (RA)

QP Edge of conduction (EOC) Edge of conduction (EOC) Cuto (OFF)

DL Edge of conduction (EOC) Edge of conduction (EOC) Cuto (OFF)

Thus,

183
 VOH = VCC − VBE,P (F A) − VD,L(ON ) (2.6.8)

VOB = VCC − IC,S(F A) RC − VBE,P (F A) − VD,L(ON ) (2.6.9)

VBE,O(F A)
= VCC − RC − VBE,P (F A) − VD,L(ON ) (2.6.10)
RD
VOL = VCE,O(SAT ) (2.6.11)

VIL = VBE,S(F A) − VCE,I(SAT ) (2.6.12)

VIB = VBE,O(F A) + VBE,S(F A) − VCE,I(SAT ) (2.6.13)

VIH = VBE,O(SAT ) + VBE,S(SAT ) − VCE,I(SAT ) (2.6.14)

Example 2.15: For the TTL gate in Figure 2.6.3, determine the VTC critical points VOH , VOL ,
VIL , VIH , VIB and VOB for βF = 100 and σmax = 0.85.

2.6.4 TTL Fan-Out

Figure 2.6.5: TTL NAND gate in output-low state driving N identical load gates.

Maximum fan-out will be determined by the output-low state, as when output is high input
0 0
transistor QI is in reverse active mode (i.e., IIH = 0).

184
 From Path 1,

IOL = IC,O(SAT ) − ID,L(EOC) = IC,O(SAT ) (2.6.15)

IC,O(SAT ) = σβF IB,O(SAT ) (2.6.16)

Continuing

IB,O(SAT ) = IE,S(SAT ) − IRD(OL) (2.6.17)

VBE,O(SAT )
IRD(OL) = (2.6.18)
RD
IE,S(SAT ) = IC,S(SAT ) + IB,S(SAT ) (2.6.19)

VCC − VCE,S(SAT ) − VBE,O(SAT )

IC,S(SAT ) = (from Path 2) (2.6.20)
RC

From Path 3,

IB,S(SAT ) = IC,I(RA) (2.6.21)

= (1 + βR )IB,I(RA) (2.6.22)

VCC − VBC,I(RA) − VBE,S(SAT ) − VBE,O(SAT )

IB,I(RA) = (2.6.23)
RB

From Path 1,
0 VCC − VBE,I(SAT ) − VCE,O(SAT )
IIL = (2.6.24)
RB

Thus, the maximum fan-out is given by

   
IOL(max) IC,O(SAT )(max)
Nmax = 0
= (2.6.25)
IIL I0
  IL
σmax βF IB,O(SAT )
= 0
(2.6.26)
IIL

Example 2.16: For the TTL gate in Figure 2.6.3, determine the maximum fan-out for βF = 25,
βR = 0.1 and σmax = 0.85.

2.6.4.1 TTL Power Dissipation

Example 2.17: Calculate the average power dissipation for Example 2.16 above?

185
2.6.5 Open-Collector TTL

Figure 2.6.6: Open-collector TTL gate.

Open-collector TTL gates, one of which is shown in Figure 2.6.6 above, are often used in data
busses where multiple gate outputs must be ANDed.

◦ This can be accomplished by using a single pull-up resistor with open-collector TTL gates.

◦ This type of connection is referred to as wired-AND.

186
2.6.6 Low Power TTL (LTTL)

Figure 2.6.7: Low power TTL (LTTL) with increased resistances.

Power dissipation can be lowered by just increasing the resistance values as shown in Fig-
ure 2.6.7 above.

However, this results in:

◦ decreased fan-out,

◦ longer transient response times.

Example 2.18: Calculate the average power dissipation for LTTL in Figure 2.6.7 and compare
it with that of TTL which was calculated in Example 2.17.

187
2.6.7 High Speed TTL (HTTL)

Figure 2.6.8: 54H00/74H00 high-speed TTL (LTTL) with smaller resistances and Darlington pair
active pull-up driver.

Switching speed can be increased by just decreasing the resistance values as shown in Fig-
ure 2.6.8 above. An additional Darlington pair is also used to improve the low-to-high switching
speed, together with REP resistor which provides a discharge path for QP 2 in order to improve
the high-to-low switching speed.

However, this results in

◦ increased power dissipation.

188
2.7 Other TTL Gates
In this section, we are going to investigate the following TTL gates

• AND gates

• NOR gates

• OR gates

• AND-OR-INVERT (AOI) gates

• XOR gates

• Schmitt Trigger Inverters and NAND gates

• Tri-State buers

2.7.1 AND Gate

NAND gate will become an AND date, if the output drivers are enabled in the inverse fashion.
This is accomplished by using an inverting driver splitter as shown in the block diagram of
Figure 2.7.1 below.

Figure 2.7.1: Block diagram of a TTL AND gate.

This second level inversion is accomplished by QS2 , QSD , DS , RSD and RCS which are enclosed
in the shaded block in Figure 2.7.2 below. Circuit symbol and VTC for a TTL AND gate are
also displayed in Figure 2.7.3 and Figure 2.7.4, respectively.

189
 Figure 2.7.2: Circuit schematic of a standard 5408/7408 TTL AND gate.

Figure 2.7.3: Circuit symbol of a TTL AND gate.

Figure 2.7.4: Voltage transfer characteristics of a standard TTL AND gate given in Figure 2.7.2.

When the input is low, e.g., VIN = 0 V, QI is saturated, QS2 and QSD are cuto. Consequently,
QS and QO are saturated, and QP and DL are cuto. So, the output is LOW, i.e., VOL =
VCE,O(SAT ) .

190
 The output will start increase when QO goes from saturation mode to forward active mode.
Only QS2 being in forward active mode is not enough to decrease the voltage at the base of QS
below 1.6 V and change the state of QO . So, QSD needs to go into forward active mode as well.
Thus, the value of the input to make the output rise is equal to VIL = VBE,SD(F A) + VBE,S2(F A) −
VCE,I(SAT ) .

QS will turn o when the voltage at its base goes below 0.7 V and this will occur suddenly when
QSD and QS2 go into saturation. Thus, the value of the input which makes the output high is
given by VIH = VBE,SD(SAT ) + VBE,S2(SAT ) − VCE,I(SAT ) . Then, QI goes into reverse active mode
and the output stays high.

The states of active elements in a standard TTL noninverter are given in Table 2.14 below.

Table 2.14: State of active elements for output-high and output-low states in a standard TTL inverter.

Element VOL VOH

QO Saturated (SAT) Cuto (OFF)

QS Saturated (SAT) Cuto (OFF)

QP Cuto (OFF) Edge of conduction (EOC)

DL Cuto (OFF) Edge of conduction (EOC)

QSD Cuto (OFF) Saturated (SAT)

QS2 Cuto (OFF) Saturated (SAT)

DS Conducting (ON) Conducting (ON)

QI Saturated (SAT) Reverse active (RA)

A knee is not present in the VTC of the TTL AND gate in contrast to the VTC of the TTL
NAND gate, and the transition region is more abrupt. Thus,

VOL = VCE,O(SAT ) (2.7.1)

VOH = VCC − VBE,P (F A) − VD,L(ON ) (2.7.2)

VIL = VBE,SD(F A) + VBE,S2(F A) − VCE,I(SAT ) (2.7.3)

VIH = VBE,SD(SAT ) + VBE,S2(SAT ) − VCE,I(SAT ) (2.7.4)

2.7.2 NOR Gate

NOR function is obtained by using separate input sections QI , RB and QS for the inputs where
drive splitter transistors are connected in parallel (i.e., their collectors and emitters are connected
together) as shown in Figure 2.7.5(a) below. Circuit symbol for the NOR gate is also displayed
in Figure 2.7.5(b) below.

191
 (b)

(a)

Figure 2.7.5: Standard 5402/7402 TTL NOR gate: (a) Circuit schematic, (b) Circuit symbol.

Example 2.19: For the two input TTL NOR gate in Figure 2.7.5(a), determine the average
power dissipation and compare the result with that of a standard TTL inverter calculated in
Example 2.17.

NOTE: You need to consider all four possible input states.

2.7.3 OR Gate
OR function is obtained by using separate input sections and parallel drive splitter transistors
of the second lvel inversion circuitry as shown in Figure 2.7.6(a) below. Circuit symbol for the
OR gate is also displayed in Figure 2.7.6(b) below.

192
 (b)

(a)

Figure 2.7.6: Standard 5432/7432 TTL OR gate: (a) Circuit schematic, (b) Circuit symbol.

2.7.4 AND-OR-INVERT (AOI) Gates

TTL gates performing more complex logic functions can be designed using the following rules

1. ANDing of signals

◦ Multi-emitter input BJT sections

2. ORing of signals

◦ Multiple input sections (QI and RB )

◦ Multiple and parallel connected drive splitting BJTs (QS )

3. If non-inverting ORing is desired

◦ Additional logic inversion circuitry with parallel connected drive splitting BJTs

4. Totem-pole output branch

Example 2.20: Design a four-input AOI TTL gate which performs VOU T = VA VB + VC VD .

Solution:Circuit schematic and circuit symbol for the solution are shown in Figure 2.7.7 and
Figure 2.7.8 below.

193
 Figure 2.7.7: AOI TTL gate performing VOU T = VA VB + VC VD in Example 2.20.

Figure 2.7.8: Circuit symbol for VOU T = VA VB + VC VD in Example 2.20.

Example 2.21: Design a six-input AOI TTL gate which performs VOU T = VA VB + VC + VD VE VF .

Solution:Solution is given in Figure 2.7.9 below.

194
Figure 2.7.9: AOI TTL gate performing VOU T = VA VB + VC + VD VE VF in Example 2.21.

Example 2.22: Design a six-input AOI TTL gate which performs VOU T = VA VB + VC + VD VE VF .

Solution:Solution is given in Figure 2.7.10 below.

195
 Figure 2.7.10: AOI TTL gate performing VOU T = VA VB + VC + VD VE VF in Example 2.22.

2.7.5 XOR Gate

Figure 2.7.11: Circuit symbol for an XOR gate.

Circuit symbol and truth table for an XOR gate are given in Figure 2.7.11 above and Table 2.15
below, respectively.

196
 Table 2.15: Truth table for an XOR gate.

VIN A VIN B VOU T

LOW LOW LOW

LOW HIGH HIGH

HIGH LOW HIGH

HIGH HIGH LOW

As we notice, the output is LOW when the inputs are the same, and HIGH when the inputs are
dierent.

Also, the outputs will be the same, even when the inputs are inverted, i.e,

F =A⊕B =A⊕B (2.7.5)

We can form an XORing logic pair using two transistors: by connecting one input to the base
of the rst transistor and to the emitter of the second transistor, and connecting the other input
to the base of the second transistor and to the emitter of the rst transistor where the collectors
of the transistors are connected together, as shown in Figure 2.7.12 as QX1 and QX2

So, both transistors will be OFF when the inputs are the same. First transistor will be in
saturation if the rst input is HIGH and the second input is LOW, and similarly second transistor
will be in saturation if the rst input is LOW and the second input is HIGH. This is actually
the XNOR operation, so we need to add an inverter section to the common collector of the
transistors in order to obtain the XOR operation.

Also, in order to make sure the transistors will be in saturation when the inputs are dierent,
we invert the inputs rst to obtain xed voltage levels for the inputs of the XORing logic pair
which consists of QX1 and QX2 .

197
 Figure 2.7.12: Standard 5486/7486 TTL XOR gate.

2.7.6 Schmitt Trigger Inverters and NAND Gates

Consider a noisy signal, shown at the top of Figure 2.7.13(a) below, as an input to an inverter
gate. We need to produce a neat inverter output signal considering the input is LOW before t2 ,
HIGH between t2 and t3 , LOW between t5 and t8 and HIGH after t8 , as shown at the bottom
of Figure 2.7.13(a) below.

As we can see, a single threshold is not enough to determine the input voltage state. Two
thresholds are needed one for low-to-high transition and another one for high-to-low transition.

198
 (b)

(a)

Figure 2.7.13: Schmitt trigger inverter: (a) Noisy input and the corresponding inverting output voltage
waveforms, (b) VTC characteristics exhibiting hysteresis having dierent threshold levels VID and VIU
for high-to-low and low-to-high transitions, respectively.

As seen from Figure 2.7.13(b) above, VTC exhibits hysteresis, i.e., low-to-high path is not the
same as the high-to-low path of the input-output relationship.

2.7.6.1 Basic Emitter-Coupled Schmitt Trigger Noninverter

(b)
(a)

Figure 2.7.14: Basic emitter-coupled noninverting Schmitt Trigger: (a) Circuit, (b) VTC.

Hysteresis can be achieved by the basic emitter-coupled noninverting Schmitt Trigger circuit
shown in Figure 2.7.14(a) above.

Let us rst investigate, low-to-high path of the input. When input is LOW, e.g., VIN S = 0 V,
then QS1 is cuto and QS2 is in saturation. Thus, the output is LOW, i.e., VOU T S = VOLS =
VE + VCE,S2(SAT ) . So, IE,S2 = IB,S2 + IC,S2 , i.e.,

199
 VE VCC − VE − VBE,S2(SAT ) VCC − VE − VCE,S2(SAT )
= + (2.7.6)
RSE RCS1 RCS2

We nd VE as
VCC − VBE,S2(SAT ) VCC − VCE,S2(SAT )
 
VE = + Req (2.7.7)
RCS1 RCS2

where Req = RCS1 ||RCS2 ||RSE .

Thus, VOLS is given by

VCC − VBE,S2(SAT ) VCC − VCE,S2(SAT )

 
VOLS = + Req + VCE,S2(SAT ) (2.7.8)
RCS1 RCS2

As, we keep increasing the input, eventually QS1 will become forward active at an input voltage
VIN S = VIU S = VE + VBE,S1(F A) . Then, VE will increase and VOU T S will start to rise.

Thus, VIU S is given by

VCC − VBE,S2(SAT ) VCC − VCE,S2(SAT )

 
VIU S = + Req + VBE,S1(F A) (2.7.9)
RCS1 RCS2

Once the input is further increased, voltage at QS1 will go into saturation and QS2 will turn o.
Then, the output voltage will become HIGH at VOU T S = VOHS = VCC − IRCS2 RCS2 . But, as
there is no load IRCS2 = 0 and
VOHS = VCC (2.7.10)

[]Now we can investigate the high-to-low path of the input. In this case QS2 is cuto and QS1 is in
saturation. The output will fall when QS2 becomes forward active, i.e., when VBE,S2 = VBE(F A) .

As VE = VIN S − VBE,S1(SAT ) , VBE,S2 = VB,S2 − VE , VB,S2 = VCC − IC,S1 RCS1 and IC,S1 ≈ IE,S1 =
VE /RSE , we can obtain the input in terms of VBE,S2 as

VCC − VBE,S2
VIN S = + VBE,S1(SAT ) (2.7.11)
RCS1 /RSE + 1

As the output will start to drop when QS2 turns on, i.e., when VBE,S2 = VBE(F A) , then we can
nd VIDS as
VCC − VBE,S2(F A)
VIDS = + VBE,S1(SAT ) (2.7.12)
RCS1 /RSE + 1

Example 2.23: For the Schmitt Trigger noninverter circuit in Figure 2.7.14(a), determine the
VOHS , VOLS , VIU S and VIDS values where RCS1 = 4 kΩ, RCS2 = 2.5 kΩ, and RSE = 1 kΩ.

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 Solution: As Req = RCS1 ||RCS2 ||RSE = 606 Ω,

VOHS = 5 V (2.7.13)

VCC − VBE,S2(SAT ) VCC − VCE,S2(SAT )

 
VE,S2(SAT ) = + Req = 1.8 V (2.7.14)
RCS1 RCS2
VOLS = VE,S2(SAT ) + VCE,S2(SAT ) = 2 V (2.7.15)

VIU S = VE,S2(SAT ) + VBE,S1(F A) = 2.5 V (2.7.16)

VCC − VBE,S2(F A)
VIDS = + VBE,S1(SAT ) = 1.66 V (2.7.17)
RCS1 /RSE + 1

2.7.6.2 Schmitt Trigger NAND Gate

We can convert the basic emitter-coupled Schmitt Trigger noninverter in Figure 2.7.14(a) to
a TTL compatible Schmitt Trigger NAND gate by connecting and ANDing diode section at
the input and by adding a emitter-follower level shifter section with QL and DL followed by a
normal inverting driver splitter connected a totem-pole output section at the output, as shown
in Figure 2.7.15 below.

Figure 2.7.15: Standard 5424/7424 Schmitt Trigger NAND gate.

Circuit symbol for a Schmitt Trigger NAND gate is shown in Figure 2.7.16 below.

Figure 2.7.16: Circuit symbol for a Schmitt Trigger NAND gate.

An example VTC for a standard Schmitt Trigger NAND gate is shown in Figure 2.7.17 below.

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 Figure 2.7.17: An example VTC for a standard Schmitt Trigger NAND gate.

Example 2.24: For the Schmitt Trigger NAND circuit in Figure 2.7.15, determine the VOH ,
VOL , VIU and VID values where RCS1 = 4 kΩ, RCS2 = 2.5 kΩ, and RSE = 1 kΩ.
HINT: Use the results in Example 2.23.

Solution:
VOH = VCC − VBE,P (F A) − VD,L(ON ) = 3.6 V (2.7.18)

VOL = VCE,O(SAT ) = 0.2 V (2.7.19)

VID = VIU S − VD,I(ON ) = 1.8 V (2.7.20)

VIU = VIDS − VD,I(ON ) = 0.96 V (2.7.21)

2.7.7 Tri-State Buers

Figure 2.7.18: Circuit symbol for a low-enabled tri-state buer (or noninverter).

Circuit symbol and truth table for a low-enabled tri-state buer (or noninverter) are given in
Figure 2.7.18 above and Table 2.16 below, respectively.

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 Table 2.16: Truth table for a low-enabled tri-state buer.

VIN VEN VOU T

LOW LOW LOW

HIGH LOW HIGH

LOW HIGH HIGH IMPEDANCE (Z)

HIGH HIGH HIGH IMPEDANCE (Z)

High impedance Z-state nodes are oating, i.e., not connected. So, high impedance Z-state
nodes are not at ground, not at VCC and have no driving ability.

Figure 2.7.19: Circuit schematic for a low-enabled tri-state buer (or noninverter).

Enable-disable functionality is basically achieved by connecting a diode DS to the enable input

of QI which is also ANDed together with the actual input.

◦ When VEN is HIGH, DS is OFF. So, the circuit operates like a normal noninverter and
output is determined by the input VIN .
◦ When VEN is LOW, QS and QO are OFF due to AND operation, and DS is also ON. As
DS is ON, voltage at the base of QP VEN + VD,S(ON ) which is not high enough to
drops to
turn on QP 2 . So, both QO are QP 2 are OFF, and output VOU T is not connected to pull-up
or pull-down drivers regardless of the value of the input VIN . In other words, when VEN is
LOW, the circuit is disabled and the output is in high impedance state.

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 (a) (b)

Figure 2.7.20: Example usage of high-enabled tri-state buers: (a) Four-buers connected to a single
bus, (b)Case of TA is enabled, TB , TC and TD are disabled.

Figure 2.7.20(a) shows an example of four tri-state buers connected to a single bus. Fig-
ure 2.7.20(b) shows how to enable a single buer at a time using a 2:4 decoder, e.g., acting as a
4-to-1 multiplexer with two select inputs.

Tri-state buers are often used to drive multi-bit circuit busses as shown in Figure 2.7.21 below.

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Figure 2.7.21: 8-bit data bus driven by four 8-bit register outputs where one enable signal enables or
disable all 8-bit register outputs.

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2.8 NMOS and CMOS Gates

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