Fuzzy Logic PID controller based on FPGA for process control

Student: V. Tipsuwanpornm1 T. Runglimmawan . S. Intajag Supervisor: V. Krongratana4

V. Tipsuwanporn,3 S. Intajag and 4V. Krongratana Department of Instrumentation Engineering.
Faculty of Engineering, King Mongkut7s Institute of Technology Ladkrabang, Bangkok 10520.
Thailand (Tel: 66 - 2326 - 7347: Ext. 102; E - mail: ktvittayv(kmitl.ac.th)

T. Runghimnmawan Dept. of Electrical Engineering Faculty of Engineering,

,

Kasem Bundit University, Bangkok,Thailand.

E-mail thanrunh(a,,vahoo.com

Abstract
In this paper. a fuzzy proportional integral derivative (PID) controller, which is fabricated on a Field Programmable
Gate Array (FPGA). is proposed to conitrol an ilndustrial process. The fuzzy logic is provided to tune the PID parameters
by using a gain scheduhng method. The tuning scheme is represented by a fuzzy svsten. which consists of
fuzzification, rule inference and defuzzification. The fabricated FPGA chip, XC2S50-Stq-144. is embedded with the
fuzzy system. which the chip is called fuzzv-PID controller. The fuzzy-PID controller is contained several circuits, such
as multiplier, adder, subtraction and some of the otlher logic gate. The controller system uses two converter cards:
TDA8763AM/3 (10 bits, high speed) to convert from analog to digital signal, DAC08 (8 bits) to convert from digital to
analog. The maximum speed of the controller about 2.1 psec per action at 40.550 AIH.Z. is calculated from timing
summary. The fuzzy-PID controller based on FPGA is verified by using to control model of lev,el and temperature
process. From the experimental results of the level and temperature control. the fuzzy-PID controller lhas achieved and
shown the better performance than stanidard PID controller E50AK. which is automatic tuneable parameter system.

Keywords
FPGA, PID, Fuzzy- logic, Process control. Fuzzy-PID controller.

0-7803-8304-4/04/$20.00 @c(2004 IEEE 1495

1 INTRODUCTION be developed empirically in practice witlhout
comiphcated mathematics.
In recent years. there has been growing in using fuzzy
logic for industrial process control. In the proposed Fuzzy logic corresponds with ordinamy set theory [2].
scheme, the conventional PID parameters (Kp. Kd and KX) wliich is a binary logic operators AND, OR, NOT, and
are formulated with the fuzzv system and embedded on so on. The universe of discourse U is a collection of
FPGA cliip. XC2S50-5tq-14, wliich the fabricated cliip objects under consideration. The fuzzy subset A in U is
is verified by two industrial processes. level and characterized by a membership function pA which takes
temperature control. From the experiment. the fabricated the values in the interval [0,1]. witlh 0 representing no
chip las maximum execute time approximatelv 2.096 memberslhip and 1 representing full memberslip. In
vsec per action, which is better than the standard PID designinig a fuzzv systenm universe of discourse and
E5AK. memberslhip functions of inputs and outputs (linguistic
variables) are first detennined. To allow fuzzy
2 RELATED THEORIES approximate reasoning. the fuzzy inference meclanism
based on the generalized modus ponens (GMP) slhown
below is usually adopted:
2.1 PID controller
Promise 1: if input x is A then output v is B
Fundamental equation of a PID controller [1] is given as: Premiise 2: inlput x is A'
Consequence: output lis B'
L',,(t) = Kp[e(t) + Ife(t)dt +Td de() j (1) Where A. B. A' and B' are fuzzn sets. Premise 1 (the
"'if.. then" part) can be represented by fuzzy relation R,
which can be deriNed from different fuzzy implication
where To(t) denotes controler output at time t. Kp functions. The one based on the "mimn" implication
represents a controller gain, Ti is integral time (sec.), Td function requires the following computation:
is a derivative time (sec.) and e(t) is sy'stem error, which pR(u,V) = min(pA(ut), pB(i)): II e U. v e V.
is defined as:
Where /,(u,v) is the miemberslhip function of R. With a
e t) = sp (t) -pi, (t) (2) specific input, the fuzzy inference is completed tlrough
the fuzzy composition shJow below:
where st(t) and pli(tJ denote set point and process output. B' = A' o R
respectively. The fuzzy composition based on the mx-min operator
requires the flowing computation:
Eq. (1) is transformed to digital PID controller by
discrete differential equation as seen in Eq. (3). pB(i) = max min(uA(u). pR(u,i))
To obtain a crisp output from the fuzzy inference engine,
2ne,- e~v n a defuzzification algonrtlu is fonLulated. In our schenme.
iVa v KL(e -e,, )
+K re,+ (e,
' (3) center of gravity (COG) is used to defuzzifV as seen in
=

-
the following:
wlhere AT denotes the sampling period, FrY is controller 11i
Zo = v
l/Z (5)
output at the nth sampling instant and e, is error at the ;ith V

sampling instant.
wlhere , and zv are the weiglht (value) and center (in the
From Eq. (1) and (2), the digital PID is formulated as Eq. universe of discourse). respectively. The output of the
(4). fuzzxv inference engine is Z.v which is a crisp set.
IRo =1Ti'
0 0,
+(K +XK
p
+Kd)e
a'f n
-(K, +2K4)en-l++Kde.-'
e de
(4)
4
2.3 Fuzzy gain scheduling
According to the methodology proposed by Zhao et al.
where K, = KpVT/T and Kd = KpTd/VT [3]. the three cunrent PID parameters are determined as
following.
2.2 Fuzzy Logic Kp= (Kp, ma,~
) K; + Kpn, l

Fuzzy logic can emulate decision experience of human Kd

iu1 =!d- -d
(dd,m,, mi,,)K*++d,min
id.miZd *Kd
(6)
to intuitively construct fuzzy controller. The emulations p
by fuzzy logic can easily describe, represent. and Ki =
a'Kd
manipulate the vague situations in the same as the
human's behaviours. The advantages of the fuzzy Where K 'p K'd and a are constants that are determined
controller are not required the rigour of a mathematical bv means of fuzzy! mechanism. Kp,.=, Kp,min. Kdmax and
model and the controller is a nonlinear miiodel. which can Kdmm. are constants, wliich are adopted to normalize the

1496
values of Kp and Kd½ which have the values in the range FPGA. Thus, all of operators consist of 3 circuits that
of zero and one. These constants are determined by the are: full adder, which has 3 inputs at each input has 20
following rule of thumb. bits, full adder, which has 2 inputs at each input has 10
Kp,min = 0.322K,, Kp,m = 0.6K. bits, and multipliers, which has 2 inputs at each input has
(7) 10 bits. Each process is controlled by state machine.
Kd,min 0.08KT, Kdm, = 0. 15K4T0 which related to clock signal.
K2, and T, are the gain and the period of oscillation at the
stabilitvh limit under proportional control, respectivel.
Processl Process2 Proce ss 3

The input e(t) and Ae(t) of the fuzzv module use seven
triangular membership functions. The output K 'p and K'd
use two exponential membership functions: meanwhile. V ;4K~e I K.+T;' a A
ac uses four singleton membership functions. The fuzz's
rule-base is determined with heuristic based on the step
response of the process. Thus, the sets of rule-base are (g) / i + 2Kg .) e,?. + K,, eii+ [ T?'
[ o = (X + K + K'). e 'K-
slhown in table 1 (for K 'p). K 'd and a are shown in table
2 and table 3, respectively. Figure 2: The process within digital PID processor.
3.2 Fuzzy - PID Processor
Table 1: Fuzzy tuning rules for K'0
Ae(t) Fuzzy-PID processor. XC2S50-5tq-144, is designed with
NB NM NS ZO PS PMJ PB the fuzzx gain schleduling metlhod [3]. which consists of
NB B B B B B B B
NM S B B B B B S two inputs (e(t) and Ae(tb) of the process. Each input
NS S S B B B S S uses seven triangle membership functions. which
e(tj zo s s s B S S S
PS
PM
S
S
S
B
B
B
B
B
B
B
S
B
S
S
provide to formulate PID parameters: Kp, Kd and ua. The
PB B B B B B B B six triangle membership functions are used to assign
output variables (Kp and Kd). oc uses five singleton
Table 2: Fuzzy tuning rules for K d membership functions. Figure 3 and 4 are shown the
Ae(t) membership functions of inputs and outputs. The fuzzy
NB
NB
S
NM
S
NS
S
ZO
S
PS
S
PM
S
PB
S
rules are heuristically determined based on the step
NM B B S S S B B response of process.
NS B B B S B B B
e(t) ZO
PS
B
B
B
B B
B B B B B NB NM NS ZO PS PM PB
S B B B
PM B B S S S B B
PB S S S S S S S e(t)
or
Aeft)
Table 3: Fuzzy tuning rules for oc Figure 3: Membership function for e(t) and Ae(t)
Ae(t)
NB NM NS ZO PS PM PB Z VS S M B VB
NB 2 2 2 ' I 2
NM 3 3 2 2 2 3 3
NS 4 3 3 2 3 3 4 Kp
or
e(t) Zo S 4 3 3 3 4 5 o
PS 4 3 3 2 3 4 Kd
PM
PB
3
2
3
2
2
2
2 2
2
3 3 Figure 4: Membership function for Kp and Kd
The linguistic variables of Figure 3 and 4 are given as
3 METHODOLOGY following:
NB: Negative Big: NM: Negative Medium:
3.1 PID processor NS: Negative Small: Z: Zero,
The digital PID processor is embedded on chip FPGA. PS: Positive Small: PM: Positive Medium:
which uses algoritlun of digital PID equation. The block PB: Positive Big, VS: Very Small:
of diagram is shown in figure 1. Let SP and PV be 10 S: Small: M: Medium!
bits, k-p. Ki and Kdbe 8 bits, and VO be 12 bits. B: Big: VB: Very Big.
8 bit 8 bit 8 bit
Figure 5 shows block diagram of fuzzy processor.
Fuzzification blocks use the Look Up Table (LUT)
10 bit K, K- Kc technique to transfer crisp value to fuzzy value (Notice:
SPF
10bit Digital PID Processor the degree of overlap between membership function does
12 bit not exceed two functions). The block of rule inference
Figure 1: Block diagram of digital PID processor. are used to approximate of reasoning, which corresponds
with variables of inputs and outputs. Defuzziflcation
The internal mechanisms of digital PID processor consist block uses to convert fuzzy output to crisp value by
of 3 processes as shown in Figure 2. Process 1. 2 and 3 using COG method that shown in equation (5). All block
are a sharing operator in order to reduce gate number of is controlled by clock signal.

1497
 processor is operating to compute the parameters p4 Kd?
and K,: the processor uses 16 clock signals for nmultiplier
3 clock signals for adder, 56 clock signals for division. 5
clock signals for PID processor and some of the other
uses 5 clock signals. The block diagran of the fuzzy-
PID controller is shown in figure 9, which consist of
ADC. DAC and fuzzy - PU) processor.

4 bit h t

Mult3plier 84bit (Otpt

Figure 5: Block diagram of Fuzzv processor. ClocFgr 9 d f y
Architectures of the fuzzNy processor on FPGA in each E
FL LUT
bi
block are shown in Figures 6 to 8. Fbigur 8:arhiecur oftedfuzfctinbok
The fu -PJDcontrollerisvMu
erie by eprmnwi
Clock

4bit + E, Digital PID ' Divisiut

F 7j
cip15 btt Generate
Crisp Address
Selection MF
KIFWI Figure 8: arvlvitecture of the defusaification block.
Signal
S :i: ;: -:00 Memorc ::
Addr s et j ; 0 0000: 0; vI Rule ; ;0
LWT
Membership experimetK T:
= 75 ad = 2 s. at s1 i:l :
tuitreton
100msec. Hence. from equation (7) the rangfce
Figure 6: architecture of the fuzzification block.
Fuzzification block, which generates address selection
signal, is shown in Figure 6. The generated signal will KiV Sensor 7 7
correspond with crisp value, which is read fuzzv values Figure 9: block diagram of the fuzzy - PID controller.
from memoir and send to the rule inference block. The
inference block is used to formulate the reason from The fuzzv-PID controller is vrerified bTexeimn wih
membership function by LUT and find out the fuzzy level and tem-perature process control. Figure 10
output values by- max-min operators. The rule inference Kp,min 0.32x7524p,K:
illustrates a diagram of tlleKp,,m=.X54
level process control.. which
mechanism is shown in figure 7. controls level witIfin bottom tank bvl adjusts the
4 bit
percentage of valves. The v alves are controlled bi7 fulzZ,5
- PID controller (control signal is 4 - 20 siAi-). From the
4 Max - Mit
experiment, Ku, = 75 and T,, = 2 sec. at saimpling rate=
4 bit
100 insec. Hence, from equation (7) the range of
pararneter is sliown in tlle following:
It024,
4 bit
4 bit kDpmin = 0.3"2 x 75 = 24, lkp,?ras=0.6 x 75 = 45
4 bit Kd,min =0.08 X 75 x 2- 12, Kdm,ma. = 0.15 X 75 x 2-=22.5

MF t - ?t RuleO
t Fuzz Rule

Figure 7: architecture of the inference rule block.

Schemnatic of the defuzzification block is shown in figure
8, which consists of adder module, mnultiplier module
[4], division module. memorv crisp output value and
some of other logic. Fuzzy--PID processor uses to
compute the parameters of PID (k:p Kt and K): thus,
each module is used repeatabilit to reduce internal gate
of chip FPGA. The recall module was controlled by
clock signal. The designed modules of adder and
multiplier use only one clock signal: whereas. division Figure 10: Diagram of experimental level process svstem.
module used 14 clock signals. Meanwhile the fuzzy-PID

1498
Tables 4 and 5 show fuzzv nile-base of Kp and Kd, which Table 7: Fuzzy rule-base forK, of temperature control.
use the membership functions in Figure 3 and 4. The Ae(i)
linguistic variables are defined separation of interval of NB
NB
VB
NM
VB
NS
VB
ZO
VB
PS
VB
PM
VB
PB
VB
Kp and Kd. The fuzzv rules of a are slhown in table 6. NM
NS
S
VS
M
S
B
M
VB
VB
B
M
M
S
S
VS
Table 4: Fuzzy rule-base for K, of level process control.
e(t) Zo
PS
Z
Z
z
VS
z
S
MB Z
S
Z
VS
Z
Z
PM Z S M B M S Z
Ae(W) PB VB VB VB VB VB VB VB
NB NM NS ZO PS PM PB
NB VB VB VB VB VB VB VB
NM Z B S VB S B Z Table 8: Fuzzv rule-base forLd of temperature control.
NS Z VS VS VB VS VS Z
zo
PS Z
z z
VS
VS
VS
VB
VB
VS
VS
VZ
VS
Z NB NM
Ae(t)
NS ZO PS PM PB
Z
PM Z B S VB S B Z NB Z Z Z Z Z Z Z
PB VB VB VB VB VB VB VB NM NI S VS Z VS S Z
NS B M VS S VS M B
e(t) zo VB VB VB VB VB VB VB
Table 5: Fuzzy rule-base for LTd of level process control. PS
PM
VB
VB
VB VB M VB VB VB
VB M S M VB VB
Ae(t) PB B B B B B B B
NB NM NS ZO PS PM PB
NB Z Z Z Z Z Z Z
NM
NS
VB
VB
VB
B
VS
B
Z
Z
VS
B
VB
B
VB
VB
4 EXPERIMENTAL RESULT
e(t) Zo VB VB VB VB VB VB VB
PS
PM
VB
VB
B
VB
B
VS
Z
Z
B
VS
B
VB
VB
VB
4.1 Simulation Results
PB Z Z Z Z Z Z Z
The fabricated processor is verified by simulation, wh1ich
uses the application program ModelSimXE. The
Table 6 Fuzzy} rule-base for (x . simulations of fuzzy-PID processor to observe the
Ae(t) changing of parameter are slhown in figure 12.
NB NM NS ZO PS PM PB
NB 2 2 2 2 2 ..

.W . W ......
.^s [email protected]

NNM 3 3 2 2 2 3 3
NS 4 3 3 2 3 3 4
e(tJ Zo 5 4 3 3 3 4 5
PS 4 3 3 2 3 3 4
PM 3 3 2 2 2 3 3 .0sr
PB 2 2 2 2 2

Diagram of temperature process control is shown in

Figure 11. The fuzzy - PID controller is used for control
temperature of oven, wliich is sent ampere between 4 to
20 mA to block the phase control for controlling Figure 12: Simulation result of the Fuzzv-PID processor.
electrical heater. The inputs of fuzzy-PID controller is From the result. the process changing has effect to change
obtained from transmitter. 0-10 1 From the experiment. of the pammeters of PID too. which depends on the fuzzy
K,, = 150 and T1, = 5 sec. at sampling rate = 100 msec. rule-base. From the XiliRxWebpack Synthesis, this
Therefore, from the Eq. (7) the ranges of parameter are processor can execute at maximum frequency: 40.550
showed in the follow ing: MHz w?ith one-action using 85 clock cycles. Tlherefore.
execute times about 24.661 nsec x 85 = 2.096 ,usec per
Kpmin 0.32 x 150 = 48 Kpmai = 0.6 x 150 g90 action. Timing summarm are shown in the following.
Kd,mini 0.08 x 150 N 5 60. Kd.ma = 0.15 x 150 x =5 112.5
Timing Summar:
Fuzzv - PID controller
0T- 10 rl based on FPGA Speed Grade: -5
using
Athmebership functionsinFigueA3D
and D 4A Minimum period: 24.661nts (Maximum Frequencv: 40.550AM1Hz)
Minimum input arrival time before clock: 14.496ns
Maximum output required time after clock: 9.992ns
E
Maximum combinational path delav: 13.384ns
~~~~Convertor
OVEN
4.2 The results of implementation
The experimental results of level process control are
= N 4 -20 mA
slhown in figure 13 and 14. In figure 13. used the fuzzyr
IPhase Conhtol
PID controller based on FPGA to control level at 75 %
Figure 1 1: Diagram of temperature conrtol system. and then the changing level to 50 %. Figure 14 uses the
standard PID controller (E50AK: automatic tunable
Tables 7 and 8 show fuzzv rule-base of K. and Kd, bv parameter svstem) to control the levjel process control.
using the meinbership functions in Figure 3 and 4. Tlle
linguistic variables are defined by separation of intemral Experimental results of temperature control process are
of Kp and Kd. Table 6 shows the fuzz rule-base of a. shown in figure 15 and 16. The response of the proposed
metlhod to control the temperature at 60 °C is shown in

1499
Figure 15. The response of standard PID controller to photographs of equipments, that use to experiment, are
control temperature at 50 °C is shown in figure 16. slhown in figure 16 and 17.

p`K~
, I's,
/ .:.>Y -..:

;'- ':' -..

L.

Figure 13: The experimental result use fuzzy PID

controller based on FPGA, by control level at
75 % and then step clhange to 50 %. ss.

/l
1

Figure 14: The experimental result use standard PID

controller E50AK. by conitrol level at 75 %
and then step change to 50 %.
Figure 17:
5 Conclusions
From the experiment of process control, the fuzzy-PID
processor can compute the parameter of PID processor
tc
;c: bi
by depending on fuzzy rule-base. For another process.
this controller can implement by designing the suitability
*i:ja.L.. of the fuzzy rule inference. The fabricated FPGA chip
Figure 15: The experimental result use fuzzy PID provides the maximum execute time about 2.096 ,sec
per actioni. Therefore, the fuzzy PID processor can apply
controller based on FPGA to control to control process that faster than the level and
temperature at 60 'C. temperature control process by, only adjust the fuzzv rule
........". inference and sampling time.
Mi~~~~~

Finally, the fuzzv-PID controller based on chip FPGA

are verified by experiment the level process and
temperature process. which the fuzzy rule inference
obtained from process observation (trial and error). From
the experiment. the changing of manipulate variable
(MV) depends on process variable (PV). The efficiency
of the fuzzv,-PID controller is better than standard PID
Figure 14: The experimental result use standard PID E5AK.
controller ESOAK to control temperature at
SOOC. REFERENCES
Table 9: The efficiencv of both controllers [1] Chi-Tsong Chew "'Analog and digital control
Cntrollei Fuzzy PU) Standard PU) system design," Saunders College Publishing,
based on
(5K 1993.
Parametr FPGA (ESAK)
[2] J. Yaw, M. Ryan and J. Power, "Using fuzzy logic
Level process: toward intelligent system." Prentice Hall, New York.
Rise time 40 sec. 45 sec. 1994.
Setting time 50 sec. 60 sec. [3] Z.Y.Zhao, M.Tomizuka. "Fuzzy gain sclheduling of
Overshoot 0 0 PID controller."IEEE, pp.698-703,1992.
Temperature process: [4] Charles H. Roth. Jr, "Digital System Design Using
Rise time 60 sec. 50 sec. VHDL,"' P WS Publishing Companyv Boston. 1998.
Setting time 480 sec. 420 sec. [5] R. Townsend, "Digital Computer Structure and
Overshoot 0 12 % Design,"" Butterworth Scientific, londow 2 nd

The efficient of controllers are shown in table 9. which is pp. 1 17-143, 1982.
compared both level and temperature controllers. The [6] A. Visioli, "Tuning of PID controllers with fuzzy
logic.*' IEE pr-oc.-Control Theory Appl.. Vol.
148.No.1, 2001.

1500