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Chap5 Lect15 Combo

This document discusses principles of combinational circuit design in VLSI systems. It covers topics such as logical effort of compound gates, bubble pushing, multiplexer design, input ordering, asymmetric gates, skewed gates, and optimizing transistor ratios. The key points are calculating logical effort and delay for different gate structures, techniques for simplifying logic functions through transformations, and methods for optimizing speed, area and power through transistor sizing and skewing inputs.

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Sravya Reddy
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© Attribution Non-Commercial (BY-NC)
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38 views11 pages

Chap5 Lect15 Combo

This document discusses principles of combinational circuit design in VLSI systems. It covers topics such as logical effort of compound gates, bubble pushing, multiplexer design, input ordering, asymmetric gates, skewed gates, and optimizing transistor ratios. The key points are calculating logical effort and delay for different gate structures, techniques for simplifying logic functions through transformations, and methods for optimizing speed, area and power through transistor sizing and skewing inputs.

Uploaded by

Sravya Reddy
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Principles of VLSI Design

Combinational Circuits

CMPE 413

Combinational Circuits Logical Effort of Compound Gates


unit inverter AOI21 AOI22 Complex AOI

Y=A
A Y

Y = AgB + C
A B C Y

Y = AgB + C gD
A B C D A 4 B 4 D 2 C 2 D 4 4 2 2 Y Y

Y = Ag( B + C ) + D gE
D E A B C B C D E D 6 6 6 2 2 B A E A 2 3 6 2 C Y 2 Y

A A 2 1 Y A B

4 B C 2 2 4 C

4 Y 1

C A B

gA = 3/3 p = 3/3

gA = 6/3 gB = 6/3 gC = 5/3 p = 7/3

gA = 6/3 gB = 6/3 gC = 6/3 gD = 6/3 p = 12/3

gA = 5/3 gB = 8/3 gC = 8/3 gD = 8/3 gE = 8/3 p = 16/3

Principles of VLSI Design

Combinational Circuits

CMPE 413

Combinational Circuits Bubble Pushing Start with network of AND/OR gates Convert to NAND/NOR + inverters Push bubbles around to simplify logic DeMorgan's Law

Y (a) (b)

Y (c) D (d)

Principles of VLSI Design

Combinational Circuits

CMPE 413

Combinational Circuits Multiplexer example: Estimate the delay of NAND and compound gate designs of a mux with maximum capacitance of 16 units on each input and an output load of 160 units
D0 S Y D1 S

D0 S D1 S
H = 160/16 = 10 B=1 N=2

P=2+2=4 G = (4/3) * (4/3) = 16/9 F = GBH = 160/9 = N F = 4.2 f D = Nf + P = 12.4

P=4+1=5 G = (6/3) * (1) = 2 F = GBH = 20 = N F = 4.5 f D = Nf + P =


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Principles of VLSI Design

Combinational Circuits

CMPE 413

Combinational Circuits Example (contd.): Annotate transistor sizes to achieve the above delays

8 8 8 25 25 25 25 Y 10 10 6 6 10 10 6 6 24 12 Y

8 8 8

16

160 * (4/3) / 4.2 = 50

16

160 * 1 / 4.5 = 36

Principles of VLSI Design

Combinational Circuits

CMPE 413

Input Ordering We were using a very simple delay model Let's calculate the parasitic delay for Y falling, considering input arrival times i.e. If A arrives latest? If B arrives latest?

2 A B

2 2 2x 6C 2C

With A arriving the latest the delay is 2 However with B arriving the latest the delay is 2.33

Outer input is the one closest to the supply rail (B) Inner input is the closest to the output (A) If input arrival times are known, connect the latest input to the inner terminal

Principles of VLSI Design

Combinational Circuits

CMPE 413

Asymmetric Gates Asymmetric gates favor one input over the other E.g. Suppose input A is the most critical Use smaller transistor on A (less C) Boost size of non-critical input This keeps the total resistance the same gA= 10/9 gRESET = 2 gTOTAL = gA + gRESET = 28/9 Asymmetric gate approaches g=1 on critical input but total logical effort goes up
A reset

2 A reset

2 4/3 4

2
Symmetric gates Inputs can be made perfectly symmetric

2 1 1

A B

1 1

Principles of VLSI Design

Combinational Circuits

CMPE 413

Skewed Gates Skewed gates favor one edge over the other Ex: Rising output of the inverter is the most critical Downsize the non-critical NMOS transistor
HI-skew inverter 2 A 1/2 Y A 1 unskewed inverter (equal rise resistance) 2 Y A 1/2 unskewed inverter (equal fall resistance) 1 Y

Definition: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition gu = 2.5/3 = 5/6, gd = 2.5/1.5 = 5/3 Skewed gates reduce size of non-critical transistors Logical effort is smaller for preferred direction but larger for the other direction
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Principles of VLSI Design

Combinational Circuits

CMPE 413

Skewed Gates

Inverter

NAND2
2 2 Y 2 2 gu = 4/3 gd = 4/3 gavg = 4/3 B Y A gu = 1 gd = 2 gavg = 3/2 B Y A gu = 2 gd = 1 gavg = 3/2 B A

NOR2
4 4 Y 1 1 gu = 5/3 gd = 5/3 gavg = 5/3

unskewed

2 A 1 Y gu = 1 gd = 1 gavg = 1

A B

2 1 1

4 4 Y 1/2 1/2 gu = 3/2 gd = 3 gavg = 9/4

HI-skew

2 A 1/2 Y gu = 5/6 gd = 5/3 gavg = 5/4

A B

1 2 2

2 2 Y 1 1 gu = 2 gd = 1 gavg = 3/2

LO-skew

1 A 1 Y gu = 4/3 gd = 2/3 gavg = 1

A B

Principles of VLSI Design

Combinational Circuits

CMPE 413

Asymmetric Skew Combine asymmetric and skewed gates Downsize non-critical transistors on unimportant input Reduce parasitic delay for critical input

A reset

1 A reset

2 4/3 4

Principles of VLSI Design

Combinational Circuits

CMPE 413

Best P/N Ratio We have been selecting the P/N ratio to obtain unit rise and fall resistance (2-3 for inverter) Alternative: choose ratio for least average delay Eg: Inverter delay, driving an identical inverter ( = P/N ratio) P A tpdf = (P + 1) tpdr = (P + 1) (/P) tpd = (P + 1) (1 + /P) / 2 = (P + 1 + + /P) / 2 Differentiate wrt P, least delay for
P =

In general, best P/N ratio is sqrt of that giving equal delay Only improves average delay slightly for inverters But significantly reduces both area and power
Inverter NAND2
2 2 Y A B 2 2 gu = 4/3 gd = 4/3 gavg = 4/3 B A 1

NOR2
2 2 Y 1 gu = 2 gd = 1 gavg = 3/2

fastest P/N ratio

1.414 Y 1 gu = 1.15 gd = 0.81 gavg = 0.98

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Principles of VLSI Design

Combinational Circuits

CMPE 413

Combination Circuit Observations For speed: NAND vs. NOR Many simple stages vs. fewer high fan-in stages Latest-arriving input For area and power: Many simple stages vs. fewer high fan-in stages

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