Introduction to Assembly Language

1. Machine Language
This is what the computer actually sees and deals with. Every
command the computer sees is given as a number or sequence of
numbers.
2. Assembly Language
This is the same as machine language, except the command
numbers have been replaced by letter sequences which are easier
to memorize. Other small things are done to make it easier as well.
3. High-Level Language
They are there to make programming easier. Assembly language
requires you to work with the machine itself. High-level languages
allow you to describe the program in a more natural language. A
single command in a high-level language usually is equivalent to
several commands in an assembly language.
 Assembly programming is low-level programming using some basic syntax to
represent machine code for a specific CPU.
 An assembler is used to translate the assembly code into the machine code
for the target computer.
 Assembly language is useful in making efficient code that consumes less
number of clock cycles and takes minimum memory footprint as compared
to high level language.
 This makes Assembly Language Programming to be used in designing
software for memory and power constrained portable devices.
 The first meaningful processor Intel released was 8080, an 8bit processor, which
became popular due to its simplistic design and versatile architecture.
 However, an advanced version was released as 8085 based on the experience gained
from 8080. The processor became widely popular in the engineering community due to
its simple and logical nature.
 The first 16-bit CPU produced by Intel was the 8086. A version of the 8086 that used an
8-bit data bus, the 8088, was released later to permit lower-cost designs.

 The 8088 was used in the very popular IBM PC and many later compatible machines.
Intel’s first 32-bit CPU was the 80386. It was designed to be backwards compatible with
the large amount of software, which was available for the 8086. The 80386 extended
the data and address registers to 32 bits.
 The Intel ’386 also included a sophisticated memory management
architecture that allowed virtual memory and memory protection to be
implemented. This same basic 80386 architecture is used in the Pentium
series and compatible processors

 The success of these processors were unexpected for the developers

themselves, because when they were introduced the processor contained a
timer tick count which was valid for five years only. History however took a
turn and the architecture is there at every desk even after 25 years.
 When to use Assembly Language:

 if bugs have to be analyzed,

 if the program executes not as designed and expected,
 if the higher-level language doesn't support the use of certain hardware features,
 if time-critical in line routines require assembly language portions,
 Why use Assembly Language?
 Short and easy: Assembler instructions are shorter. The programs are easier to debug,
every step makes sense.
 Fast and quick: Because only necessary code steps are executed, assembly programs are
as fast as possible.
 Assembler is easy to learn: Learning assembly language for whatever hardware type
brings you to understand the basic concepts of any other assembly language dialects.
Consider this an advantage: by learning assembly language you simultaneously learn more
about the hardware. Higher level languages often do not allow you to use special
hardware features and so hide these functions.
 The basic operational design of a computer system is called its architecture.
The architecture of most computers in use today, e.g the 80x86 processor
series is based on the design of the pioneer, John Von Neumann.
 A typical Von Neumann system has three major components:
 The central processing unit (or CPU)
 Memory, and
 Input/output (or I/O).
 The way a system designer combines these components impacts system
performance. In Von Neumann Architecture (VNA) machines, like the 80x86
family, the CPU is where all the action takes place. All computations occur
inside the CPU.
 Data and CPU instructions reside in memory until required by the CPU. To the
CPU, most I/O devices look like memory because the CPU can store data to
an output device and read data from an input device.
 The major difference between memory and I/O locations is the fact that I/O
locations are generally associated with external devices in the outside world.

Figure 1: Components of a Computer System

 The System Bus
 It connects the various components of a VNA machine, transmits and shares data throughout the
computer and between devices. CPU is the heart of the computer and most computations occur
inside the CPU. RAM is a place to where the programs are loaded in order to be executed.
 The 80x86 Processor consist of three major buses:
 The data bus
 The address bus
 The control bus
 A bus is a collection of wires on which electrical signals pass between components in the system.
Buses vary from processor to processor. However, each bus carries comparable information on all
processors; e.g., the data bus may have a different implementation on the 80386 than on the 8088,
but both carry data between the processor, I/O, and memory.
 A typical 80x86 system component uses standard (Transistor-Transistor Logic: A digital Logic design
in which a bipolar transistor act on direct current pulses) TTL logic levels. i.e each wire on a bus
uses a standard voltage level to represent zero(0) and one(1).
 The Data Bus
 The data bus is used to shuffle data between the various components in a
computer system. The size of this bus varies widely in the 80x86 family and it
defines the “size” of the processor.
 The data bus contains 8, 16, 32, or 64 lines on typical 80x86 systems. The 8088
and 80188 microprocessors have an 8-bit data bus (eight data lines). The 8086,
80186, 80286, and 80386SX processors have a 16-bit data bus.
 The 80386DX, 80486, and Pentium Overdrive Ô processors have a 32-bit data bus,
while Pentium Ô and Pentium Pro processors have a 64-bit data bus.
 Future versions of the chip (the 80686/80786) may have a larger bus. Having an
8-bit data bus does not limit the processor to 8-bit data types. It simply means
that the processor can only access one byte of data per memory cycle.
The Data Bus

 The size of the data bus affects the performance of the system more than
the size of any other bus. For instance, processors with a 16 bit bus are
naturally faster than processors with an eight bit bus.
 The data bus is used to move the data from the memory to the processor
in a read operation and from the processor to the memory in a write
operation.
 Data moves from both, processor to memory and memory to processor.
Hence, the data bus is bidirectional.
 The Address Bus
 The data bus on an 80x86 family processor transfers information between a
particular memory location or I/O device and the CPU.
 The address bus is unidirectional and address always travels from processor to
memory. This is because memory is a dumb device and cannot predict which
element the processor at a particular instant of time needs.
 To differentiate memory locations and I/O devices, the system designer assigns a
unique memory address to each memory element and I/O device. When the
software wants to access some particular memory location or I/O device, it places
the corresponding address on the address bus.
 Circuitry associated with the memory or I/O device recognizes this address and
instructs the memory or I/O device to read the data from or place data on the
data bus.
The Address Bus
 Only the device whose address matches the value on the address bus
responds. With a single address line, a processor could create exactly two
unique addresses: zero and one. With n address lines, the processor can
provide 2n unique addresses.
 The number of bits on the address bus will determine the maximum
number of addressable memory and I/O locations. The 8088 and 8086,
for example, have 20-bit address bus. Therefore, they can access up to
1,048,576 (or 220) memory locations
 The Control Bus
 The control bus is an eclectic collection of signals that control how the processor
communicates with the rest of the system.
 Control bus is special and relatively complex, because different lines comprising it
behave differently.
 There are two lines on the control bus, read and write, which specify the
direction of data flow. The control bus carries the intent of the processor that it
wants to read or to write. Memory changes its behavior in response to this signal
from the processor. It defines the direction of data flow.
 If processor wants to read but memory wants to write, there will be no
communication or useful flow of information. Both must be synchronized, like a
speaker speaks and the listener listens.
 If both speak simultaneously or both listen there will be no communication. This
precise synchronization between the processor and the memory is the responsibility
of the control bus. It is only the mechanism because the responsibility of sending the
appropriate signals on the control bus to the memory is of the processor
 The control bus is a bidirectional bus and can carry information from processor to
memory as well as from memory to processor because for situations when
peripherals want to talk to the processor when the processor wasn’t expecting them
to speak, special lines in the control bus are used. Therefore, the information in such
signals is indicates the incapability of the peripheral to do something for the moment.
 Other signals include system clocks, interrupt lines, status lines, and so on. The exact
make up of the control bus varies among processors in the 80x86 family.
Register Architecture
CPU REGISTERS
 The basic purpose of a computer is to perform operations, and operations need
operands. Operands are the data on which we want to perform a certain operation.
 The addition operation for instance, involves adding two numbers to get their sum. We
can have precisely one address on the address bus and precisely one element on the
data bus. At the very same instant the second operand cannot be brought inside the
processor. As soon as the second is selected, the first operand is no longer there.
 Registers are temporary storage placed inside the processor. Now one operand can be
read in a register and added into the other which is read directly from the memory.
Both are made accessible at one instance of time, one from inside the processor and
one from outside on the data bus.
CPU REGISTERS

 The result can be written to at a distinct location as the operation has completed and
we can access a different memory cell. Sometimes, both operands are held in
registers for the sake of efficiency.
 Registers are like a scratch pad ram inside the processor and their operation is very
much like normal memory cells. They have precise locations and remember what is
placed inside them.
 They are used when we need more than one data element inside the processor at
one time.
 Registers are relatively very small in number, and are therefore a very scarce and
precious resource.
 The 8086 CPU has 14 registers and each register has its own name
CPU REGISTERS

 There are 8 general-purpose registers:

 AX - the accumulator register (divided into AH / AL), for multiply/divide
 BX -the base address register (divided into BH / BL), index register for
MOVE
 CX - the count register (divided into CH / CL), for string operations
 DX - the data register (divided into DH / DL): port address for IN and OUT
 SI - source index register.
 DI - destination index register.
 BP - base pointer.
 SP - stack pointer.
 The programmer determines the usage for each register regardless of its name.
 The size of the above registers is 16 bits, 0011000000111001b (in binary form),
or 12345 in decimal (human) form.
CPU REGISTERS
 The registers AX, BX, CX, and DX behave as general purpose registers in Intel
architecture and do some specific functions in addition to it. X in their names stand for
extended (16bit registers). For example AX means we are referring to the extended
16bit “A” register, where A stands for Accumulator. Its upper and lower byte are
separately accessible as AH (A high byte) and AL (A low byte).
 All general purpose registers can be accessed as one 16bit register or as two 8bit
registers. The two registers AH and AL are part of the big whole AX. AX is a composite
or extended register formed by gluing together the two parts AH and AL.
 All general purpose registers can act as accumulator in most instructions, but there are
some specific variations which can only work on AX , hence it is named accumulator.
CPU REGISTERS
 The B of BX stands for Base because of its role in memory addressing.
 The C of CX stands for Counter as there are certain instructions that work with an
automatic count in the CX register.
 The D of DX stands for Destination as it acts as the destination in I/O operations.
 The location of registers inside the CPU makes them much faster than memory which
requires a system bus to access it and this takes much longer. Accessing data in a
register usually takes no time, which is why variables should be kept in the registers.
 Register sets are very small and most registers have special purposes which limit their
use as variables, but they are still an excellent place to store temporary data of
calculations.
INDEX REGISTERS
 Index registers are SI (source index) and DI (destination index). These are the index
registers of the Intel architecture which hold address of data and used in memory
access.
 Intel allows many mathematical and logical operations on these registers as well like
the general registers due to its openness and flexibility.
 The source and destination are named because of their implied functionality as the
source or the destination in a special class of instructions called the string instructions.
However their use is not at all restricted to string instructions.
 SI and DI are 16bit and cannot be used as 8bit register pairs like AX, BX, CX, and DX.
INDEX REGISTERS
 Stack Pointer (SP): It is a memory pointer and is used indirectly by a set of
instructions. It has a very special purpose (maintains the program stack). The proper
operation of most programs depends upon the careful use of this register, as this
register would not normally be used for arithmetic computations.

 Base Pointer (BP): It is the bx register, used generally to access parameters and local
variables in a procedure.
SEGMENT REGISTERS
 The segment registers have a very special purpose, i.e. pointing at accessible blocks of
memory. They work together with general purpose registers to access any memory
value.
 If we would like to access memory at the physical address 12345h (hexadecimal), we
would set the DS=1230h and SI = 0045h. More memory can be accessed than with a
single register that is limited to 16-bit values.
 CPU makes a calculation of physical address by multiplying the segment register by
10h and adding general purpose register to it (1230h* 10h + 45h = 12345h):
12300
+ 0045
12345
 The address formed with 2 registers is called an effective address.
SEGMENT REGISTERS
 By default BX, SI and DI registers work with DS segment register; BP and SP work with
SS segment register. Other general purpose registers cannot form an effective address
except BX.
 CS (code segment) - points at the segment containing the current program.
 DS(data segment) - generally points at segment where variables are defined.
 ES (extra segment)- it's up to a coder to define its usage.
 SS(stack segment) - points at the segment containing the stack.
INDEX REGISTERS

 IP (Instruction pointer)
 This is the special register containing the address of the next instruction to be
executed. No mathematics or memory access can be done through this register.
 It is out of our direct control and is automatically used.
 Program control instructions change the IP register.
 IP register always works together with CS segment register and it points to
currently executing instruction.
 Flags Register
 Determines the current state of the processor.
 The flags register is not meaningful as a unit rather it is bit-wise significant and
accordingly each bit is named separately. The bits not named are unused.
INDEX REGISTERS
 Flags Register is modified automatically by CPU after mathematical operations,
this allows to determine the type of the result, and to determine conditions to
transfer control to other parts of the program.

 Generally, these registers cannot be accessed directly.

 The Intel flags register has its bits organized as follows:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
O D I T S Z A P C
FLAGS REGISTERS

C Carry When two 16bit numbers are added the answer can be 17 bits long or when two 8bit numbers are
added the answer can be 9 bits long. This extra bit that won’t fit in the target register is placed in the
carry flag where it can be used and tested.
P Parity Parity is the number of “one” bits in a binary number. Parity is either odd or even. This information is
normally used in communications to verify the integrity of data sent from the sender to the receiver.
A Auxiliary Carry A number in base 16 is called a hex number and can be represented by 4 bits. The collection of 4 bits is
called a nibble. During addition or subtraction if a carry goes from one nibble to the next this flag is set.
Carry flag is for the carry from the whole addition while auxiliary carry is the carry from the first nibble to
the second.
Z Zero Flag The Zero flag is set if the last mathematical or logical instruction has produced a zero in its destination.

S Sign Flag A signed number is represented in its two’s complement form in the computer. The most significant bit
(MSB) of a negative number in this representation is 1 and for a positive number it is zero. The sign bit of
the last mathematical or logical operation’s destination is copied into the sign flag.
T Trap Flag The trap flag has a special role in debugging which will be discussed later.
I Interrupt Flag It tells whether the processor can be interrupted from outside or not. Sometimes the programmer doesn’t
want a particular task to be interrupted so the Interrupt flag can be zeroed for this time. The programmer
rather than the processor sets this flag since the programmer knows when interruption is okay and when it
is not. Interruption can be disabled or enabled by making this bit zero or one, respectively, using special
instructions.
D Direction Flag Specifically related to string instructions, this flag tells whether the current operation has to be done from
bottom to top of the block (D=0) or from top to bottom of the block (D=1).
O Overflow Flag The overflow flag is set during signed arithmetic, e.g. addition or subtraction, when the sign of the
destination changes unexpectedly. The actual process sets the overflow flag whenever the carry into the
MSB is different from the carry out of the MSB
Segmented Memory
 The registers BX, SI, BP and DI can be used to access memory. Combining these
registers inside [ ] symbols can give 17 different memory locations. These
combinations are supported (addressing modes):

[BX + SI] [SI] [BX + SI] + d8

[BX + DI] [DI] [BX + DI] + d8
[BP + SI] d16 (variable offset only) [BP + SI] + d8
[BP + DI] [BX] [BP + DI] + d8

[SI] + d8 [BX + SI] + d16 [SI] + d16

[DI] + d8 [BX + DI] + d16 [DI] + d16
[BP] + d8 [BP + SI] + d16 [BP] + d16
[BX] + d8 [BP + DI] + d16 [BX] + d16
 d8 - stands for 8 bit displacement.
 d16 - stands for 16 bit displacement.
 Displacement can be an immediate value or offset of a variable, or both. It's up to compiler
to calculate a single immediate value.
 Displacement can be inside or outside of [ ] symbols, compiler generates the same machine
code for both ways.
 Displacement is a signed value, so it can be either positive or negative. The compiler takes
care about difference between d8 and d16, and generates the required machine code.
 For example,
 let's assume that DS = 100, BX = 30, SI = 70.
 The following addressing mode: [BX + SI] + 25 is calculated by processor to this
physical address: 100 * 16 + 30 + 70 + 25 = 1725.
Memory Access
 By default DS segment register is used for all modes except those with BP register, where
SS segment register is used.
 An easy way to remember all those possible combinations is given in the chart below:

 There are a total of 17 different legal memory addressing modes on the 8086: disp, [bx],
[bp], [si], [di], disp[bx], disp[bp], disp[si], disp[di], [bx][si], [bx][di], [bp][si], [bp][di],
disp[bx][si], disp [bx][di], disp[bp][si], and disp[bp][di
 For example:
 Choose disp from column one, nothing from column two, [di] from column 3, you get
disp[di].
 Choose disp, [bx], and [di]. You get disp[bx][di].
 Skip column one & two, choose [si]. You get [si]
 Skip column one, choose [bx], then choose [di]. You get [bx][di]
Memory Access
 If there is an addressing mode that cannot be constructed from this table, then it is illegal.
 For example,
 disp[dx][si] is illegal because [dx] cannot be obtained from any of the columns in the
chart.
 BX and BP never go together as well as SI and DI.
 [BX+5] is an example of a valid addressing mode
 The value in segment register (CS, DS, SS, ES) is called a "segment", and the value in
purpose register (BX, SI, DI, BP) is called an "offset".
 When DS contains value 1234h and SI contains the value 7890h it can be also recorded as
1234:7890. The physical address will be 1234h * 10h + 7890h = 19BD0h.
 The effective address is the final offset produced by an addressing mode computation. For
example, if bx contains 10h, the effective address for 10h[bx] is 20h.
Memory Access
 Different addressing modes may take differing amounts of time to compute the effective
address. The exact difference varies from processor to processor, the more complex an
addressing mode is, the longer it takes to compute the effective address.
 Also, complexity of an addressing mode is directly related to the number of terms in the
addressing mode. For example, disp[bx][si] is more complex than [bx].
 The displacement field in all addressing modes except displacement-only can be a signed
eight bit constant or a signed 16 bit constant. If offset is in the range -128…+127 the
instruction will be shorter (and therefore faster) than an instruction with a displacement
outside that range.
Memory Access
 The size of the value in the register does not affect the execution time or size. So if you can
arrange to put a large number in the register(s) and use a small displacement, that is
preferable over a large constant and small values in the register(s).
 If the effective address calculation produces a value greater than 0FFFFh, the CPU ignores
the overflow and the result wraps around back to zero.
 For example, if bx contains 10h, then the instruction mov al, 0FFFFh[bx] will load the al
register from location ds:0Fh, not from location ds:1000Fh.
80x86 Physical Memory Organization

 In a typical VNA machine, the CPU connects to memory via the bus. The 80x86 selects some
particular memory element using a binary number on the address bus. Another way to
view memory is as an array of bytes. A Pascal data structure that roughly corresponds to
memory would be:
 Memory : array [0..MaxRAM] of byte;
 The value on the address bus corresponds to the index supplied to this array. E.g., writing
data to memory is equivalent to
 Memory [address] := Value_to_Write;
 Reading data from memory is equivalent to
 Value_Read := Memory [address];
80x86 Physical Memory Organization
 Different 80x86 CPUs have different address busses that control the maximum number
of elements in the memory array). However, regardless of the number of address lines
on the bus, most computer systems do not have one byte of memory for each
addressable location.
 For example, 80386 processors have 32 address lines allowing up to four gigabytes of
memory. Very few 80386 systems actually have four gigabytes. Usually, one to 256
megabytes is found in an 80x86 based system.
 This corresponds to the entire address space of the 8088, 8086, 80186, and 80188
microprocessors.
 Most DOS programs limit their program and data addresses to locations in this range.
Addresses limited to this range are named real addresses after the 80x86 real mode.
Segments on the 80x86

 Segmentation provides a powerful memory management mechanism, allowing

programmers to partition their programs into modules that operate independently of
one another.
 Segments provide a way to easily implement object-oriented programs. Segments allow
two processes to easily share data.
 It allows programmers to extend the addressability of a processor. In the case of the
8086, segmentation, Intel’s designers extend the maximum addressable memory from
64K to one megabyte.
Segments on the 80x86

 Memory looks like a linear array of bytes. A single index (address) selects some
particular byte from that array which may be termed linear or flat addressing.
 Segmented addressing uses two components to specify a memory location: a segment
value and an offset within that segment. Ideally, the segment and offset values are
independent of one another.
 The best way to describe segmented addressing is with a two-dimensional array. The
segment provides one of the indices into the array, the offset provides the other.