acer hc eae a a REE ENETEr NTN oe LR 12.3.10 Available PLAs Some of the commercially available PLA ICs with their features are given in Table 12.2. The 825200 and 82S201 are pin-for-pin mask programmable replacements for the 828100 and 828101, respectively. The PLS 100 and PLS 105 PLA: ni to 825100 and 828105, respectively. The DM 7575 PLA has totem-pole output, 1M5200 have passive pull-up. The devices with passive pull-up are useful for expanding func- tions by wire ANDing the outputs of similar other devices A most commonly used type of PLD is programmable array logic (PAL). I is programmable array of logic gates on a single chip in AND-OR configuration. In contrast to PLA, it has program- mable AND array and a fixed OR array in which each OR gate gets inpuls from some of the AND gates, 1é7all the AND gate ontputs are not connected to any OR gate. Figure 12.17 illustrates the configuration of AND and OR arrays for a PAL with 5 inputs, 8 programmable AND gates and 4 fixed OR gates. Each AND gate has all the 10 inputs (in complemented and uncomplemented form) with fusible links intact which can be programmed to generate 8 product terms. Each OR gate gets inputs from the outputs of only two AND gates shown by *, The input and output Grcuits of PALs are similar to those of PLAs. The number of fusible links in a PAL is the product of 2Mand n where Mis the number of input variables and nis the number of product terms,20. 3 51 =e 96. mt TLL wdyg sg St ost SE 8 96 * atqneduzos dia TLE uid-ge 3 gt 08 90 8 ae or ajqnediios iq ESS —— - ~. WE se 009 8 se 8. 8h ot ayqueduros. dig TLL wid-ge 009 s+ O8 20. 8 8h oT Via oeezwa Vid seca Vist _torsee __oorsen Vid Tozs7e Somes AY) IAM SV]g aquieae amos [ZL ae. TLL ez 009 st 08 SE ae ge ot Vid o0zsze yen 2 0 a sunray spaaay 20] uoned —affijon oun sonpozy— sinduy mdmoymduy — Fureyoug -ssrp ramog —Ayddng ssaoy ning, jo equngFig. 12.17 Programmable array logic. One of the most commonly used PAL 16L8 is shown in Fig. 12.18. Its programmable AND array consists of 64 gates. It has 16 input variables and 8 outputs, therefore, @ach AND gate has 2x 16 = 32 inputs. Fight AND gates are associated with each output pin, seven of them provide inputs to a fixed 7-input OR gate and the eighth is connected to the enable input terminal of the output buffer. Thus, any output can perform only logic functions that can be expressed as sums of seven or fewer product terms. Each product term can be q function of up to all 16 inputs but only 7 such product terms are available, Since, in a PAL the inputs to the OR gates are fixed, therefore, no two OR gates can share a product term, Where a product term is needed by two OR gates, it must be generated twice. There is a three-state inverter between the output of each OR gate and the output pin of the device, therefore, the output may be programmed as always enabled, always disabled, or enabled by a product term involving the inputs (Problem 12.11)Table 12.3 (Contd.) Taputs Ousputs External Feedback Total ‘Bidirectional Regi Combis Total” Package combinational stered rational pins 8 20 8 24 10 20 4 24 10 20 8 24 10 20 10 22 16 20 18 12.4.6 Simple PLDs (SPLDs) The PLDs such as PLAs, PALs and other similar type of devices discussed above are simple PLDs (SPLDs). Some of the major manufacturers of SPLDs, alongwith their some of the SPLD products and their WWW locators are given in Table 12.4 Table 12.4 SPLD manufacturers SPLD Protuets WWW Locator Manufacturer Altera Classic hutp://wwrw-altera.com Atmd PAL hitp://wwaw.atmel.com Cypress PAL http://www.cypress.com Lattice GAL hep://worwdatticesemi.com Philips PLAPAL hnp://www.philips.com Vantis PAL’ hup:/Awww.vantis.com ‘The programmabie logic devices (PLDs) such as PLAs and PALs have limited number of inputs, product terms, and outputs. These devices, therefore, can support up to about 32 total number of inputs and outputs only (see Table 12.3) For implementation of civcuits that require more inputs and outputs than that are available in a single SPLD chip, either multiple SPLD chips can be employed as discussed in Sec. 12.3.8 or mote sophisticated type of chip, referred to as complex programmable logic device (CPLD) can be used. ‘ The complexity of any digital IC chip can be specified in terms of number of equivalent 2- input NAND gates. A typical PAL has 8 macrocells, if cach macrocell represents about 20 equivalent gates, then the PAL can accommodate a circuit that needs up to about 160 gates. For circuits requiring a very large number of gates, CPLDs having large number of macrocells (say 512 macrocells) can implement circuits of up to about 10,000 equivalent gates. There are a number of manufacturers of CPLDs manufacturing a wide range of products with different features. Some of the major manufacturers of CPLDs are given in Table 12.5.Table 12.5 CPLD manufacturers Manufacturer CPLD Products WWW Locator MAX 3000, 7000 and 9000 http://www.altera.com ATE, ATV itp://www.atmel.com FLASH 370, Ultra 37000 “huip://www.cypress.com, isp LSI 1000 to 8000 http://www. lattice.com XPLA hitp://vwww-philips.com MACH 1 to 5 hitp://www.vantis.com: XC9500 htp://veveweflinx com 12.5.1 Block Diagram Figure 12.28 gives block diagram of a complex programmable logic device (CPLD). It consists of a number of PAL-like blocks, 1/0 blocks, and a set of interconnection wires. The PAL-ike blocks are connected to a set of interconnection wires and each block is also connected to an I/O block to which a number of chip’s input and output pins are attached. A PALrike block usually consists of about 16 macrocells. Each macrocell consists of an AND-OR configuration, an EX-OR gate, a FLIP-FLOP, a multiplexer, and a tri-state buffer. A typical macrocell is shown in Fig. 12.29. Each AND-OR configuration usually consists of 5-20 AND gates and an OR gate with 5-20 inputs. An OF gate is used to obtain the output of OR gate in inverted or non-inverted form depending upon its other input being 1 or 0 respectively. A D-EF stores the output of the EX-O® gate, a multiplexer selects cither the output of the D-FF or the output of the EX-OR gate depending upon its select input (1 or 0). The tri-state buffer acts as a switch which enables the chip’s pin to be used either as an output (tri-state enabled) or as an input (tri-state disabled). In case the chip's pin is used as an input pin, an external source PAL-Like PAL-Like a & Block Block A iS | - | 1 Bes 1 il Interconnection Wires g Pavike [“ "| Pathe 3 ee Block Block a g g Fig. 12.28 - Block diagram of aeee interconnecting wires PAL-Ike block Fig 12.29 A typical macracell of a CPLD can drive a signal on to the pin which can be connected to other mactocells using the intercon- nection wiring. When used as an input pin, the macrocell becomes redundant and it is wasted 12.5.2 Programming Programmable logic devices, SPLDs and CPLDs, are implemented using electrically erasable programmable read-only memory (EEPROM) technology. These are programmed in the same way as EEPROMs. The SPLD chips have a’ small number of pins and can therefore be taken out of the circuit board, without much of inconvenience, and put in a programming unit, In the case of CPLDs, instead of relying on @ programming unit to configure a chip, it would be very convenient and advantageous if it is possible to perform the programming with the chip remaining attached to the circuit board itself, This method of programming is known as in- system programming (ISP). There are two main reasons for employing ISP. * CPLDs have large number of pins (may even exceed 200) on the chip package, and these pins are fragile and easily bent, ° A socket is required to hold the chip in a programming unit. For large CPLDs the packages used are very expensive, sometimes more expensive than the CPLD device itself For the reasons mentioned above, CPLD devices usually support the ISP technique. For programming SPLDs and CPLDs a large number of programmable switches are required to be configured, hence it is not practically feasible for a user of these chips to specily manually the desired state of each switch. For this purpose computer-aided design (CAD) systems areemployed. Once the user has completed the design of a circnit using CAD tools, a programming {file or fuse map is generated, that specifies the state of each switch in the target PLD required to realize the designed circuit. A computer system that rans the CAD tools is connected by a cable to the programming unit. In the case of the ISP technique a small connector is included on the printed circuit board (PCB) that houses the CPLD and the computer system is connected by a cable to this connector. The programming involves transferring the programming file generated by the CAD system from the computer into the CPLD through this cable. The circuitry on the CPLD that allows in-system programming has been standardized by the IEEE and is usually called a JTAG port. The abbreviation JTAG stands for Joint Test Action Group. It. uses four wires to transfer information between the computer and the device being programmed Figure 12.30 illustrates the use of a JTAG port for programming two CPLDs on a circuit board. To computer Fig. 12.30 JTAG ISP programming, 12.5.3 Packaging CPLDs have a large number of pins, making it impractical to use dual-in-line packaging (DIP) Some of the commonly used packages for CPLDs are: Plastic-Leaded Chip Carrier (PLCC) A PLCC package has pins on all the four sides that ‘wrap around’ the edges of the chip, rather than extending straight down as in the case of a DIP. The IC socket of PLCC is soldered to the PCB, and the chip is held in the socket by friction. Figure 12.31 illustrates a PLCC package with socket Quad flat pack (QFP) A QFP package also has pins on all four sides like a PLOC package, but with pins extending outward from the package with a downward-curving shapevas shown in Fig. 12.32. The QFP’s pins are much thinner than those on a PLCC, making it suitable for , supporting a larger number of pins. QFPs are available with more than 200 pins, whereas PLCCs are limited to fewer than 100 pins. Some of the varieties of QFPs available are: Plastic quad flat pack (PQFP), power quad flat pack (ROFP), and 1.0 mm thin quad flat pack (TOFP). Ceramic pin grid array (PGA) It has pins extending straight outwards from the botiom of the package in a grid pattern. It can accommodate a few hundred pins in total, Figure 12.33 illustrates bottom view of a PGA package.Fig. 12.31 A PLCC package with socket Fig, 12.32 Fig. 12.33 A QEP package Bottom view of a PGA package Ball grid array (BGA) The ball grid array (BGA) packaging is similar to the pin grid array (PGA) packaging except that the pins aré small round balls, instead of posts. The pins ina BGA package are very small, hence more pins can be provided on the package. 12.5.4 Available CPLDs A number of CPLDs are available from various manufacturers. These devices are fabricated using CMOS EEPROM fabrication technology. Salient features of ALTERA’s popular families, MAX 3000 A, MAX 7000, and MAX 9000 are given in Table 12.6. Data sheets for these devices and other devices manufactured by other manufacturers can be consulted for details.ri Table 12.6 Features of ALIERA CPLDs ‘Features MAX 3000 A ‘MAX 7000 MAX 9000 Device Family Devite Family Device Family Usable gates {600-10,000 600-5,000 6,000-19, 000 ‘Macrocells. 82.512 32.256 820-560 Logic array blocks 239 216 Maximum user I/O pins (34-208 36-164 168-216 Pin-to-pin logic delay (tpd) ns 45-75 6-12 10-15 Maxinrum counter frequency (fey) MHz 116.3-227.3 909-1754, 118-144 Pin/package options 44-Pin PLCC 44-Pin PLCC 84-Pin PLCC 44-Pin TOFP 44-Pin POFP 205-Pin ROFP 100-Rin TOFP 44-Pin TQFP 240-Pin ROFP 144-Pin TOFP 68-Pin PLCC 280-Pin PGA 208-Pin PQFP 84-Pin PLCC 304-Pin ROFP 256-Rin BGA 100-Pin POFP 356-Pin BGA 400-Pin TOFP 160-Pin PQRP 160-Pin BGA 192-Pin PGA 208-Pin POFP- 208-Pin RQFP ISP via STAG Interface 3.3V operation 5.0 operation avail- available able in S-devices only No.of product terms/macroceli__ 32 32 ‘The programmable logic devices (SPLDs and CPLDs) are based on. similar basic architecture— the programmable array logic, Over the years, programmable arrays have incressed in size and complexity, and highly configurable output macrocells have been added to enhance their flexibility and expandability. To increase the elective size and to add more functionality in a single programmable device, alternative architectures have been developed which are known as field-programmable gate arrays (FPGAs). The logic densities of FPGAs are much higher than those of CPLDs. They range in size from 10,(00 to a few hundreds of thousends equivalent gates, From modem standards digital circuits with hundreds of thousands of gates is not too large. FPGA devices support implementation of relatively large logic circuits. The FPGAs do not contain AND, Of planes, instead they provide logic blocks for implemen- tation of the required digital functions. ‘An FPGA is composed of a number of relatively independent configurable logic modules, configurable 1/O cells, and programmable interconnection paths (known as rouling channel), All the resources of the device are uncomuitted and that these must be selected, configured and interconnected by a user to form a logic circuit for his application. FPGAs differ primarily in the size and configuration of their logic modules and interconnec- tion requirements. FPGAs with larger logic modules may not be sufficiently utilized, therebywasting the logic modules for performing simple logic functions. Use of smaller logic modules leads to much larger number of interconnect paths in the device causing. significant propaga- tion delay as well as consuming large percentage of the FPGA’s area. The optimal logic module size and interconnect requirements are highly dependent on the application that is being implemented in FPGA. For a given FPGA device, there are many possible ways to interconnect the resources required by an application. There are a number of different types of FPGAs available which differ in their architectures, technologies, programming techniques, and packaging. These devices are available in PLCC, QFP, PGA, and BGA packages discussed in Sec, 12.5.3 and are usually programmed using in- system programming (ISP) technique discussed in Sec. 12.5.2. There are a number of manufacturers of FPGAs manufacturing a wide range of products with different features. Some of the major manufacturers of FPGAs are given in Table 12,7. Table 12.7 FPGA manufacturers ‘Manufacturer seme locator ‘Aciel ‘Act 123, MX, 83 hetp://eww actel.com Altera Flex 6000, 8000, 10K, APEX 20K http://wwwaltera.com Atmel ‘At 6000, AT 40K hutp:/vwow.atmel.com Lucent ORCA 1.2, and 3 btp://www.lucent.com Quick Logic pASIC 12, and 3 bitp://www.quicklogic.com Vantis VFI bup://www.vantis.com Xilinx XC 2000, XC 3000, XC 4000, XC 5200, Vitex bup://www.xilinx.com 12.6.1 Logic Cell Array ‘The first family of FPGAs, developed by Xilinx Corporation of America, announced in 1984, is known as logic cell array (LCA) device. It is composed of a number of small programmable logic clements called configurable logic blocks (CLBs). Each CLB contains logic elements and a memory element in the form of a configurable FL1P-FLOP that can be used as a transparent latch or a positive edge-triggered D-type FLIP-FLOP. Special purpose logic cells, called 1/O blocks (IOBs), are arranged around the device, and each can be configured as an input, three- state output or bidirectional 1/O pin. The IOBs can also be configured with FLIP-FLOPs and can also be accessed by the CLBs for non-I/O functions. These configurable cells can be interconnected using the programming routing channel, Figure 19.34 illustrates a portion of the Xilinx XC2064 FPGA device. . The XC2064 LCA device contains 64 CLBs arranged in an 8 x 8 matrix. Each CLB contains a 4input combinational logic section, similar in many respects to a PROM, that is capable of implementing any logic function of up to four variables. In addition, it contains a configurable FLIP-FLOP, internal routing and control circuitry. Figure 12.35 shows a CLB. There are four general purpose inputs, 4, B, Cand D, a special clock input (K), and wo outputs, Xand Y. The delay through the logic cell is constant regardless of the logic function being implemented. The CLB can also be configured for use as two three-input logic functions or for multilevel applica- tions including some 5-input functions. When it is used in four-veriable form, a single-output function is available, ie. F and G outputs of the combinational logic block are same as shown in Fig, 12.36. Two independent output functions Fand G are obtained if used as shown in Fig. 12.37. In this case, both the