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An Accurate Datasheet-Based Full-Characteristics Analytical Model of GaN

HEMTs for Deadtime Optimization

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DOI: 10.1109/TPEL.2020.3044083

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7942 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 7, JULY 2021

An Accurate Datasheet-Based Full-Characteristics

Analytical Model of GaN HEMTs for
Deadtime Optimization
Zhiyuan Qi , Student Member, IEEE, Yunqing Pei , Member, IEEE, Laili Wang , Senior Member, IEEE,
Kangping Wang , Member, IEEE, Mengyu Zhu , Student Member, IEEE, Cheng Zhao , Student Member, IEEE,
Qingshou Yang , Student Member, IEEE, and Yongmei Gan , Member, IEEE

Abstract—The gallium nitride high electron mobility transistors devices have developed to its theoretical limit, it is difficult
(GaN HEMTs) are a superior candidate for the new-generation and almost impossible to further improve the power density
power electronics systems with higher efficiency and power density. and efficiency by using Si devices [1]–[3]. The emergence of
However, due to the unique reverse characteristics, the reverse
voltage drop of GaN HEMTs is much higher than that of diode. The gallium nitride high electron mobility transistors (GaN HEMTs),
deadtime loss in GaN-based bridge converters will be comparable as the representative of wide bandgap power devices, can break
to switching losses if the deadtime is not optimized. To optimize through the bottleneck [4]. Compared with Si and silicon carbide
the deadtime for higher efficiency, this article proposes an accu- (SiC) materials, GaN material has higher electron mobility,
rate analytical model of GaN HEMTs, including circuit’s parasitic higher saturated electron velocity, and higher electric breakdown
inductances, the nonlinear capacitances, the unique reverse char-
acteristics, etc. Taking a GaN-based synchronous buck converter field [5], as shown in Fig. 1. Due to these material superiorities,
as the example, the proposed model is realized, which fully uses the GaN devices can achieve smaller ON-state resistance and smaller
datasheet to avoid additional experiments. In order to accurately gate charge than Si and SiC counterparts with comparable
measure the switching current for validation, a novel parasitics- voltage and current capabilities, which means better conduction
based current measurement method is proposed. The proposed
and switching performance. Therefore, GaN devices are more
model is verified by simulation in LTspice and experiment, and
good agreement is shown. Based on the accurate analytical model, suitable for high frequency applications. By using GaN HEMTs,
the deadtime is optimized for different load currents to improve the switching frequency can be pushed up to multi megahertz
the efficiency within the full load range. Compared with the fixed easily, which is good for the increase of power density.
deadtime of 15 ns, the increase of efficiency can be up to 8%. This However, on the one hand, when operating at such high
work will promote the high-frequency application of GaN HEMTs. switching frequency, the switching losses start to dominate
Index Terms—Analytical model, deadtime optimization, gallium the overall losses and become the limiting factor to further
nitride high electron mobility transistors (GaN HEMTs), increase switching frequency [1], [6]. On the other hand, GaN
parasitics-based current measurement. HEMTs have unique reverse characteristics, which make the
reverse voltage drop of GaN HEMTs much higher than that of
I. INTRODUCTION diode. The deadtime loss in GaN-based bridge converters will be
comparable to switching losses if the deadtime is not optimized.
T IS well acknowledged that high efficiency and high power
I density are two key drivers and metrics for the advancement
of power conversion technologies. For the silicon (Si) power
To have a deep insight into the switching process and optimize
the deadtime for higher efficiency, an accurate model of GaN
HEMTs is highly required.
Basically, there are three types of models, i.e., physics-based
Manuscript received August 25, 2020; revised November 2, 2020; accepted
December 5, 2020. Date of publication December 11, 2020; date of current model, behavior model, and analytical model [7]– [12]. The
version March 5, 2021. This work was supported in part by the Science and Tech- physical model can achieve very close simulation results to
nology Plan of Guangdong Province, China, under Grant 2017B010112002, experimental results, but it is very time-consuming and needs
in part by the Key-Area Research and Development Program of Guangdong
Province, China, under Grants 2020B010173001 and 2020B010170001, and in many parameters related to device fabrication [7], [9], [13], [14].
part by the Power Electronics Science and Education Development Program The widely used model is the behavior model because it has good
of Delta Group under Grant DREG2019007. Recommended for publication by tradeoff between the accuracy and the simulation time. However,
Associate Editor W. Cao. (Corresponding author: Laili Wang.)
The authors are with the State Key Laboratory of Electrical Insulation it is not suitable for massive data processing [9], [13]. Relatively,
and Power Equipment, Xi’an Jiaotong University, Xi’an 710049, China the analytical model is the fastest and suitable for data process-
(e-mail: [email protected]; [email protected]; llwang@mail. ing, but the major challenge to improve the accuracy should
xjtu.edu.cn; [email protected]; [email protected];
[email protected]; [email protected]; ymgan@mail. be addressed. This article will focus on proposing an accurate
xjtu.edu.cn). and rapid analytical model for GaN HEMTs. So far, there have
Color versions of one or more of the figures in this article are available online been some analytical models of GaN HEMTs presented [3],
at https://doi.org/10.1109/TPEL.2020.3044083.
Digital Object Identifier 10.1109/TPEL.2020.3044083 [6], [15]–[17], but most of them are modified from the models

0885-8993 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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QI et al.: ACCURATE DATASHEET-BASED FULL-CHARACTERISTICS ANALYTICAL MODEL OF GaN HEMTs 7943

be comparable to switching losses if the deadtime is not opti-

mized. Therefore, the deadtime needs to be optimized for higher
efficiency by considering the unique reverse characteristics of
GaN HEMTs. Besides, either a constant transconductance or
only the transfer characteristics in datasheet is conventionally
used to model the I-V characteristics of GaN HEMTs, affecting
the accurate prediction of the switching process. To improve
the accuracy, both the transfer characteristics and the output
characteristics need to be used to model the I-V characteristics.
According to the above analysis, this article will fully use the
datasheet to model the I-V characteristics and C-V characteristics
of GaN HEMTs without any additional experiments, and further
propose an accurate analytical model of GaN HEMTs, includ-
ing circuit’s parasitic inductances, the nonlinear capacitances,
Fig. 1. Comparison of Si, GaN, and SiC properties. the unique reverse characteristics, etc. Based on the proposed
model, the deadtime will be optimized to improve efficiency by
revealing the impact of deadtime on power losses. The rest of
this article is organized as follows. In Section II, the device-level
modeling process of GaN HEMTs is described in detail. Based
on the device-level model, detailed circuit-level model is built
in Section III, the switching process is discussed in depth by
dividing it into four phases. In Section IV, a parasitics-based
current measurement method is proposed, and the verification
of the proposed model is carried out by simulation and experi-
ment. Then, based on the presented model, the power losses are
decomposed. In Section V, in order to improve the efficiency,
Fig. 2. Equivalent circuit schematic of GaN HEMTs’ device-level model. the deadtime is optimized for different load currents. Finally, in
Section VI, the conclusion and the next working plan are given
out.
of MOSFETs [12], [13], [18]–[31], which are not suitable for
GaN HEMTs. In order to realize an accurate analytical model II. DEVICE-LEVEL MODELING OF GAN HEMTS
of GaN HEMTs, circuit’s parasitic inductances, the nonlinear
The modeling process in this article is divided into two steps,
capacitances, and the unique reverse characteristics of GaN
i.e., the device-level model of GaN HEMTs and the circuit-level
HEMTs should be considered [9].
model. In this section, the device-level model of GaN HEMTs is
However, in the existing analytical models of GaN HEMTs,
presented in detail. Fig. 2 shows the schematic of GaN HEMTs’
the nonlinear capacitances are usually achieved directly from
device-level model. It can be seen that there are no differences
datasheet, which cannot reflect the real nonlinearity of the para-
between the model of GaN HEMTs and Si MOSFET from the as-
sitic capacitances. It is because of the gate-to-source capacitance
pect of the schematic. In the model, there are three nonlinear ca-
of GaN HEMTs being strongly affected by gate-to-source volt-
pacitances, i.e., gate-source capacitance CGS (vGS ), gate-drain
age, but the nonlinear capacitances in datasheet are with regard
capacitance CGD (vGD ), drain-source capacitance CDS (vDS ),
to drain-to-source voltage. In order to achieve the nonlinearity of
and a voltage-controlled current source ich (vG , vD , vS ) repre-
gate-to-source capacitance with regard to gate-to-source voltage,
senting channel current. But, the I-V characteristics and C-V
some additional experiments are conventionally needed [32],
characteristics of GaN HEMTs are quite different from Si MOS-
which is not expected for engineers and designers. To avoid
FETs, which will be carefully modeled below. The GaN HEMTs
additional experiments, the datasheet needs to be fully used.
EPC2015C is taken as the example to demonstrate the modeling
Besides the curve of nonlinear capacitances in datasheet, the
process. The technique of extracting image data and curve fitting
curve of gate charge can also be used, and then some derivations
is used to fully extract the information of datasheet, and some
are required. For simplification, a Schottky diode is usually
derivations are carried out to achieve the accurate analytical
used to replace the synchronous switch in the existing analytical
model of GaN HEMTs without any additional experimental
models of GaN HEMTs [3], [6]. But actually, GaN HEMTs
measurements.
have unique reverse characteristics as mentioned above. When
operating reversely, GaN HEMTs are controlled by gate-to-drain
A. Modeling of GaN HEMTs’ I-V Characteristics
voltage instead of gate-to-source voltage. However, the driving
signal is usually applied between gate terminal and source As mentioned above, the reverse characteristics of GaN
terminal. During the deadtime, GaN HEMTs operate at weak HEMTs are unique, which means different I-V characteristics
active region, resulting in a higher reverse voltage drop than the from power MOSFETs. For power MOSFETs, as long as the value
voltage drop of diode. The power losses during deadtime can of the gate-to-source voltage is higher than threshold voltage,

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7944 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 7, JULY 2021

Fig. 3. Fitted curves of EPC2015C’s I-V characteristics (solid line: curves Fig. 4. (a) Fitted curves of CISS , COSS , and CRSS versus vDS (solid line:
from datasheet, dash line: fitted curves). (a) Transfer characteristics. (b) Output curves from datasheet, dash line: fitted curves). (b) Derived curves of CGS , CDS,
characteristics. and CGD versus vDS .

the channel will conduct current no matter the drain-to-source

HEMTs fully conduct and locate in the forward ohmic region,
voltage is positive or negative. For the GaN HEMTs, it has a
the output characteristics curve is used to obtain f2 (vGS , vDS ).
symmetrical structure, which can be regarded as a parallel-pair
By using linear lowess fitting method with a span of 1%, the
of two power MOSFETs in opposite directions [33]. When drain-
output characteristics curve is well fitted, as shown in Fig. 3(b),
to-source voltage is positive, the channel current is controlled
and the obtained fitting function is f2 (vGS , vDS ). As afore-
by gate-to-source voltage; but when drain-to-source voltage
mentioned, GaN HEMTs have symmetrical structure, and thus
is negative, the channel current is controlled by gate-to-drain
symmetrical working characteristics. Therefore, f3 (vGD ) and
voltage. This results in the unique reverse characteristics of GaN
f4 (vGD , −vDS ) can be achieved just by changing vGS and vDS
HEMTs, which has great influence on the power loss during
in f1 (vGS ) and f2 (vGS , vDS ) to vGD and−vDS .
deadtime between top switch and bottom switch in half-bridge
circuit.
The same as power MOSFETs, the operation of GaN HEMTs B. Modeling of GaN HEMTs’ C-V Characteristics
can also be divided into three regions under the positive drain- An accurate modeling of C-V characteristics can precisely
to-source voltage or negative drain-to-source voltage, i.e., cutoff describe the dynamic behavior of GaN HEMTs, thus can achieve
region, active region, and ohmic region. Conventionally, the a precise description of the switching process. Generally, the
cutoff region is treated as an ideal OFF-state without any current datasheet just gives out the curves of input capacitance CISS ,
flowing through, and the ohmic region is treated as the absolute output capacitance COSS , and reverse capacitance CRSS with
ON-state without voltage drop across drain and source terminals. regard to vDS , which can be obtained by curve fitting, as shown
Besides, a constant transconductance is often used to describe in Fig. 4(a). By using (2)–(4), the curves of CGS , CGD, and CDS
the dependence of channel current on gate-to-source voltage in with regard to vDS are achieved, as shown in Fig. 4(b). It can be
active region. In this article, no assumption for simplification is seen that the derived CGS is almost constant versus vDS , that is
made, the output characteristics and transfer characteristics are why it is usually treated as a constant in conventional analytical
both used into the modeling of the I-V characteristics. models [6], [12], [13], [22], [26], [27], [32]. However, the fact is
The I-V characteristics reflecting the steady behavior of GaN that the three interelectrode capacitances are just related to their
HEMTs can be described by (1) as follows: respective applied voltage. For example, CGS is related to vGS
⎧ strongly [7], [19], [34]–[41], CGD and CDS are actually related to
⎪ f1 (vGS ) , if vDS > vGS − vth ≥ 0
⎪
⎪
⎪
⎪ or vDS > 0 > vGS − vth vGD and vDS , respectively. What is more, as the structure of GaN
⎪
⎨ HEMTs is symmetrical, so the three nonlinear capacitances are
f2 (vGS , vDS ) , if vGS − vth > vDS ≥ 0
ich = (1) also symmetrical with regard to their respective voltage. In order
⎪
⎪ −f3 (vGD ) , if − vDS > vGD − vth ≥ 0
⎪
⎪ to achieve accurate model of C-V characteristics, the datasheet
⎪
⎪ or − vDS > 0 > vGD − vth
⎩ needs to be fully used, and some derivations are necessary.
−f4 (vGD , −vDS ) , if vGD − vth > −vDS > 0
where vGS , vGD , vDS , and vth are the gate-to-source volt- CISS = CGS + CGD (2)
age, gate-to-drain voltage, drain-to-source voltage, and thresh-
old voltage, respectively. f1 (vGS ), f2 (vGS , vDS ), f3 (vGD ), and CRSS = CGD (3)
f4 (vGD , −vDS ) are the functions of channel current in different COSS = CDS + CGD (4)
regions.
With regard to the function f1 (vGS ), since vDS > vGS − With regard to the nonlinear capacitance CDS (vDS ), it can be
vth ≥ 0 or vDS > 0 > vGS − vth , it means that the GaN HEMTs obtained by simply subtracting (3) from (4). For the nonlinear
operate in forward active region or forward cutoff region. Hence, capacitance CGD (vGD ), as the measurement of C-V curves
the transfer characteristics curve is used to obtain f1 (vGS ). in datasheet is under the condition of vGS = 0 V [42], so
The transfer characteristics curve can be well fitted by using vDS = vDG , thus CGD (vGD ) can also be obtained. For the
linear-interpolant method, as shown in Fig. 3(a), and the obtained nonlinear capacitance CGS (vGS ), it cannot be obtained directly
fitting function is f1 (vGS ). When vGS − vth > vDS ≥ 0, GaN from the C-V curves in datasheet. Therefore, this article also

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QI et al.: ACCURATE DATASHEET-BASED FULL-CHARACTERISTICS ANALYTICAL MODEL OF GaN HEMTs 7945

TABLE I
SPECIFICATIONS OF THE SYNCHRONOUS BUCK CONVERTER

Fig. 5. Derivation of CGS − vGS curve from the vGS − QG curve in datasheet.
(a) The vGS - QG curve. (b) The derived CGS - vGS curve.

uses the QG -vGS curve in datasheet into the derivation of vGS -

dependent CGS . It should be noted that the curve of QG -vGS
reflects the turn-ON process of GaN HEMTs. With the driving
current flowing into the gate terminal of GaN HEMTs, CGS
charges and CGD discharges, thus the gate-to-source voltage
rises. There is no current flowing through the channel until vGS is
higher than threshold voltage vth , then the channel current rises
continuously until the current of output inductor. During this
current-increasing period, vDS remains to be 20 V, CGS (vGS )
during this range can be obtained from (5). Then, it starts to
enter the voltage-decreasing stage when vGS remains constant,
which is so-called Miller platform. During this stage, CGS keeps
constant. After that, when vDS drops to smaller than vGS− vth ,
GaN HEMTs fully conducts and locates in ohmic zone, and
CGS (vGS ) can be calculated by using (6). Based on the above
method, the curve of CGS− vGS is obtained as shown in Fig. 5. It
can be seen that there is a sudden change at the Miller platform
voltage vpl , which exactly verifies why CGS cannot be treated as
a constant. Through the above process, an accurate device-level
model of GaN HEMTs is built.
dQG dQGS dQGD dQGS dQGD
= + = +
dvGS dvGS dvGS dvGS d (vGD + 20)
dQGS dQGD
= + = CGS (vGS ) + CGD (20 − vGS )
dvGS dvGD
(5)
Fig. 6. (a) Schematic of synchronous buck converter with main parasitic
dQG dQGS dQGD inductances. (b) Schematic of the obtained circuit-level model.
= +
dvGS dvGS dvGS
dQGS dQGD
≈ + = CGS (vGS ) + CGD (vGD ) . (6) including Lin , LG1 , LD1 , LS1 , LG2 , LD2 , and LS2 . By substi-
dvGS dvGD tuting the device model of GaN HEMTs into the circuit, the
circuit-level model can be obtained as shown in Fig. 6(b). The
power loop inductance Lloop is the sum of LD1 , LS1 , LD2 , and
III. CIRCUIT-LEVEL MODELING OF GAN HEMTS BASED ON A LS2 . In the model, LS1 and LS2 are replaced by LS , which is about
SYNCHRONOUS BUCK CONVERTER
80 pH [43]. Considering the actual current of load inductor in
Based on the built device-level model of GaN HEMTs, this synchronous buck converter, the current of load inductor IL is
section takes a GaN-based synchronous buck converter as the modeled as a current source with triangle waveform as shown
example to derive the circuit-level model. The specifications of in Fig. 7.
the synchronous buck converter are shown in Table I. In order Then, based on the Kirchhoff voltage law and Kirchhoff
to describe the switching behavior of GaN HEMTs as actually current law, the voltage equations and current equations of both
as possible, the decoupling capacitors Cin and almost all the the power loop and two driving loops can be derived for the
related parasitic inductances are considered into circuit-level circuit-level model, as listed in (7)–(16). The variables used in
model. Vdc represents the voltage of the input filter capacitors, the model are defined in Table II. There are ten state variables
which is almost constant. Fig. 6 (a) shows the schematic of the and ten equations in the model, so the unique solution exists.
synchronous buck converter with main parasitic inductances, However, since the interelectrode capacitances are nonlinear

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7946 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 7, JULY 2021

Fig. 7. Current waveform of load inductor.

TABLE II
DEFINITIONS OF CIRCUIT PARAMETERS IN PROPOSED MODEL

Fig. 8. Schematic of main waveforms during a switching period.

diG2 diDS2
VG2 = vGS2 + RG2 iG2 + (LG2 + LS ) + Ls
dt dt
(11)
dvGS2 dvDS2
iG2 = CISS2 · − CGD2 · (12)
dt dt
dvDS2 dvGS2
iDS2 = ich2 + COSS2 · − CGD2 · (13)
dt dt
IL = iDS1 − iDS2 (14)
diin
Vdc = vin + Lin (15)
dt
dvin
iin = iDS1 + Cin · . (16)
dt
about their respective applied voltage, the algebraic solution
cannot be obtained. The iteration calculation method is required For ease of solving the proposed model, (7)–(16) are rear-
to solve the proposed analytical model. What is more, solving ranged into the form of (17) as follows:
the power electronics problems is often a stiff problem, so the dX
= AX + B (17)
ode15s function in MATLAB is employed to solve the stiff dt
model.
where X = [vGS1 iG1 vGS2 iG2 vDS1 vDS2 iDS1 iDS2 iin vin ]T , A
diG1 diDS1 and B are given in the Appendix.
VG1 = vGS1 + RG1 iG1 + (LG1 + LS ) + LS
dt dt In order to calculate the proposed analytical model, the initial
(7) state should be set carefully. As the synchronous buck converter
is taken as the example in this article, so this article sets the
dvGS1 dvGD1
iG1 = CGS1 · + CGD1 · ON state of bottom switch as the initial state which can help
dt dt
to improve the accuracy of calculation. At the initial state,
dvGS1 dvDS1 the bottom switch Q2 fully conducts the current from source
= CISS1 · − CGD1 · (8)
dt dt terminal to drain terminal, and vDS2 is negative. At this time,
dvDS1 dvGD1 ich2 is actually controlled by vGD2 . Then, as shown in Fig. 8,
iDS1 = ich1 + CDS1 · − CGD1 · this article divides a full switching period into four phases for
dt dt
dvDS1 dvGS1 calculation, i.e., the deadtime phase before top switch turning ON
= ich1 + COSS1 · − CGD1 · (9) (from t1 to t2 ), the top switch turning-ON and conducting phase
dt dt
  (from t2 to t3 ), top switch turning-OFF phase (from t3 to t4 ),
diG1 diG2 and the bottom switch turning-ON and conducting phase (from
vin = vDS1 + vDS2 + Rloop iDS1 + LS +
dt dt t4 to t5 ). According to the calculation process shown in Fig. 9,
diDS1 the four subprocesses are calculated in turn, during which each
+ Lloop (10) phase starts at the end state of the previous phase.
dt

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QI et al.: ACCURATE DATASHEET-BASED FULL-CHARACTERISTICS ANALYTICAL MODEL OF GaN HEMTs 7947

the −iDS2 causes the difference iDS2 − ich2 , which discharges

COSS2 reversely. Then, −vDS2 and vGD2 decrease, and −ich2
decreases accordingly. With the further increase of vGS1 , when
it increases to a value that makes the current iDS1 reach to IL , it
means that IL is completely commutated from Q2 to Q1 . But the
increase of iDS1 still continues, and the difference iDS1 − IL will
charge COSS2 to increase vDS2 . Meanwhile, as vGS1 increases,
vDS1 decreases due to the discharge of COSS1 by ich1 − iDS1 .
When vDS1 is close to zero, the top switch Q1 is fully turned
ON. After that, the parasitic inductance of power loop Lloop will
resonate with COSS2 to result in the current oscillation of Q1 and
voltage oscillation of Q2 . With the arrival of turn-OFF signal of
Q1 at t3 , this phase ends.

C. Phase III: Top Switch Turning-off Phase

This phase starts with the arrival of top switch’s turn-OFF
signal at t3 , and vGS1 starts to fall down. With the decrease of
vGS1 , ich1 decreases. Due to the presence of parasitic inductance,
iDS1 does not change immediately, the difference iDS1 − ich1 will
charge COSS1 to increase vDS1 . Then, a voltage across parasitic
inductance is caused to reduce iDS1 , thus a reverse current
Fig. 9. Calculation process of the proposed analytical model of GaN HEMTs. through bottom switch −iDS2 increases due to the relationship
−iDS2 = −(iDS1 − IL ). Generally, the turn-ON signal of Q2 is not
A. Phase I: Deadtime Phase Before Top Switch Turning on applied before Q1 is completely turned OFF. Therefore, −iDS2
is used to discharge COSS2 , which reduces vDS2 . For Q1 , it will
The arrival of bottom switch’s turn-OFF signal at t1 indicates
turn into the active region from ohmic region when vGS1 − vth <
the start of this phase. And vGS2 decreases as VG2 drops from 5
= vDS1 , and the channel will be turned OFF when vGS1 < vth . For
to 0 V. At the beginning, Q2 is still fully ON, −vDS2 is negligible,
Q2 , vDS2 will reduce to zero and then increase reversely. Since
so vGD2 is approximately equal to vGS2 , and decreases with the
vGS2 is zero, vGD2 is approximately to −vDS2 , it increases with
decrease of vGS2 , so does −ich2 . Due to the presence of parasitic
the reverse charge of COSS2 . When vGD2 > = vth , the channel
inductance, iDS2 does not change immediately, the difference
of Q2 is turned ON. The reverse charging process will continue
ich2 − iDS2 will charge COSS2 reversely to increase −vDS2 . The
until vGD2 reaches to an enough high value so that the current
decrease of vGD2 and the increase of −vDS2 will result in the
−iDS2 can absolutely flow through the channel. Accordingly,
relationship vGD2 − vth < = −vDS2 , which means Q2 starts to
the source-to-drain voltage −vDS2 does not increase any more.
operate at the active region. When vGS2 drops to almost zero,
As Q2 is operating at the weak active region, −vDS2 is usually
vGD2 is equal to −vDS2 , and −vDS2 does not increase any more.
much higher than the voltage drop of diode. When the turn-ON
This process will last till the turn-ON signal of top switch arrives.
signal of Q2 comes at t4 , this phase ends. The duration of this
During this process from t1 to t2 , the value of −vDS2 is related to
phase t4 − t3 is another deadtime td2 , which also needs to be
the channel current, and is usually much higher than the voltage
carefully optimized.
drop of diode. For the GaN HEMTs EPC2015C operating at 10
A, the value of −vDS2 is about 2.16 V. It will bring a large power
loss during this phase, which is called the deadtime loss before D. Phase IV: Bottom Switch Turning-on and Conducting
top switch turns ON. Therefore, the deadtime td1 = t2 − t1 needs Phase
to be carefully optimized.
When the turn-ON signal of Q2 arrives at t4 , the turn-ON
process of Q2 starts. With the increase of vGS2 , vGD2 = vGS2 +
B. Phase II: Top Switch Turning-on and Conducting Phase
vSD2 increases, then ich2 increases, which will be larger than
At the time t2 , the turn-ON signal of top switch Q1 comes, −iDS2 . The extra current will discharge COSS2 reversely to
and this stage starts. Due to the excitation of driving voltage leading Q2 from active region into ohmic region. When −vDS2 is
VG1 jumping from 0 to 5 V, vGS1 will increase. When vGS1 close to zero, Q2 is fully turned ON. Then the parasitic inductance
increases to higher than vth , the channel of Q1 is turned ON of power loop Lloop will resonate with COSS1 to cause the
and starts to conducts current. As vGS1 increases, ich1 increases. oscillation of waveform. This phase ends with the arrival of
Because of the presence of parasitic inductance, iDS1 does not bottom switch’s turn-OFF signal at t5 .
change immediately. The current difference ich1 − iDS1 will Through the calculation process shown in Fig. 9, the proposed
discharge COSS1 , which leads to the decrease of vDS1 and model can be calculated accurately by using MATLAB, thus
further the increase of iDS1 . Then, −iDS2 will decrease due to the switching waveforms during a full switching period can be
the relationship of −iDS2 = − (iDS1 − IL ). The decrease of obtained.

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7948 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 7, JULY 2021

Fig. 10. Simulation model in Ansys Q3D Extractor.

Fig. 11. Switching waveforms comparison between the proposed model and
TABLE III LTspice at the load current of 5 A (solid line: proposed model, dotted line:
EXTRACTION OF THE CIRCUIT’S PARASITIC INDUCTANCES LTspice). (a) Phase I and phase II. (b) Phase III and phase IV.

Fig. 12. Schematic of synchronous buck converter with sensing trace.

IV. VERIFICATION AND DISCUSSIONS OF THE PROPOSED
ANALYTICAL MODEL
In this section, the proposed analytical model of GaN HEMTs
will be verified. Before this, the parasitic inductances need to
be extracted for simulating the actual circuit. Therefore, Ansys
Q3D Extractor was utilized to extract the parasitic inductances.
In order to achieve accurate parasitic inductances, the simulation
model was obtained by first exporting the actual layout of
printed circuit board (PCB) in Altium Designer to the specific
format of ODB++, and then using Ansys SIwave to convert
the ODB++ files to the files readable by Q3D Extractor, as
Fig. 13. Designed sensing trace for current measurement in PCB.
shown in Fig. 10. The simulation frequency was set to 100
MHz representing high frequency oscillation, then the parasitic
inductances were extracted as listed in Table III. As mentioned the simulation waveforms by the proposed model are consistent
above, the common source inductance LS of EPC2015C is about with the simulation waveforms by LTspice.
80 pH. The decoupling capacitor Cin is 0.3 uF, consisting of three
0.1 uF ceramic capacitors in parallel. With the extracted parasitic B. Parasitics-Based Current Measurement Method
inductances, the switching process during a full switching period In order to measure the switching currents accurately in
can be accurately calculated by using the proposed analytical experimental verification, a novel high-bandwidth current mea-
model. surement method based on the parasitics of PCB’s trace was
proposed. As shown in Figs. 12 and 13, the trace from the source
A. Simulation Verification by LTspice terminal of Q2 to the ground terminal of decoupling capacitors
LTspice is widely used for the simulation of power electronics was used as the sensing trace, whose parasitic inductance is
circuits, the behavior model used in LTspice can achieve very Lsense , and parasitic resistance is Rsense . The mutual inductance
close results to experiment. Hence, the simulation verification between the sensing trace and the rest trace in power loop is M.
by LTspice was firstly carried out, in which the device model The current through the sensing trace is the iDS1 , and it exists
of EPC2015C is provided by manufacturer. The load current is the following relationship between iDS1 and the voltage across
5 A, and the deadtimes td1 and td2 are both set to 30 ns. The the sensing trace vsense .
simulation results by the proposed model are compared with diDS1
the simulation results by LTspice in Fig. 11. We can see that vsense = Rsense iDS1 + (Lsense − M ) . (18)
dt

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QI et al.: ACCURATE DATASHEET-BASED FULL-CHARACTERISTICS ANALYTICAL MODEL OF GaN HEMTs 7949

Fig. 14. Extracted parasitics of sensing trace by Ansys Q3D Extractor.

Fig. 15. Verification of the proposed parasitics-based current measurement
method by LTspice.

The key is to derive the switching current iDS1 and iDS2 from
the measured vsense in . As we know, a periodic function can
be represented by an infinite series of sine and cosine functions,
which is the so-called Fourier series. Hence, iDS1 can be written
as
∞
iDS1 = I0 + Ik sin (kωt + ϕk ) (19)
k=1

where ω = 2πf and f is the switching frequency.

By using (18), vsense can be written as
∞

vsense = R0 I0 + Rk Ik sin (kωt + ϕk ) Fig. 16. (a) Experiment setup for validating the proposed analytical model.
(b) 12-3.3 V synchronous buck converter.
k =1
∞

+ kωLk Ik cos (kωt + ϕk )
k =1
∞

= R0 I 0 + Zk Ik sin (kωt + ϕk + ϕz ) (20)
k =1

where Rk = Rsense (kf ), Lk = Lsense (kf ) − M (kf ), Zk =

Rk 2 + (kωLk )2 ,and ϕz = atan( kωL k
Rk ).
Fig. 17. Measured waveforms at different load current. (a) 2A. (b) 10A.
From (19) and (20), iDS1 can be derived from the measured
vsense , and thus iDS2 = IL − iDS1 can be obtained. In order
The converter operates at the switching frequency of 1 MHz.
to obtain the frequency-dependent Rk and Lk , the frequency
The PWM signals for gate driver LM5113 are generated by DSP
characteristics of Lsense , Rsense , and M were extracted by using
TMS320F28335, the deadtimes td1 and td2 are both set to about
Ansys Q3D Extractor, as shown in Fig. 14. The proposed current
30 ns. The 1-GHz high-bandwidth oscilloscope MSO64 6-BW-
measurement method was verified by simulation in LTspice.
1000A and passive voltage probe TPP1000 from Tektronix were
From Fig. 15, we can see that it shows good agreement between
used to accurately measure the switching waveforms.
the derived current and the current by simulation. Benefitting
Through the experiment, the waveforms of vDS1 , vDS2 , and
from the consideration of the frequency characteristics of sens-
vsense at the load current of 2 and 10 A were measured, as
ing trace, the proposed parasitics-based current measurement
shown in Fig. 17. Based on the proposed current measurement
can realize very high bandwidth, which is very suitable for the
method, iDS1 and iDS2 were derived from the measured vsense .
measurement of high frequency switching current.
Then, the experimental waveforms of vDS1 , vDS2 , iDS1 , and
iDS2 were replotted in Figs. 18 and 19 to be compared with
C. Experimental Verification the switching waveforms by the proposed model. Benefitting
In order to verify the proposed analytical model of GaN from the consideration of the nonlinear capacitances and the
HEMTs, an experimental protype of 12-3.3 V synchronous buck unique reverse characteristics of GaN HEMTs, and almost all
converter based on EPC2015C was built, as shown in Fig. 16. the parasitic inductances of circuit into the proposed analytical

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7950 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 7, JULY 2021

Fig. 18. Switching waveforms comparison between the proposed model and
experiment at the load current of 2 A (solid line: proposed model, dotted line:
experiment). (a) Phase I and II. (b) Phase III and IV.

Fig. 20. Derived channel currents by the proposed model at the load current
of 15 A. (a) Phase I and II. (b) Phase III and IV.

Fig. 19. Switching waveforms comparison between the proposed model and
experiment at the load current of 10 A (solid line: proposed model, dotted line:
experiment). (a) Phase I and II. (b) Phase III and IV. Fig. 21. Decomposition of power losses related to GaN HEMTs.

widely used for calculation power losses of switching devices.

model, the simulation results during the full switching period
show good agreement with the experimental results. The error
Ploss = f · iDS · vDS dt (21)
between the simulation results and experimental results can be
attributed to the following two reasons. First, the experimental
results are highly related to the designed measuring points, the Ploss = f · ich · vDS dt. (22)
complicated parasitics in actual circuit can have great influence
on the measurement results. Second, the temperature effect In this article, the channel current can be calculated accurately,
was not considered in the proposed analytical model, while the as shown in Fig. 20, so the power losses of switching devices can
junction temperature has serious and complex influence on the be accurately evaluated by using (22). Based on the proposed
operation of switching devices. Nevertheless, the accuracy of the model, power losses of top switch and bottom switch are calcu-
proposed analytical model of GaN HEMTs was verified, thus lated at the load current of 10 A, including the turn-ON loss of
we can have accurate evaluation of the power losses. top switch Pon1 , conduction loss of top switch Pcon1 , turn-OFF
loss of top switch Poff1 , turn-ON loss of bottom switch Pon2 ,
conduction loss of bottom switch Pcon2 , turn-OFF loss of bottom
D. Decomposition of Power Losses Based on the Proposed
switch Poff2 , deadtime loss before top switch turning ON Pd1 ,
Analytical Model and the deadtime loss after top switch turning OFF Pd2 . Then,
Conventionally, the power losses of switching devices are the calculated power losses are plotted in Fig. 21, which shows
calculated by integrating the product of drain-to-source voltage that the deadtime losses Pd1 and Pd2 are 0.2361 and 0.2686 W,
and drain current, as shown in (21). It is not quite exact due to respectively, accounting for significant proportions of the total
the presence of the output capacitance. It is more accurate by power loss (19% and 22%, respectively). Therefore, it is very
using (22) to calculate the power losses of switching devices. necessary to optimize the deadtimes to reduce deadtime losses
As the channel current is usually unmeasurable, so (21) is still and improve efficiency.

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QI et al.: ACCURATE DATASHEET-BASED FULL-CHARACTERISTICS ANALYTICAL MODEL OF GaN HEMTs 7951

Fig. 22. Effects of deadtime td1 and td2 on power losses at the load current Fig. 23. Effects of deadtime td1 and td2 on power losses at the load current
of 10 A. a) The effects of deadtime td1 . (b) The effects of deadtime td2 . of 1 A. (a) The effects of deadtime td1 . (b) The effects of deadtime td2 .

V. OPTIMIZATION OF DEADTIME
As mentioned above, due to the large reverse voltage of
GaN HEMTs, the power losses during deadtime can account
for significant proportions in the total power loss. It is very
important to optimize the deadtime for higher efficiency. The
two aforementioned deadtimes td1 and td2 can not only affect
the deadtime losses, but also affect the other losses. Moreover,
different load currents can have great impact on the selection
of the deadtime because different load currents make different Fig. 24. Curve of optimal deadtime tod1 and tod2 versus load current IO .
voltage changing rate during the switching transient. If the (a) tod1 vs. IO . (b) tod2 vs. IO .
deadtime is too large, it can cause significant power loss during
deadtime. If the deadtime is too short, it may cause short-through comes, so Pon2 is smaller. If vDS2 is zero when the turn-ON signal
between top switch and bottom switch, which can also result in of bottom switch comes, Pon2 is smallest. The value of td2 is
large power loss. Therefore, based on the proposed model, this optimal. If we increase td2 further, vDS2 will turn to negative
section focuses on the optimization of the deadtime with the before the turn-ON signal comes, Pon2 will increase slightly.
consideration of the load current’s effect. When −vDS2 is high enough to make IL flow through the channel
It can be easily understood that the deadtime td1 only affects absolutely, the continuous increase of td2 will no longer increase
Pd1 , Pon1 , and Poff2 , while td2 only affects Pd2 , Poff1 , and Pon2 . Pon2 . As for Poff1 , it is not affected by td2 . The result is that
Fig. 22 shows the effects of td1 and td2 on power losses at the load there is an optimal td2 to make the sum of Pd2 , Poff1 , and Pon2
current of 10 A. From Fig. 22(a), we can see that Pd1 increases minimum.
as td1 increases while Pon1 and Poff2 have an oscillation with
the increase of td1 . The frequency of the oscillation is related to Vdc (1 − D) DT
Ilimit = ≈ 1.2 A. (23)
the resonance between parasitic inductance Lloop and the output LO
capacitance of GaN HEMTs COSS . Overall, the effect of td1 on
Ptotal1 , i.e., the sum of Pd1 , Pon1 , and Poff2 , is mainly decided According to the above analysis, td1 should be as short as
by Pd1 , and in direct proportion to td1 . However, if the load possible if IO is higher than Ilimit . In this article, td1 is set to 3 ns
current IO is smaller than a value Ilimit , as shown in (23), IL will if IO is higher than Ilimit . But if IO is lower than Ilimit , there is an
have negative value and flow through Q1 reversely to discharge optimal td1 . The effect of td1 under different load currents below
COSS1 , which reduces vDS1 before Q1 is turned ON, so Pon1 is Ilimit is investigated, the optimal values of td1 under different
reduced. With the increase of td1 , Pon1 gets smaller, so does currents below Ilimit are obtained as shown in Fig. 24(a). The
Ptotal1 . When vDS1 reduces to zero, the ZVS of Q1 is achieved, smaller IO makes larger negative peak of IL to accelerate the
and the continuous increase of td1 will charge COSS1 reversely discharge of COSS1 , so the required optimal deadtime tod1 is
to increase −vDS1 , so Pon1 and Ptotal1 are increased, the td1 smaller. As for td2 , the optimal value exists within full load range,
when vDS1 is zero is the optimal, as shown in Fig. 23(a). From so the effect of td2 under different load currents is also inves-
Figs. 22(b) and 23(b), we can see that with the increase of td2 , gated, the optimal values of td2 under different load currents are
Pd2 does not change at the beginning until a value after which obtained in Fig. 24(b). Since larger IO charges or discharges the
it increases almost linearly. With regard to Pon2 , it decreases output capacitance faster, the optimal deadtime tod2 is smaller
at beginning until a value after which it starts to increase, and with the increase of IO . Then, the comparison between the
then turns to flat. There is an optimal deadtime of td2 to realize optimized deadtime and the fixed deadtime is conducted, td1
minimum Pon2 . It can be explained as follows. If td2 is too and td2 are both fixed to 5, 10, and 15 ns, respectively. As shown
small, the turn-ON signal of bottom switch will arrive before top in Fig. 25, through the optimization control of td1 and td2 under
switch is turned OFF. Since vDS2 is still positive, a large channel different load currents, the efficiency within full load range can
current will be caused, which increases Pon2 . With the increase be improved obviously. Compared with the fixed deadtime of
of td2 , vDS2 is smaller when the turn-ON signal of bottom switch 15 ns, the increase of efficiency can be up to 8%.

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7952 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 7, JULY 2021

where
COSS1
a1 = (A4)
CISS1 · COSS1 − CGD1 2
CGD1
a2 = (A5)
CISS1 · COSS1 − CGD1 2
a3 =
 
− (LG2 + LS ) Lloop − LS 2
Fig. 25. Comparison of efficiency between the optimized deadtime and fixed (LG1 + LS ) (LG2 + LS ) Lloop − LS 2 (LG1 + LG2 + 2LS )
deadtime. (a) IO < Ilimit . (b) IO > Ilimit . (A6)
a4 = RG1 a3 (A7)
VI. CONCLUSION
a5 = a13
In order to optimize the deadtime for higher efficiency, this
article proposes an accurate analytical model of GaN HEMTs, −LS 2
=
including circuit’s parasitic inductances, the nonlinear capac- (LG1 + LS ) (LG2 + LS ) Lloop − LS 2 (LG1 + LG2 + 2LS )
itances, the unique reverse characteristics, etc. The proposed (A8)
analytical model fully uses the datasheet to avoid additional
experiments. A 12-3.3 V synchronous buck converter based a6 = RG2 a5 (A9)
on EPC2015C is taken as the example to build the analytical a7 = a8
model. The proposed model is first verified by simulation in
LTspice. For experimental verification, a novel parasitics-based LS (LG2 + LS )
=
current measurement method is proposed, which is verified by (LG1 + LS ) (LG2 + LS ) Lloop − LS 2 (LG1 + LG2 + 2LS )
simulation in LTspice. Then, the proposed analytical model of (A10)
GaN HEMTs is verified by experiments, and good agreement
is demonstrated. Based on the accurate analytical model, the a9 = Rloop a7 (A11)
deadtimes are optimized for different load currents to improve a10 = −a7 (A12)
the efficiency within the full load range. Compared with the fixed
COSS2
deadtime of 15 ns, the increase of efficiency can be up to 8%. In a11 = (A13)
the future work, on the basis of the proposed analytical model CISS2 · COSS2 − CGD2 2
of GaN HEMTs in this article, we will investigate the effects CGD2
a12 = (A14)
of circuit’s parasitic inductances and driving resistances on the CISS2 · COSS2 − CGD2 2
switching losses and voltage overshoot, to provide guidance for
engineers to optimize the circuit’s parameters. a14 = RG1 a13 (A15)
a15
APPENDIX  
− (LG1 + LS ) Lloop − LS 2
As mentioned in Section III, the circuit-level model is written =
(LG1 + LS ) (LG2 + LS ) Lloop − LS 2 (LG1 + LG2 + 2LS )
into the form of the state-space equation
(A16)
dX
= AX + B (A1) a16 = RG2 a15 (A17)
dt
a17 = a18
where X = [vGS1 iG1 vGS2 iG2 vDS1 vDS2 iDS1 iDS2 iin vin ]T .
According to (7)–(16) LS (LG1 + LS )
⎡ ⎤ =
0 a1 0 0 0 0 a2 0 0 0 (LG1 + LS ) (LG2 + LS ) Lloop − LS 2 (LG1 + LG2 + 2LS )
⎢ a3 a4 a5 a6 a7 a8 a9 0 0 a10 ⎥ (A18)
⎢ ⎥
⎢ 0 0 0 a11 0 0 a12 0 0 0 ⎥ a19 = Rloop a18
⎢ ⎥ (A19)
⎢ a13 a14 a15 a16 a17 a18 a19 0 0 a20 ⎥
⎢ ⎥ a20 = −a17
⎢ 0 a21 0 0 0 0 a22 0 0 0 ⎥ (A20)
A=⎢ ⎢ 0 0 0 a23 0 0 a24 0 0 0 ⎥ (A2)
⎥
⎢ ⎥ CGD1
⎢ a25 a26 a27 a28 a29 a30 a31 0 0 a32 ⎥ a21 = (A21)
⎢ ⎥ CISS1 · COSS1 − CGD1 2
⎢ a33 a34 a35 a36 a37 a38 a39 0 0 a40 ⎥
⎢ ⎥ CISS1
⎣ 0 0 0 0 0 0 0 0 0 a41 ⎦ a22 = (A22)
0 0 0 0 0 0 a42 0 a43 0 CISS1 · COSS1 − CGD1 2
 T CGD2
B = b1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 0 (A3) a23 = (A23)
CISS2 · COSS2 − CGD2 2

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QI et al.: ACCURATE DATASHEET-BASED FULL-CHARACTERISTICS ANALYTICAL MODEL OF GaN HEMTs 7953

CISS2 −LS (LG2 +LS )VG1 −LS (LG1 +LS )VG2

a24 = (A24) b8 = (LG1 +LS )(LG2 +LS )Lloop −LS 2 (LG1 +LG2 +2LS )
(A42)
CISS2 · COSS2 − CGD2 2
[(LG1 +LS )(LG2 +LS )Lloop −LS 2 (LG2 +LS )] dIdtL
a25 = a33 − (L +L )(L +L )L −L 2 (L +L +2L )
G1 S G2 S loop S G1 G2 S

LS (LG2 + LS ) Vdc
= b9 = (A43)
(LG1 + LS ) (LG2 + LS ) Lloop − LS 2 (LG1 + LG2 + 2LS ) Lin
(A25) where
 Vdc (1−D)
a26 = a34 = RG1 a25 (A26) dIL LO , 0 ≤ t ≤ DT
= , 0 ≤ D ≤ 1. (A44)
dt −D·Vdc
a27 = a35 LO , DT <t ≤T

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in Proc. IEEE Energy Convers. Congr. Expo., 2016, pp. 1–8.
[24] K. N. Chen, Z. M. Zhao, L. Q. Yuan, T. Lu, and F. B. He, “The impact of
nonlinear junction capacitance on switching transient and its modeling for Zhiyuan Qi (Student Member, IEEE) was born
SiC MOSFET,” IEEE Trans. Electron Devices, vol. 62, no. 2, pp. 333–338, in Henan Province, China, in 1989. He received
Feb. 2015. the B.S. and M.S. degrees in electrical engineering
[25] R. Q. Li, Q. H. Zhu, and M. J. Xie, “A new analytical model for predict- and automation from Harbin Engineering Univer-
ing dv/dt-induced low-side MOSFET false turn-on in synchronous buck sity, Harbin, China, in 2012 and 2015, respectively.
converters,” IEEE Trans. Power Electron., vol. 34, no. 6, pp. 5500–5512, He is currently working toward the Ph.D. degree in
Jun. 2019. electrical engineering with Xi’an Jiaotong University,
[26] J. Brown, “Modeling the switching performance of a MOSFET in the Xi’an, China.
high side of a non-isolated buck converter,” IEEE Trans. Power Electron., His research interests include the packaging and
vol. 21, no. 1, pp. 3–10, Jan. 2006. integration of wide-bandgap power semiconductors
[27] Y. L. Xiong, S. Sun, H. W. Jia, P. Shea, and Z. J. Shen, “New physical in- and high-frequency power conversion technologies.
sights on power MOSFET switching losses,” IEEE Trans. Power Electron.,
vol. 24, no. 1–2, pp. 525–531, Jan./Feb. 2009.
[28] C. C. McAndrew and J. J. Victory, “Accuracy of approximations in
MOSFET charge models,” IEEE Trans. Electron Devices, vol. 49, no. 1,
pp. 72–81, Jan. 2002. Yunqing Pei (Member, IEEE) was born in 1969.
[29] V. Dimitrov, P. Goranov, and D. Hvarchilkov, “An analytical approach to He received the B.S. and M.S. degrees in electrical
model the switching losses of a power MOSFET,” in Proc. 2016 IEEE Int. engineering, and the Ph.D. degree in power electron-
Power Electron. Motion Control Conf., 2016, pp. 928–933. ics from Xi’an Jiaotong University, Xi’an, China, in
[30] S. Eskandari, K. Peng, B. Tian, and E. Santi, “Accurate analytical switching 1991, 1994, and 1999, respectively.
loss model for high voltage SiC MOSFETs includes parasitics and body He was a Faculty Member with Xi’an Jiaotong Uni-
diode reverse recovery effects,” in Proc. IEEE Energy Convers. Congr. versity, where he is currently a Professor. From 2006
Expo., 2018, pp. 1867–1874. to 2007, he was a Visiting Scholar with the Center
[31] J. J. Wang, H. S. H. Chung, and R. T. H. Li, “Characterization and experi- of Power Electronics Systems, Virginia Polytechnic
mental assessment of the effects of parasitic elements on the MOSFET Institute and State University. His research interests
switching performance,” IEEE Trans. Power Electron., vol. 28, no. 1, include the high-power inverters, switch-mode power
pp. 573–590, Jan. 2013. supply, and converters in distributed generation systems.
[32] A. Endruschat, C. Novak, H. Gerstner, T. Heckel, C. Joffe, and M. Marz,
“A universal SPICE field-effect transistor model applied on SiC and GaN
transistors,” IEEE Trans. Power Electron., vol. 34, no. 9, pp. 9131–9145,
Sep. 2019.
[33] Efficient Power Conversion Corporation. “Circuit simulations using EP-C Laili Wang (Senior Member, IEEE) received the
device models,” [Online]. Available: https://epc-co.com/epc/Portals/0/ B.S., M.S., and Ph.D. degrees from the School of
epc/documents/product-training/Circuit_Simulations_Using_Device_ Electrical Engineering, Xi’an Jiaotong University,
M-odels.pdf Xi’an, China, in 2004, 2007, and 2011, respectively.
[34] A. X. Zhang et al., “Analytical modeling of capacitances for GaN HEMTs, Since 2011, he has been a Postdoctoral Research
including parasitic components,” IEEE Trans. Electron. Devices, vol. 61, Fellow with the Electrical Engineering Department,
no. 3, pp. 755–761, Mar. 2014. Queen.s University, Kingston, ON, Canada. From
[35] Y. H. Jia, Y. H. Xu, Z. Wen, Y. Q. Wu, and Y. X. Guo, “Analytical 2014 to 2017, he was an Electrical Engineer with
gate capacitance models for large-signal compact model of AlGaN/GaN Sumida, Canada. In 2017, he joined as a Full Pro-
HEMTs,” IEEE Trans. Electron. Devices, vol. 66, no. 1, pp. 357–363, fessor with Xi’an Jiaotong University. His research
Jan. 2019. interests include package and integration, wireless
[36] H. Gerstner, A. Endruschat, T. Heckel, C. Joffe, B. Eckardt, and M. Marz, power transfer, and energy harvesting.
“Non-linear input capacitance determination of WBG power FETs using Dr. Wang is an Associate Editor for the IEEE TRANSACTIONS ON POWER
gate charge measurements,” in Proc. IEEE 6th Workshop Wide Bandgap ELECTRONICS and IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN
Power Devices Appl., 2018, pp. 247–253. POWER ELECTRONICS. He is the Vice Chair of the Technical Committee of
[37] S. Aamir Ahsan, S. Ghosh, K. Sharma, A. Dasgupta, S. Khandelwal, and Y. Power Conversion Systems and Components (TC2) in PELS, the Co-Chair of
S. Chauhan, “Capacitance modeling in dual field-plate power GaN HEMT the System Integration and Application in International Technology Roadmap
for accurate switching behavior,” IEEE Trans. Electron. Devices, vol. 63, for Wide Bandgap Power Semiconductor (ITRW), and the Chair of the IEEE
no. 2, pp. 565–572, Feb. 2016. CPSS and PELS Joint Chapter in Xi’an, China.

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QI et al.: ACCURATE DATASHEET-BASED FULL-CHARACTERISTICS ANALYTICAL MODEL OF GaN HEMTs 7955

Kangping Wang (Member, IEEE) received the B.S. Qingshou Yang was born in Hebei, China, in 1993.
and Ph.D. degrees in electrical engineering from He received the B.S. and M.S. degrees in electrical en-
Xi’an Jiaotong University, Xi’an, China, in 2012 and gineering and automation from Yanshan University,
2018, respectively. Qinhuangdao, China, in 2016 and 2019, respectively.
From 2016 to 2017, he was with the Department He is currently working toward the Ph.D. degree in
of ePOWER, Electrical and Computer Engineering, electrical engineering with Xi’an Jiaotong University,
Queen.s University, Canada, as a Visiting Scholar. Xi’an, China.
Since 2018, he has been an Associate Professor with His research interests include application of wide-
the School of Electrical Engineering, Xi’an Jiaotong bandgap devices and power electronic integration.
University, Xi’an, China. His research interests in-
clude high-frequency power conversion technology,
and application and integration technology of wide-bandgap devices.
Dr. Wang was the recipient of the Best Paper Award of the International
Conference on Power Electronics – ECCE Asia in 2019.

Yongmei Gan was born in 1971. She received the

B.S. degree and the M.S. degree in control engineer-
ing from the Xi’an University of Technology, Xi’an,
China, in 1993 and 1996, respectively, and the Ph.D.
degree in control theory and control engineering from
Mengyu Zhu was born in 1997. She received the Northwestern Polytechnical University, Xi’an, China,
B.S. degree in electrical engineering and automation in 1999.
from the China University of Mining and Technology, Since 2000, she has been with the School of Elec-
Xuzhou, China, in 2018. She is currently working trical Engineering, Xi’an Jiaotong University, Xi’an,
toward the M.S. degree in electrical engineering with where she is currently an Associate Professor. From
Xi’an Jiaotong University, Xi’an, China. 2008 to 2009, she was a Visiting Scholar with the
Her research interests include gate drive tech- Electrical and Computer Engineering, University of Toronto. Her research
nologies of wide-bandgap semiconductors, design interests include package and integration, energy harvesting, and supervisory
of high-power high-voltage power converters, high- control of discrete-event systems.
temperature semiconductor packaging technology,
and high-temperature converter.

Cheng Zhao (Student Member, IEEE) was born in

Shanxi, China, in 1996. He received the B.S. de-
gree in electrical engineering from Jilin University,
Changchun, China, in 2017. He is currently working
toward the Ph.D. degree in electronic and electrical
engineering with Xi’an Jiaotong University, Xi’an,
China.
His research interests include packaging and appli-
cations of power semiconductor devices and parallel
operation of SiC MOSFETs.

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