L9788

Multifunction IC for automotive engine management system

Datasheet - production data

 1 channel LS main relay driver (MRD) with

internal diode for reverse battery protection
 5 channels pre-drivers for external FET drivers.
Pre-driver 1&3 configurable for O2H load with
external Rshunt-on the source of Ext.
N-channel MOS
 6 channels pre-drivers for internal or external
igniter drivers
LQFP100 14 x 14 x 1.4 mm
(exposed pad down)  1 K-Line ISO9141/LIN 2.1 compliant
GADG2411160920PS  Integrated charge-pump
 VRS-interface
Features  Watchdog
 AEC-Q100 qualified  Wake-up pin
 Engineered for ISO26262 compliant system  Temperature sensor and monitoring
 1 pre-boost regulator and 1 pre-buck regulator  Stop-counter with wakeup
 1 linear 5 V regulator with 1 A output current  Dual bandgap reference & oscillator
 3 independent self-protection 5 V tracking  Micro-second-channel MSC for differential
regulator with 150 mA output. single ended mode
 1 input voltage pin for monitor external  SEO function
tracking.  CAN-FD with wakeup by CAN function
 Coordinated soft start-up of all regulators  Package LQFP100 exposed pad
 4 channels LS injector LS drivers
 2 channels LS drivers for O2H load with current Description
sense
The L9788 is an integrated circuit designed for
 2 channels LS camshaft or solenoid drivers automotive engine management system.
 5 channels LS relay drivers L9788 is a device realized in ST BCD proprietary
 2 channels LS LED drivers technology, able to provide the full set of power
 3 channels LS/HS drivers with low battery supplies and signal preprocessing peripherals
function for smart start needed to control a 4-cylinders internal
combustion engine.

Table 1. Device summary

Order code Package Packing

L9788 LQFP100 14x14x1.4 mm Tube

L9788TR (Exposed pad down 7.6x7.6 mm)

Tape & Reel

May 2022 DS12308 Rev 4 1/264

This is information on a product in full production. www.st.com
Contents L9788

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.1 Latch-up trials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2 ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3 Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4 Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3 Operation behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1 Power up/down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.1 Power up/down state diagram chart . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.2 Power up sources and actions summary . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.3 Power up from KEY_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.4 Power down from KEY_IN when PHOLD = 0 . . . . . . . . . . . . . . . . . . . . 29
3.1.5 Power up from WK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.6 Power down from WK_IN when PHOLD=0 . . . . . . . . . . . . . . . . . . . . . . 30
3.1.7 Power up from WAKE_UP_TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.8 Power on with PHOLD_EN (EOT function 3) . . . . . . . . . . . . . . . . . . . . . 35
3.1.9 Power down from WAKE_UP_TIMER when PHOLD_EN=0 . . . . . . . . . 37
3.1.10 Power down from PHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1.11 Power up from CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1.12 Power down from WAKE_UP_CAN when PHOLD_EN=0 . . . . . . . . . . . 37
3.1.13 Finish wake function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2 Secure Engine Off (SEO) function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3 Reset strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4 Smart reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.4.1 Smart reset RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.4.2 Smart Reset RSTC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4.3 After run reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.5 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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4 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.1 Basic feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.1.1 Monitoring module - WDA Functionality . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1.2 ERR CNT (EC) and reactions, PWR COUNTER (PWR_CNT) and
generation of the monitoring module reset . . . . . . . . . . . . . . . . . . . . . . 50
4.1.3 Generation of a monitoring module reset . . . . . . . . . . . . . . . . . . . . . . . 51
4.1.4 Question generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.1.5 Response comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.1.6 Reset behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.1.7 Access during a sequencer-run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.1.8 Clock and time references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5 Main relay driver (low-side driver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.1 ON state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.1.1 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.1.2 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.2 OFF state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6 Multi-voltage regulator supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.1 Pre-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2 Pre-buck regulator with internal MOS . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3 Tracking regulator for sensors supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4 External tracking regulator monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.5 VDD5 linear regulator with external MOSFET . . . . . . . . . . . . . . . . . . . . . 75
6.6 VDD_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.7 VB_IN and VB_IN_SW SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.8 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.9 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

7 Low-side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.1 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.1.1 ON state - overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.1.2 ON state - thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.1.3 ON/OFF state - Error in on status diagnosis . . . . . . . . . . . . . . . . . . . . . 84
7.1.4 OFF state - short load and open load . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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7.1.5 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7.2 Low-side driver - INJECTOR INJ[1:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.2.1 Enable pin INJ_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.3 Low-side driver - O2 HEATER O2H[1:2] . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.4 Low-side driver - SOLENOID SOL [1:2] . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.5 Low-side driver - RELAY RLY [1:5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.6 Low-side driver - LED[1:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

8 High/low-side drivers - STARTER STR[1:3] . . . . . . . . . . . . . . . . . . . . 107

8.1 ON state diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.2 ON/OFF state - Error in on status diagnosis . . . . . . . . . . . . . . . . . . . . . 108
8.3 OFF state diagnosis LS mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.4 OFF state diagnosis HS mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.5 Delay-off function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.6 Starter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

9 Pre-drivers - ExtFET (MOS_Gate1/2/3/4/5) - PRD[1:5] . . . . . . . . . . . . 122

9.1 LS external MOSFET pre-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
9.2 ON state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.3 ON/OFF state - Error in status diagnosis . . . . . . . . . . . . . . . . . . . . . . . . 124
9.4 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.5 OFF state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

10 Pre-drivers - IGNITER IGN[1:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

10.1 Ignition pre_drivers diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
10.2 Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10.3 Short to BAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.4 Open load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.5 Error in driver status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

11 Inductive sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

11.1 VRS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
11.2 VRS - Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
11.2.1 VRS normal mode configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
11.2.2 VRS_A - Manual Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

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11.2.3 VRS_A - Fully Adaptive Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

11.2.4 VRS_A - Adaptive filter time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
11.2.5 VRS_B - Manual Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11.2.6 VRS_B -Limited Adaptive Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11.2.7 VRS_B - Fixed Filter Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11.3 VRS diagnostic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
11.4 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

12 CAN FD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

12.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.2 CAN state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.3 CAN normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.4 CAN low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.5 CAN Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.6 CAN error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.6.1 Dominant CAN_TX time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.6.2 CAN permanent recessive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.6.3 CAN permanent dominant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.6.4 CAN_RX permanent recessive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.6.5 Smart reset RSTN effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.7 Wake up With U-Chip OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.8 Wake up with U-Chip ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.8.1 Wake up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.8.2 Normal pattern wake up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.8.3 No pattern wake up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
12.9 Automatic voltage biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
12.10 CAN reset matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
12.11 CAN looping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

13 LIN/K-LINE interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

13.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.2 LIN receive only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.3 LIN thermal shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
13.4 LIN error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
13.4.1 LIN dominant TXD timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

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13.4.2 LIN permanent recessive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

13.4.3 LIN Permanent Dominant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
13.4.4 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

14 Built in self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

14.1 Power supply independency and voltage monitors . . . . . . . . . . . . . . . . 171
14.2 Analog comparators BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

15 Stand-by memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

16 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

17 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

18 Micro second channel (MSC) interface . . . . . . . . . . . . . . . . . . . . . . . . 177

18.1 Function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
18.2 Downstream communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
18.2.1 Command frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
18.2.2 Data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
18.3 Upstream communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
18.4 Micro Second Channel activity watchdog . . . . . . . . . . . . . . . . . . . . . . . . 185
18.5 Downstream frame Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
18.5.1 CONFIG-REG 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
18.5.2 CONFIG-REG 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
18.5.3 CONFIG-REG 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
18.5.4 CONFIG-REG 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
18.5.5 CONFIG-REG 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
18.5.6 CONFIG-REG 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
18.5.7 CONFIG-REG 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
18.5.8 CONFIG-REG 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
18.5.9 CONFIG-REG 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
18.5.10 CONFIG-REG 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
18.5.11 CONFIG-REG 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
18.5.12 CONFIG-REG 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
18.5.13 CONFIG-REG 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
18.5.14 CONFIG-REG 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
18.5.15 CONFIG-REG 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

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18.5.16 CONFIG-REG 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

18.5.17 CONFIG-REG 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
18.5.18 CONFIG-REG STBY_NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
18.5.19 CONFIG-REG 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
18.5.20 CONFIG-REG 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
18.5.21 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
18.6 Upstream frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
18.6.1 Upstream Bit Map Read1 (CONFIG-REG 1-4) . . . . . . . . . . . . . . . . . . 219
18.6.2 Upstream Bit Map Read2 (CONFIG-REG 5-8) . . . . . . . . . . . . . . . . . . 220
18.6.3 Upstream Bit Map Read3 (CONFIG-REG 11-13, 16-0) . . . . . . . . . . . . 221
18.6.4 Upstream Bit Map Read4 (CONFIG-REG 16-1 + Wake up timer_SET) . 222
18.6.5 Upstream Bit Map Read5 (CONFIG-REG 17-0, WAKE_UP_TIMER
VALUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
18.6.6 Upstream Bit Map Read6 (DRIVER DIAGNOSIS) . . . . . . . . . . . . . . . 224
18.6.7 Upstream Bit Map Read7 (DRIVER DIAGNOSIS) . . . . . . . . . . . . . . . 225
18.6.8 Upstream Bit Map Read8 (DRIVER DIAGNOSIS) . . . . . . . . . . . . . . . 225
18.6.9 Upstream Bit Map Read9 (DRIVER DIAGNOSIS) . . . . . . . . . . . . . . . 226
18.6.10 Upstream Bit Map Fast Read10 (SAFETY WDA) . . . . . . . . . . . . . . . . 227
18.6.11 Upstream Bit Map Read11 (SAFETY+BIST+VRS+LIN+ASIC_REV) . 229
18.6.12 Upstream Bit Map Read12 (PHOLD+POWER_UP+ADC) . . . . . . . . . 232
18.6.13 Upstream Bit Map Read13 (SUPPLY UV/OV) . . . . . . . . . . . . . . . . . . . 234
18.6.14 Upstream Bit Map Read14 (THERMAL WARNING AND CAN) . . . . . . 235
18.6.15 Upstream Bit Map Read15
(MEM_STBY_CONFIG+CONFIG_REG20+UCs) . . . . . . . . . . . . . . . . 236
18.6.16 Upstream Bit Map Read16 (MEM_STBY_DATA) . . . . . . . . . . . . . . . . 238

19 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

19.1 LQFP100 (14x14x1.4 mm exp. pad down) package information . . . . . . 239
19.2 LQFP100 (14x14x1.4 mm exp. pad down) marking information . . . . . . 242

Appendix A Device behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

A.1 Summary of all drivers block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
A.2 Slew rate and on/off delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
A.3 Power up/down scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
A.4 Main relay scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Appendix B Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

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B.1 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

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L9788 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4. ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Pin classify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Power up sources and actions summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 9. Key pins electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10. WK pins electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. VB_STBY pins electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. Wake up timer resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13. Finish wake timer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 14. SEO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 15. SEO Circuit electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Smart reset circuit electrical characteristic table 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 17. Smart reset circuit electrical characteristic table 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 18. Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 19. Error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 20. Internal states for WDA_INIT=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 21. Question and answer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 22. Watchdog reset behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 23. WDA circuit electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 24. WDA reset circuit electrical characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 25. ON state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 26. Main relay low-side driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 27. Pre-boost regulator output electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 28. Pre-boost regulator external components electrical characteristics . . . . . . . . . . . . . . . . . . 67
Table 29. Pre-buck regulator output electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 30. Pre-buck regulator external components electrical characteristics (Vpre application
information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 31. Tracking sensor supplies electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 32. VTrack external components characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 33. External VTrack monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 34. VDD5 linear controller pre-driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 35. Linear controller pre-driver. External components characteristics . . . . . . . . . . . . . . . . . . . 76
Table 36. VDD_IO electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 37. VB_IN electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 38. VB_IN_SW electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 39. Charge pump characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 40. Clock monitor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 41. Driver status diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 42. STA diagnosis for drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 43. Low-side driver error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 44. Low-side driver - INJECTOR electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 45. INJ_ENA electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 46. Low-side driver - O2 HEATER electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 47. Low-side driver - SOLENOID VALVE electrical characteristics . . . . . . . . . . . . . . . . . . . . . 97

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Table 48. Low-side driver - RELAY electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 49. Low-side driver - LED electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 50. High/low-side driver - STARTER electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 51. High/low-side driver delay-off function electrical characteristics. . . . . . . . . . . . . . . . . . . . 119
Table 52. EN_P and EN_N electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 53. Pre-driver - ExtFET error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 54. Pre-driver - ExtFET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 55. Pre-driver - IGNITER diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 56. Pre-driver - IGNITER electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 57. VRS_A, VRS_B hysteresis and filter time definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 58. VRS_A hysteresis value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 59. Peak voltage value ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 60. Insert title here . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 61. VRS sensor parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 62. Flying wheel interface function - Diagnosis test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 63. CAN threshold related Low supply voltage flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 64. CAN communication operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 65. CAN transmit data input: Pin TxDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 66. CAN transmit data output: Pin RxDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 67. CAN transmitter dominant output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 68. CAN transmitter recessive output characteristics, normal mode . . . . . . . . . . . . . . . . . . . 157
Table 69. CAN transmitter recessive output characteristics, low power mode, biasing active . . . . . 158
Table 70. CAN transmitter recessive output characteristics, low-power mode, biasing inactive . . . 158
Table 71. CAN Receiver input characteristics during normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 72. CAN Receiver input characteristics during low power mode, biasing active . . . . . . . . . . 158
Table 73. CAN Receiver input characteristics during low power mode, biasing inactive . . . . . . . . . 159
Table 74. CAN Receiver input resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 75. CAN transceiver delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 76. Maximum leakage currents on CAN_H and CAN_L, unpowered . . . . . . . . . . . . . . . . . . . 161
Table 77. Biasing control timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 78. Standby current consumption (Battery line @RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 79. Standby current consumption (Battery line @HT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 80. can_auto_bias = 1 and can_wakeup_en = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 81. can_auto_bias = 1 and can_wakeup_en = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 82. Electrical characteristics of LIN interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 83. DAC electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 84. ADC electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 85. MSC communication timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 86. MSC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 87. MSC Interface command frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 88. MSC Interface Data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 89. Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 90. MSC Interface Micro Second Channel activity watchdog . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 91. MSC Interface DOWN STREAM FRAME Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 92. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 93. MSC Interface Upstream Bit Map Read1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 94. MSC Interface Upstream Bit Map Read2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 95. MSC Interface Upstream Bit Map Read3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 96. MSC Interface Upstream Bit Map Read4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 97. MSC Interface Upstream Bit Map Read5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 98. MSC Interface Upstream Bit Map Read6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 99. MSC Interface Upstream Bit Map Read7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

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Table 100. MSC Interface Upstream Bit Map Read8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 101. MSC Interface Upstream Bit Map Read9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 102. MSC Interface Upstream Bit Map Read10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 103. MSC Interface Upstream Bit Map Read11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 104. MSC Interface Upstream Bit Map Read12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 105. MSC Interface Upstream Bit Map Read13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 106. MSC Interface Upstream Bit Map Read14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 107. MSC Interface Upstream Bit Map Read15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 108. MSC Interface Upstream Bit Map Read16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 109. LQFP100 (14x14x1.4 mm exp. pad down) package mechanical data . . . . . . . . . . . . . . . 240
Table 110. Summary of all drivers block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 111. Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 112. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

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11
List of figures L9788

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 2. Pin connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. Thermal simulation set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4. Power up state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 5. Timing for Wake Up Timer - driver by MSC start/stop commands . . . . . . . . . . . . . . . . . . . 33
Figure 6. Timing for Wake Up Timer - activated (started) by KEY negative edge . . . . . . . . . . . . . . . 33
Figure 7. Wake up timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 8. Power hold diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 9. Impulse timer clear WAKE_IN_DET after time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 10. Impulse timer disabled before time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. Timer enabled for a new detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. SEO delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 13. Reset table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 14. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 15. Reset matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 16. RSTN/RSTC after run reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 17. WDA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 18. WDA state flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 19. Monitoring cycle diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 20. Main relay low-side driver stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 21. Power supply block diagram with pre-boost regulator and MRD . . . . . . . . . . . . . . . . . . . . 62
Figure 22. Power supply block diagram with pre-boost regulator permanent VBAT . . . . . . . . . . . . . . 63
Figure 23. Power supply block diagram with charge pump without pre-boost . . . . . . . . . . . . . . . . . . . 63
Figure 24. Power supply block diagram with charge pump and MRD without pre-boost. . . . . . . . . . . 64
Figure 25. Pre-boost block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 26. Boost threshold comparator's schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 27. Power up charge pump behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 28. Power down charge pump behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 29. Clock monitor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 30. Low-side driver OFF state diagnosis schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 31. Low-side driver OFF state diagnosis load thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 32. Low-side driver OFF state fast pull up current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 33. Low-side driver OFF state diagnosis timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 34. INJECTOR LowSide driver stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 35. O2 heater LowSide driver stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 36. O2 Heater LowSide driver current sense block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 37. Solenoid valves LowSide driver stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 38. Relay LowSide driver stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 39. LED LowSide driver stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 40. Configurable high/low -side Driver block schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 41. OFF state diagnostic HS config block schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 42. OFF state diagnostic HS config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 43. High-side driver OFF state fast pull down current behavior . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 44. OFF state diagnostic high-side, timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 45. DELAY_OFF timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 46. DELAY_OFF timing terminated by MSC off command. . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 47. Safety switch off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 48. LS External MOSFET Pre-Driver Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

12/264 DS12308 Rev 4

L9788 List of figures

Figure 49. PreDriver3 configured for O2H load bit O2H_PDRV_3 = CONFIG_REG_16_1[7] = 1: . . 123
Figure 50. PreDriver1 configured for O2H load bit O2H_PDRV_1 = CONFIG_REG_16_1[6] = 1: . . 123
Figure 51. Ignition pre-drivers block schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 52. IGN pre-drivers diagnosis timing diagram at short to GND. . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 53. IGN pre-drivers diagnosis timing diagram at short to VBAT . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 54. Low-side drivers ON diagnosis timing diagram at open load . . . . . . . . . . . . . . . . . . . . . . 131
Figure 55. VRS interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 56. VRS block diagram - Normal operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 57. Hysteresis application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 58. VRS_A fully adaptive hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 59. EN_FALLING_FILT = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 60. EN_FALLING_FILT = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 61. VRS block diagram - Diagnostic operating mode - Current path . . . . . . . . . . . . . . . . . . . 142
Figure 62. Sensor sketch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 63. Variable reluctance sensor (VRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 64. Hall effect sensor configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 65. Hall effect sensor configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 66. CAN FD interface diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 67. CAN state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 68. CAN wake up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 69. CAN_TX input structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 70. CAN transceiver test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 71. Block diagram of LIN interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 72. LIN TimeOut function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 73. LIN_TX input structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 74. LIN transmission timing chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 75. LIN reception timing chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 76. LIN duty cycle timing chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 77. LIN slew rate timing chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 78. Test circuit for measurement of slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 79. Band-gap supply architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 80. Analog bist implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 81. MSC communication timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 82. Communication diagram between µC and U-CHIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 83. MSC voltage levels diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 84. MSC Command Frame bit stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 85. MSC Data Frame bit stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 86. MSC upstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 87. MSC upstream commands example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 88. MSC activity watchdog time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 89. LQFP100 (14x14x1.4 mm exp. pad down) package outline . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 90. LQFP100 (14x14x1.4 mm exp. pad down) marking information. . . . . . . . . . . . . . . . . . . . 242
Figure 91. Slew rate and on/off delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 92. Power up and power down with deglitch concept (not permanent battery) . . . . . . . . . . . 244
Figure 93. Power up and power down with boost (permanent battery) . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 94. Power up permanent battery without boost and cranking. . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 95. Power up permanent battery with boost and cranking . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 96. Power up with WK_IN and power down with WK_IN in not permanent battery condition 246
Figure 97. Power up with WK_IN and power down with WK_IN in permanent battery condition . . . 246
Figure 98. Power up with WAKE_UP_EOT/CAN and power down with WAKE_UP_EOT/CAN
(Scenario 9 and 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 99. Power up with WAKE_UP_EOT/CAN and power down with WAKE_UP_EOT/CAN

DS12308 Rev 4 13/264

14
List of figures L9788

(Scenario 24 and 25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Figure 100. Main relay driver timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 101. Power HOLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 102. Overcurrent OVC removed before VB present with KEY_IN high and Overcurrent OVC
removed before VB present with KEY_IN stays high . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 103. Overcurrent OVC permanent after VB present with KEY_IN high . . . . . . . . . . . . . . . . . . 249
Figure 104. Overcurrent OVC permanent after VB present with KEY_IN high - unlimited retry . . . . . 250
Figure 105. Overcurrent OVC removed before Tres activation with KEY_IN high and Overcurrent
OVC permanent in PHOLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 106. Overcurrent not permanent battery OVC not permanent before VB present with . . . . . . . . .
WK_IN/WAKE_UP_EOT/CAN detection (scenario 17) . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 107. Overcurrent not permanent battery OVC not permanent before VB present with . . . . . . . . .
WK_IN/WAKE_UP_EOT/CAN detection (scenario 18) . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 108. Overcurrent not permanent battery OVC not permanent after VB present with . . . . . . . . . .
WK_IN/WAKE_UP_EOT/CAN detection - no retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 109. Overcurrent in permanent battery restart conditions during KEY or WK_IN or . . . . . . . . . . .
WK_UP_EOT/CAN detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 110. Overcurrent in permanent battery PHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 111. Overtemperature in permanent battery restart conditions during KEY or WK_IN or . . . . . . .
WAKE_UP_EOT/CAN detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 112. Overtemperature in permanent battery PHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 113. Overtemperature (permanent fault) in not permanent battery Power on by KEY detection . 254
Figure 114. Overtemperature (not permanent fault) in not permanent battery Power on by KEY detection . 255
Figure 115. Overtemperature in not permanent battery Power on by WK_IN or WAKE_UP_EOT/CAN
detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 116. Overtemperature in not permanent battery Power on by PHOLD . . . . . . . . . . . . . . . . . . 256
Figure 117. Driver/predriver section application diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 118. Interface section application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 119. Multi regulator supply section application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

14/264 DS12308 Rev 4

L9788 Block diagram and pin description

1 Block diagram and pin description

1.1 Block diagram

Figure 1. Block diagram
BUCK_C_BST

VBAT_Sense BOOST_G VB_IN CP VB_IN_SW BUCK_SW VPRE

Boost Regulator VDD5 VDD5_Gate

Charge Pump Buck Regulator
Driver Regulator
VDD5_IN

BIST
VSENSE1 Vcore_UV
3 x Tracking RESET RSTN
VSENSE2 CP VDD5_UV
Regulator
VSENSE3 Internal WD_RST
Regulator 5
RLY1..5

1 x ext Tracking Dual

VSENSE4_MON Regulator Monitor Bandgap
5 x 0.6A
LSD
AD_TEST Dual 4
O2HxxA,O2HxxB
Oscillator 2
KEY_IN CURR_Sense_O2H1,2
ENABLE 4
WK_IN Wake Up O2HxPGND
VB_STDBY 6 INJ1..4
2 x 6A
SOL1..2
LSD
Key Off Timer INJ_ENA
SEO_OUT
SEO 6 x 2.2A 4 SOL12_PGND
LSD INJx_PGND
Q&A WD_RST
2
WDA LED1/2
Watchdog
6x
Ignition
FLW_IN_P Pre
2 x 70mA
FLW_IN_N LSD (LED) driver 6
VRS IGN1,2,3,4,5,6
FLW_OUT

RSTC
VDD_IO MSC 5
MSC_CK_P,N
6 PRDN1,2,3,4,5_DRN
Micro Second Channel
MSC_DI_P,N 5
MSC_EN, MSC_DO PRDN1,2,3,4,5_Gate
5 xx
CAN_TX MOSFET
CAN_RX Pre PDR_GND
CAN_H Driver
CAN FD
CAN_L Pre Driver MRD
VDD_CAN ISO11898-2 3
STR1,2,3_DRN
VB_CAN Power Output
GND_CAN EN_P
Logic
EN_N
LIN_TX 3x
Supply MRD 0.6A 3
LIN_RX LIN/K-Line STR1,2,3_SRC
LIN HSD/LSD
Interface

GND1 3 Pins TestMode

(PowerGND) GADG2411160929PS

DS12308 Rev 4 15/264

263
Block diagram and pin description L9788

1.2 Pin description

Figure 2. Pin connection diagram (top view)

CURR_Sense_O2H1

CURR_Sense_O2H2
O2H1_PGNDA

O2H1_PGNDB
O2H2_PGNDA

O2H2_PGNDB

Buck_C_BST

VBAT_Sense
VB_IN_SW
GND_CAN

VDD_CAN

Buck_SW
CAN_RX
VB_CAN
CAN_TX

Boost_G
O2H1A
O2H1B

O2H2A
O2H2B

VB_IN
CANH
CANL
GND

CP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
FLW_IN_P 1 75 GND
FLW_IN_N 2 74 RSTC
FLW_OUT 3 73 VDD5_GATE
LIN_TX 4 72 VDD5_IN
LIN_RX 5 71 AD_TEST
LIN 6 70 PDR_GND
VB_STBY 7 69 VPRE
VSENSE4_MON 8 68 VSENSE1
KEY_IN 9 67 VSENSE2
WK_IN 10 66 VSENSE3
MRD 11 65 SOL1
INJ3 12 64 SOL12_PGND
INJ34_PGND 13 63 SOL2
INJ4 14 62 IGN5
STR1_DRN 15 61 IGN6
STR1_SRC 16 60 PRD1_DRN
STR2_SRC 17 59 PRD1_GATE
STR2_DRN 18 58 PRD3_GATE
STR3_DRN 19 57 PRD3_DRN
STR3_SRC 20 56 PRD2_DRN
LED1 21 55 PRD2_GATE
LED2 22 54 PRD4_GATE
GND 23 53 PRD4_DRN
WDA 24 52 PRD5_DRN
RSTN 25 51 PRD5_GATE
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
IGN3
IGN4
MSC_EN
MSC_CK_P
MSC_CK_N
MSC_DI_P
MSC_DI_N
GND1
SEO_OUT
VDD_IO
MSC_DO
INJ_ENA
EN_N
EN_P
IGN1
IGN2

INJ1
INJ1_PGND
INJ2_PGND
INJ2
RLY3
RLY4
RLY5
RLY1
RLY2

GADG2411160940PS

Table 2. Pin function

Pin # Name Function Type Note

1 FLW_IN_P Flying wheel inputs voltage positive Power In -

2 FLW_IN_N Flying wheel inputs voltage negative Power In -
3 FLW_OUT Flying wheel output voltage Digital Out -
4 LIN_TX LIN data input Digital In -
5 LIN_RX LIN data output Digital Out -

16/264 DS12308 Rev 4

L9788 Block diagram and pin description

Table 2. Pin function (continued)

Pin # Name Function Type Note

6 LIN LIN driver output Power In/Out -

7 VB_STBY Standby function supply voltage Supply -
8 VSENSE4_MON tracking sensor supply Monitor Analog In -
9 KEY_IN Key signal input Power In -
10 WK_IN wake up signal input Power In -
11 MRD Main relay drivers outpour voltage Power Out -
12 INJ3 Injector Driver output voltage Power Out -
13 INJ34_PGND Ground GND -
14 INJ4 Injector Driver output voltage Power Out -
15 STR1_DRN Configurable high/low-side drain voltage Power Out -
16 STR1_SRC Configurable high/low-side source voltage Power Out -
17 STR2_SRC Configurable high/low-side source voltage Power Out -
18 STR2_DRN Configurable high/low-side drain voltage Power Out -
19 STR3_DRN Configurable high/low-side drain voltage Power Out -
20 STR3_SRC Configurable high/low-side source voltage Power Out -
21 LED1 LED Driver output voltage Power Out -
22 LED2 LED Driver output voltage Power Out -
23 GND Ground GND -
24 WDA Watchdog output Digital In/Out -
25 RSTN Reset output for VDD5 Digital Out -
26 SEO_OUT SEO output pin Digital Out -
Dedicated supply for FLW_OUT,
27 VDD_IO Supply -
MSC_DO,LIN_RX, CAN_RX
28 MSC_DO MSC digital I/O voltage Digital Out -
29 INJ_ENA Enable pin for injector driver Digital In -
30 EN_N enable signals Digital In -
31 EN_P enable signals Digital In -
32 IGN1 Ignition pre-driver output voltage Power Out -
33 IGN2 Ignition pre-driver output voltage Power Out -
34 RLY1 Relay Driver output voltage Power Out -
35 RLY2 Relay Driver output voltage Power Out -
36 INJ1 Injector Driver output voltage Power Out -
37 INJ1_PGND Ground GND -
38 INJ2_PGND Ground GND -
39 INJ2 Injector Driver output voltage Power Out -

DS12308 Rev 4 17/264

263
Block diagram and pin description L9788

Table 2. Pin function (continued)

Pin # Name Function Type Note

40 RLY3 Relay Driver output voltage Power Out -

41 RLY4 Relay Driver output voltage Power Out -
42 RLY5 Relay Driver output voltage Power Out -
43 IGN3 Ignition pre-driver output voltage Power Out -
44 IGN4 Ignition pre-driver output voltage Power Out -
45 MSC_EN MSC digital I/O voltage Digital In -
46 MSC_CK_P MSC digital I/O voltage Digital In -
47 MSC_CK_N MSC digital I/O voltage Digital In -
48 MSC_DI_P MSC digital I/O voltage Digital In -
49 MSC_DI_N MSC digital I/O voltage Digital In -
Shorted to GND by
50 GND1 Power ground GND
package
51 PRD5_GATE General purpose pre-drivers gate voltage Power Out -
52 PRD5_DRN General purpose pre-drivers feedback voltage Power In -
53 PRD4_DRN General purpose pre-drivers feedback voltage Power In -
54 PRD4_GATE General purpose pre-drivers gate voltage Power Out -
55 PRD2_GATE General purpose pre-drivers gate voltage Power Out -
56 PRD2_DRN General purpose pre-drivers feedback voltage Power In -
57 PRD3_DRN General purpose pre-drivers feedback voltage Power In -
58 PRD3_GATE General purpose pre-drivers gate voltage Power Out -
59 PRD1_GATE General purpose pre-drivers gate voltage Power Out -
60 PRD1_DRN General purpose pre-drivers feedback voltage Power In -
61 IGN6 Ignition pre-driver output voltage Power Out -
62 IGN5 Ignition pre-driver output voltage Power Out -
63 SOL2 Valve driver output voltage Power Out -
64 SOL12_PGND Ground GND -
65 SOL1 Valve driver output voltage Power Out -
66 VSENSE3 5V tracking sensor supply output voltage Power Out -
67 VSENSE2 5V tracking sensor supply output voltage Supply Out -
68 VSENSE1 5V tracking sensor supply output voltage Supply Out -
69 VPRE Buck output voltage Supply Out -
70 PDR_GND Ground pin for predriver supply feedback input GND -
71 AD_TEST AD test pin Analog Out -
72 VDD5_IN 5V regulator feedback voltage Power In -
73 VDD5_GATE 5V linear regulator pre-driver output Power Out -

18/264 DS12308 Rev 4

L9788 Block diagram and pin description

Table 2. Pin function (continued)

Pin # Name Function Type Note

74 RSTcase Reset output for VDDIO supply Digital Out -

75 GND Ground GND -
76 Boost_G Boost LS gate voltage Power Out -
77 VBAT_Sense Battery supply voltage Supply In -
78 VB_IN Battery supply voltage Supply In -
79 CP Charge pump Power Out -
80 Buck_C_BST Bootstrap capacitor pin Power Out -
81 Buck_SW Buck switching pin Power Out -
82 VB_IN_SW BUCK supply voltage Power In -
83 CURR_Sense_O2H2 O2heater drivers output current value Analog Out -
84 O2H2_PGNDB Ground GND -
85 O2H2B O2H2B Driver output voltage Power Out -
86 O2H2A O2H2A Driver output voltage Power Out -
87 O2H2_PGNDA Ground GND -
88 O2H1_PGNDB Ground GND -
89 O2H1B O2H1BDriver output voltage Power Out -
90 O2H1A O2H1A Driver output voltage Power Out -
91 O2H1_PGNDA Ground GND -
92 VDD_CAN CAN Supply 5 V Supply In -
93 CURR_Sense_O2H1 O2heater drivers output current value Analog Out -
94 CANH CANH output Power In/Out -
95 CANL CANL output Power In/Out -
96 CAN_RX CAN RX data output Digital In/Out -
97 GND Ground GND -
98 CAN_TX CAN TX data input Digital In -
99 VB_CAN CAN enable signal Supply In -
100 GND_CAN Ground CAN GND -

DS12308 Rev 4 19/264

263
Absolute maximum ratings L9788

2 Absolute maximum ratings

The component withstands all the following stimuli without any damage or latch-up.
Exceeding any of these values or sustaining it for extended periods may lead to
characteristics degradation or component damage.
All voltages are related to analog ground
Tj -40 to 175 °C unless otherwise specified.

Table 3. Absolute maximum ratings

Pin(1)
Pin name Parameter Referred to Constr. Min Max Unit
Direction

- -0.3 +40 V S

Chip supply 10 ms
VB_IN GND1 (ISOpulse1)
voltage -2 - V S
VB_IN pin shorted
with VB_IN_SW
- -0.3 +40 V S
Buck supply
VB_IN_SW GND1 10 ms
voltage -2 - V S
(ISOpulse1)
Battery supply
VBAT_Sense GND1 - -0.3 +40 V S
voltage sense
Protect from
VBAT_Sense Input current GND1 Reverse battery -16 - mA S
with 1k Ω resistor
Protect from
VBAT_Sense Input current GND1 ISOPULSE 1 with -150 - mA S
1 kΩ resistor
Standby function
VB_STBY supply voltage GND1 - -16 +40 V S
for EOT
Boost LS gate
Boost_G GND1 - -0.3 +20 V O
voltage
Buck output
VPRE GND1 - -0.3 +20 V S
voltage
Buck switching
Buck_SW GND1 - -0.3(2) +40 V S
pin
Bootstrap
Buck_C_BST GND1 - -0.3 +45 V I
capacitor pin
5 V linear
VDD5_GATE regulator pre- GND1 - -0.3 +20 V O
driver output
5 V regulator
VDD5_IN feedback GND1 - -0.3 +20 V S
voltage

20/264 DS12308 Rev 4

L9788 Absolute maximum ratings

Table 3. Absolute maximum ratings (continued)

Pin(1)
Pin name Parameter Referred to Constr. Min Max Unit
Direction

Dedicated 5 V
voltage for
VDD_IO FLW_OUT, GND1 - -0.3 +20 V S
MSC_DO,
TxDC, RxDC
5 V tracking
VSENSE1,
sensor supply GND1 - -2 +40 V S
VSENSE2, VSENSE3
output voltage
External tracking
VSENSE4_MON sensor supply GND1 - -2 +40 V I
Monitor
VB_IN+
CP Charge pump GND1 - -0.3 V S
5V
GND1 Power ground - - -0.3 +0.3 V O
GND_CAN Power ground GND1 - -0.3 +0.3 V O
Digital output
WDA (open drain) / GND1 - -0.3 +20 V I/O
Digital input
SEO_OUT Digital output GND1 - -0.3 +20 V O
Digital output /
RSTN, RSTC GND1 - -0.3 +20 V I/O
open drain
Digital output
AD_TEST GND1 - -0.3 +20 V O
voltage
Digital input /
INJ_ENA, GND1 - -0.3 +20 V I/O
Digital output
KEY_IN, WK_IN Input voltage GND1 - -0.3 +40 V I
Protect from
KEY_IN, WK_IN Input current GND1 Reverse battery -16 - mA I
with 1 kΩ resistor
Protect from
KEY_IN, WK_IN Input current GND1 ISOPULSE 1 -150 - mA I
with 1 kΩ resistor
MSC_EN,
MSC_CK_P,
MSC_CK_N, MSC digital I/O
GND1 - -0.3 +20 V I/O
MSC_DI_P, voltage
MSC_DI_N,
MSC_DO
FLW_IN_P, Flying wheel With 20 mA (Max)
GND1 -0.3 Vclamp V I
FLW_IN_N inputs voltage inputs current
FLW_IN_P, Flying wheel
- - -20 +20 mA I
FLW_IN_N inputs current

DS12308 Rev 4 21/264

263
Absolute maximum ratings L9788

Table 3. Absolute maximum ratings (continued)

Pin(1)
Pin name Parameter Referred to Constr. Min Max Unit
Direction

Flying wheel
FLW_OUT output voltage GND1 - -0.3 +20 V O
(open drain)
Main relay
MRD drivers outpour GND1 - -16 Vclamp V O
voltage
INJ1
INJ2
INJ3
INJ4
O2H1A
O2H1B
O2H2A
O2H2B
Low-side drivers
SOL1 GND1 - -1 Vclamp V O
output voltage
SOL2
RLY1
RLY2
RLY3
RLY4
RLY5
LED1
LED2
STR1_DRN Configurable
STR2_DRN high/low-side GND1 - -1 Vclamp V O
STR3_DRN drain voltage

STR1_SRC Configurable
STR2_SRC high/low-side GND1 - Vclamp* +40 V O
STR3_SRC source voltage

IGN1
IGN2 Negative voltage
IGN3 Ignition pre- with limited
driver output GND1 current at 20 mA, -1 +40 V O
IGN4
voltage protected by
IGN5 external resistor
IGN6

CURR_Sense_O2H1 O2heater drivers

output current GND1 - -0.3 +20 V O
CURR_Sense_O2H2 value

22/264 DS12308 Rev 4

L9788 Absolute maximum ratings

Table 3. Absolute maximum ratings (continued)

Pin(1)
Pin name Parameter Referred to Constr. Min Max Unit
Direction

INJ1_PGND
INJ2_PGND
INJ34_PGND
O2H1_PGNDA
Low-side drivers
O2H1_PGNDB GND1 - -0.3 +0.3 V O
GND
O2H2_PGNDA
O2H2_PGNDB
SOL12_PGND
PDR_GND
PRD1_GATE
PRD2_GATE General purpose
PRD3_GATE pre-drivers gate GND1 - -0.3 +20 V O
PRD4_GATE voltage
PRD5_GATE
PRD1_DRN
PRD2_DRN General purpose
pre-drivers
PRD3_DRN GND1 - -0.3 +60 V I
feedback
PRD4_DRN voltage
PRD5_DRN
Digital input
EN_N (Cranking
GND1 - -0.3 +20 V I
EN_P drivers enable
signals)
LIN_TX LIN data input GND1 - -0.3 +20 V I
LIN_RX LIN data output GND1 - -0.3 +20 V O
LIN LIN driver output GND1 T = -40 °C -18 +40 V O
LIN LIN driver output GND1 T = -27 °C, 175 °C -27 +40 V O
CAN_TX CAN data input GND1 - -0.3 +20 V I
CAN_RX CAN data output GND1 - -0.3 +20 V O
CAN driver
CANH GND1 - -27 +40 V O
output
CAN driver
CANL GND1 - -27 +40 V O
output
VDD_CAN CAN Supply 5V GND1 - -0.3 +20 V S
CAN Supply
VB_CAN GND1 - -16 +40 V S
Battery

DS12308 Rev 4 23/264

263
Absolute maximum ratings L9788

Table 3. Absolute maximum ratings (continued)

Pin(1)
Pin name Parameter Referred to Constr. Min Max Unit
Direction

Differential
VCANH-VCANL CAN-bus - - -5 10 V -
voltage
1. S: supply pin;
I: input pin;
O: output pin;
I/O: input/output pin
2. -2 V allowed during transients.

2.1 Latch-up trials

Latch-up tests performed according to JEDEC 78 class 2 Level A.

2.2 ESD
Table 4. ESD
Symbol Parameter Test condition Min Typ Max Unit Pin

ESD according to Human

HBM global Body Model (HBM), Q100-
ESD HBM Global -4 - 4 kV Global
pins 002 for global pins;
(100pF/1.5kΩ)
ESD according to Human
HBM local Body Model (HBM), Q100-
ESD HBM -2 - 2 kV ALL
pins 002 for all pins;
(100pF/1,5kΩ)
ESD according to Human
ESD HBM Global CAN_H, Body Model (HBM), Q100-
-8 - 8 kV Global
CAN CAN_L pins 002 for global pins;
(100pF/1.5kΩ) (1)
Direct ESD Test according to
IEC 61000-4-2 (150 pF,
330 ) and ‘Hardware
ESD HBM Global CAN_H,
Requirements for LIN, CAN -6 - 6 kV Global
CAN CAN_L pins
and Flexray Interfaces in
Automotive Applications’
(version 1.3, 2012-05-04)
ESD according to Charged
CDM corner
ESD CDM Corner Device Model (CDM), Q100- -750 - 750 V Corner
pins
011 Corner pins
ESD according to Charged
ESD CDM CDM all pins Device Model (CDM), Q100- -500 - 500 V ALL
011 All pins
1. HBM with all not zapped pins grounded.

24/264 DS12308 Rev 4

L9788 Absolute maximum ratings

Table 5. Pin classify

Pin classify

VB_IN VBAT_Sense VB_STBY VSENSE1/2 VESNSE3/4_MON

KEY_IN WK_IN MRD INJ1/2/3/4 O2H1/2 SOL1/2 RLY1/2/3/4/5
Global pin (ECU connector)
LED1/2 STR1/2/3_DRN STR1/2/3_SRC IGN1/2/3/4/5/6 LIN
PRD1/2/3/4/5_DRN
VDD_IO WDA SOE_OUT RSTN INJ_ENA MSC_EN MSC_CK_P
Direction pin (power and MSC_CK_N MSC_DI_P MSC_DI_N MSC_DO FLW_OUT
I/O) CURR_Sense_O2H1/2 PRD1/2/3/4/5_GATE EN_P EN_N LIN_TX
LIN_RX VDD5_IN CP EN_N EN_P
VB_IN_SW Boost_G VPRE BUCK_SW Buck_C_BST VDD5_GATE
Local pins
FLW_IN_P FLW_IN_N
GND1 INJ1/2/3/4_PGND O2H1/2_PGND_A O2H1/2_PGND_B
GND pins
GND

2.3 Temperature ranges and thermal data

Table 6. Temperature ranges and thermal data
Pin Symbol Parameter Test condition Min Typ Max Unit

- Ta Operating temperature - -40 - 125 °C

- Tj Junction temperature - -40 - 175 °C
- Tstr Storage temperature - -50 - 175 °C
Thermal resistance
- RTHj-c(1) - - 1 - °C/W
junction to case
supposing a mounting on
Thermal Resistance board 2s2p + heatsink vias
- RTHj-a(1) - 10 - °C/W
junction to ambient (refer to application note
for PCB parameters)
1. With 2s2p PCB thermally enhanced, cold plate as per std Jedec best practice guidelines (JESD51), assuming Pdiss = 5 W
dissipated statically and homogeneously, thermal vias under package exposed pad assuming filling ratio 50% and 35 µm
vias diameter (157 vias estimation); refer to Figure 3: Thermal simulation set-up on page 26.

Note: All parameters are tested in the temperature range Tj -40 - 150°C; device functionality at
high temperature is guaranteed by bench validation, electrical parameters are guaranteed
by correlation with ATE tests at reduced temperature and adjusted limits (if needed).
Temperature sensor present, please refer to Section 3.5.

DS12308 Rev 4 25/264

263
Absolute maximum ratings L9788

Figure 3. Thermal simulation set-up

Boundary conditions
- Thermal simulations carried on using typical boundaries for ECU applications:
- 4 layer board with thermal vias
- metal plate in contact with board
- Thermal interface material (TIM) between PCB and metal plate
- TAMB = 135 °C / natural convection

Picture not to scale

4 layer board PCB

With these boundaries and
Vias
considering uniform power on
overall chip surface, ST
TIM
package thermal resistance is:
metal plate
Theta J-A = 10 °C/W

GADG2411161145PS

2.4 Functional range

Table 7. Functional range
Symbol Parameter Note Min Typ Max Unit Pin

u-chip in cranking condition, reduced

operation range, main relay and
delayed off power stages keep the
Cranking
- status if delay-off function is triggered. 3.1 - 4.8 V VB_IN
condition
All other driver/regulators/CAN/LIN are
in off condition. See description in the
Reset Matrix Table, Section 12.10.
u-chip in low drop operation condition,
all functions are guaranteed all
Low drop
- parametersare guaranteed unless 4.8 - 7 V VB_IN
condition
specified. Vpre and VDD5 are in low
drop condition

u-chip in normal operation condition. all

functions and parameters are
Normal
- guaranteed, considering the description 7 - 19 V VB_IN
condition
range of electrical characteristic table
and parameters test set up

26/264 DS12308 Rev 4

L9788 Absolute maximum ratings

Table 7. Functional range (continued)

Symbol Parameter Note Min Typ Max Unit Pin

u-chip in jump start condition, all

Jump start
- functions are guaranteed. parameters 19 - 28 V VB_IN
condition
are guaranteed unless specified.

u-chip in load dump condition. U-chip is

no damage.
Load dump All drivers/regulators/CAN/LIN are in off
- 28 40 V VB_IN
condition condition. See description in the Reset
Matrix Table, Section 3.3 and
Section 12.10.

DS12308 Rev 4 27/264

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Operation behavior L9788

3 Operation behavior

3.1 Power up/down

3.1.1 Power up/down state diagram chart

The power up/down sequences are shown as state diagram in the following figure:

Figure 4. Power up state diagram

DETECTION OF
KEY=1 (high level on KEY pin after Key_Tfilter gives KEY_DET=1)
or
:.B,1ĺ(low to high level on WK_IN pin gives WAKE_IN_DET=1)
or
WAKE_UP_EOT (end of the counting of the EOT2 function gives WAKE_UP_EOT_DET=1)
or
WAKE_UP_CAN (pattern validated at CAN pins gives WAKE_UP_CAN_DET=1)
POWER
OFF UP
KEY=0
WK_IN=0
MRD_TIMEOUT EXPIRED (when system is not powered up by KEY)

POWER ON RESET RELEASE

VPRE and VDD5
3V3 digital supply -derived from VB_IN -is present
UNDERVOLTAGE

KEY_DET=0 and Watchdog PWR_CNT>7

POWER
ON
DOWN

KEY_DET=0 and WAKE_IN_DET=0 and WAKE_UP_EOT_DET=0 and WAKE_UP_CAN_DET=0 and PHOLD_TIMEOUT=OFF

or
KEY_DET=0 and MSC_WAKE_IN_RST=1 and WAKE_UP_EOT_DET=0 and WAKE_UP_CAN_DET=0 and PHOLD_TIMEOUT=OFF
or
KEY_DET=0 and WAKE_IN_DET=0 and MSC_WAKE_UP_EOT_RST=1 and WAKE_UP_CAN_DET=0 and PHOLD_TIMEOUT=OFF
or
KEY_DET=0 and WAKE_IN_DET=0 and WAKE_UP_EOT_DET=0 and MSC_WAKE_UP_CAN_RST=1 and PHOLD_TIMEOUT=OFF
or
KEY_DET=0 and WAKE_IN_DET=0 and WAKE_UP_EOT_DET=0 and WAKE_UP_CAN_DET=0 and PHOLD_TIMEOUT(EOT3)=EXPIRED
or
KEY_DET=0 and (WAKE_IN_DET=1 or WAKE_UP_EOT_DET=1 or WAKE_UP_CAN_DET=1) and FIN_WAKE EXPIRED and PHOLD_TIMEOUT=OFF

GADG2411161158PS

3.1.2 Power up sources and actions summary

Table 8. Power up sources and actions summary

KEY_IN WK_IN EOT CAN_FD VB_IN MRD Actions

active - - - not permanent on MRD on by KEY_IN pin

active - - - permanent on MRD on by KEY_IN pin
active - - not permanent on MRD on by WK_IN pin
MRD used as normal low-side driver (is
- active - - permanent off
controlled by MSC)
- - active - not permanent on MRD on by EOT
MRD used as normal low-side driver (is
- - active - permanent off
controlled by MSC)

28/264 DS12308 Rev 4

L9788 Operation behavior

Table 8. Power up sources and actions summary (continued)

KEY_IN WK_IN EOT CAN_FD VB_IN MRD Actions

- - - active not permanent on MRD on by CAN

MRD used as normal low-side driver (is
- - - active permanent off
controlled by MSC)

3.1.3 Power up from KEY_IN

The chip is powered up if KEY_IN signal stays asserted for Key_Tfilter.There is a MSC bit
(KEY_IN_PIN_FLT in read command 15 frame 2) to indicate the status of KEY_IN pin signal
after filter time.

3.1.4 Power down from KEY_IN when PHOLD = 0

The chip is powered down if KEY_IN signal stays de-asserted for Key_Tfilter if no other
power up source is active.
Condition:
4.8 ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified.

Table 9. Key pins electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

Logic input high

VIH - 3.6 - 4.1 V KEY_IN
voltage threshold
Logic input low
voltage threshold
VIL1 - 3.1 - 3.6 V KEY_IN
Main logic in POR
not released
Logic input low
voltage threshold
VIL2 - 1.7 - 2.3 V KEY_IN
Main logic POR
released
Logic input
VIHYS - 0.1 - 0.8 V KEY_IN
hysteresis
Filter time for Guaranteed by
Key_Tfilter 7.5 16 24 ms KEY_IN
switching on/off test scan(1)
Input current of
Iinput KEY_IN ≤ 5 V - - 340 µA KEY_IN
KEY_IN
RPD Pull-down resistor KEY_IN = 1 V 170 300 500 kΩ KEY_IN
1. Filter time for switching on, is active until KEY logic is out of POR, Filter time for switching off, is active until main logic out
of POR.

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263
Operation behavior L9788

3.1.5 Power up from WK_IN

The chip is powered up if WK_IN signal has a rising edge and stays asserted for WK_Tfilter.
In case the power up of the chip is not completed in a MRD_EN_TIMEOUT from WK_IN
rising edge detection the Main Relay Driver is switched off and the chip goes in OFF state.
The u-chip will not power up until further rising edge on WK_IN pin. This detection of a
WK_IN condition flag is named WK_IN_DET (detection of a WK_IN condition) and is
cleared by VDD5/VDDIO under voltage or by the MSC command WK_IN_RST. In these
cases, if no other power-on source is active, a power down sequence is started.When U
chip is already in on state (the logic is out of power on reset), the rising edge on pin WK_IN
only sets a flag, with no impact on power supply.
The Main Relay Driver is not switched on by WAKE_IN_DET rising edge if the device is in
permanent battery. To recognize the permanent battery condition the main logic has to be
out of Power On Reset within Tbattery_det.
There is a MSC bit (WAKE_IN_PIN_FLT in read command 15 frame 2) to indicate the status
of WK_IN pin signal after filter time.
A negative glitch on WK_IN can produce unwanted power up and also prevent the correct
power down.
To cover the major cases the falling edge filtering is done both in the VB_STBY domain and
in the VB_IN domain. Depending on which supply is present the behavior is described in the
following cases:
1. If VB_STBY is present the falling edge filtering is applied also to power up so a
negative glitch on WK_IN will not power up the device.
If VB_STBY is not present a negative glitch on WK_IN will power up the device.
2. If VB_IN is present (after the device is already powered up) the falling edge filtering on
WK_IN avoids that a glitch (happening in PHOLD after the MSC has cleared the
WK_IN detection) is recognized as valid detection and the device is kept on.

3.1.6 Power down from WK_IN when PHOLD=0

The chip is powered down if the MSC clears, by the MSC command WK_IN_RST, the
detection of WK_IN positive edge if no other power up source is active. The power down is
actuated even if WK_IN is still high. The power down is not activated by WK_IN going low or
WK_IN low level. The detection reset by MSC command, WK_IN_RST
(CONFIG_REG12[7]), is active at level, so from when MSC writes them at 1 they keep on
clearing the detections. If there is further wake detection signal, the detection signal will be
cleared, until the MSC writes 0 in the bits.
Condition:
4.8 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified.

Table 10. WK pins electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

Logic input high

VIH - 3.6 - 4.1 V WK_IN
voltage threshold
Logic input low
VIL - 3.1 - 3.6 V WK_IN
voltage threshold
VIHYS Logic input hysteresis - 0.1 - 0.8 V WK_IN

30/264 DS12308 Rev 4

L9788 Operation behavior

Table 10. WK pins electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Input current of
Iinput WK_IN ≤ 5 V - - 340 µA WK_IN
WK_IN
Filter time for Guaranteed by test
WK_Tfilter 1 2 3 ms WK_IN
switching on/off scan
RPD Pull-down resistor WK_IN=1V 170 300 500 kΩ WK_IN
Timeout for power up
MRD_EN_TIMEOUT - 331 500 650 ms WK_IN
execution
Main logic POR
timeout (used to
Tbattery_det - 210 - 450 µs -
recognize permanent
battery condition)

3.1.7 Power up from WAKE_UP_TIMER

The chip is powered up when an end counting is reached inside the wake_up_timer block.
The end and enable counting are set by MSC before the chip is powered down. In case the
power up of the chip is not completed in a MRD_EN_TIMEOUT from WAKE_UP_EOT end
of counting detection the Main Relay Driver is switched off and the chip goes in OFF state.
When U chip is already in on state (the logic is out of power on reset), the wake_up_timer
end counting only sets a flag, with no impact on power supply. This flag is named
WAKE_UP_EOT_DET (detection of a wake_up end of time condition) and is clear by
VDD5/VDDIO under voltage or by the MSC command WAKE_UP_EOT_RST. If no other
power on source is active a power down sequence is started.
The Main Relay Driver is not switched on by WAKE_UP_EOT if the device is powered in
permanent battery.
The MSC sets the programmable time on Wake up timer_SET Registers (CONFIG-REG15-
0 to CONFIG_REG15-2). The counting can be started/stopped by MSC command -
CONFIG_REG1[6:7] = WAKE_UP_TIMER_START_STOP[0:1] (CONFIG_REG1 D6;D7) -
or by switching the pin KEY_IN according to a selection set by MSC bit -
CONFIG_REG20[2] = WAKE_UP_TIMER_EN_SEL.
The counter counts time on the WAKE_UP_TIMER_CNT Register.
WAKE_UP_TIMER_CNT Register and Wake up timer_SET Register are being compared,
and when they match, WAKE_UP_EOT_DET signal will be set to high level to trigger a
power up sequence.
Condition:
4.8 V ≤ VB_IN ≤ 18 V, 3.5 V ≤ VB_STBY ≤ 18 V Tj -40 to 175 °C unless otherwise specified;
VB_STBY > 3.5 V, EOT can keep the counter value (allow to stop counting), 
5 V < VB_STBY < 18 V, EOT full function, full parameter.

DS12308 Rev 4 31/264

263
Operation behavior L9788

Table 11. VB_STBY pins electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

VB_STBY voltage
range that EOT counter
VVB_STBY_Th - 3.5 - - V VB_STBY
keep data or operating
correctly
VB_STBY current with
3.5 < VB_STBY< 18 V
IVB_STBY_EOT_disable EOT 32 kHz Clock - - 30 µA VB_STBY
VB_CAN < 0.7 V
device OFF

VB_STBY current with 3.5 < VB_STBY< 18 V

IVB_STBY_ EOT_enable EOT 32 kHz Clock VB_CAN < 0.7 V - - 50 µA VB_STBY
device ON -40 °C < Tamb < 80 °C
VB_STBY current with 3.5 < VB_STBY< 18 V
IVB_STBY_EOT_enable EOT 32 kHz Clock VB_CAN < 0.7 V - - 70 µA VB_STBY
device ON 80 °C < Tamb < 125 °C
Freq EOT 32 kHz Clock 6 V < VB_STBY <18 V
EOT_clock_frequency -6% 1 +6% Hz VB_STBY
internal components -40° C <Tamb < 80 °C
Freq EOT 32 kHz Clock 6 < VB_STBY < 18 V
EOT_clock_frequency -7% 1 +7% Hz VB_STBY
internal components 80 °C < Tamb < 125 °C
VB_STBY under
voltage threshold the
VB_STBY_UV 32 kHz clock is active VB_STBY > 3.1 V 3.5 - 5 V VB_STBY
but counter is stopped
during crank.

When VB_STBY_UV happens, it stops the counter.

The counter will resume when vb_stby_uv goes low (no undervoltage).

32/264 DS12308 Rev 4

L9788 Operation behavior

Figure 5. Timing for Wake Up Timer - driver by MSC start/stop commands

MSC read and clear

VB_STBY_UV
Power on reset on VB_STBY

VB_STBY_UV=READ13.FRAME2[0]

counter start(1) stop(0)

WAKE_UP_TIMER_SET

WakeUpTimer COUNT_VALUE h00001

h00000
END COUNTING
POWER_UP

WAKE_UP_EOT_DET POWER_ON

WAKE_UP_EOT_DET_RST
(MSC)
POWER_DOWN

GADG2411161534PS

Figure 6. Timing for Wake Up Timer - activated (started) by KEY negative edge

Configuration “Start by Key Signal” Configuration “Start by Command”

KEY

EOT counter value

Full scale

MSC communication
CSN

ECU sleep ECU sleep ECU sleep

t
readout set command
counter configuration start
value “START by counter
Command”
GADG2411161545PS

Reset condition
VB_STBY under voltage stops (not reset) EOT counter during cranking. The counter is reset
in case of power on reset generated on VB_STBY supply.

DS12308 Rev 4 33/264

263
Operation behavior L9788

Count up
Wake up Timer shall count up the timer from 1 while the MSC Wake Up Timer Start command
is given. When Wake Up Timer Stop command is given, the Wake Up Timer shall stop
counting and hold the value until Wake Up Timer Start command is given again. While the
counter is counting the EOT_STATUS will be 1. If it's not counting EOT_STATUS will be 0.

Wake Up Timer start/stop commands

Wake Up Timer counts up when msc start command in the MSC
WAKE_UP_TIMER_START_STOP register is given. When the msc stop command in the
MSC WAKE_UP_TIMER_START_STOP register is given the timer shall stop counting up
but hold the WAKE_UP_TIMER_CNT Register. The bit can be set or reset via MSC.

WAKE_UP_TIMER_CNT Register
WAKE_UP_TIMER_CNT Register consists of 24 bits it's Read Only. The range of
WAKE_UP_TIMER_CNT is from 0 (h'000000) to 16777215 (h'FFFFFF).
WAKE_UP_TIMER_CNT Register is set to 0 (h'00000) when power on reset of VB_STBY
occurs. WAKE_UP_TIMER_CNT Register is set to all "0" via MSC when power on reset
period or VB_STBY is open.

Wake up timer_SET time register

The Wake up timer_SET register consists of 24 bits. And the register is Read and Write register.
The range of Wake up timer_SET is from 0 (h'000000) to 16777215 (h'FFFFFF). Wake Up
Timer_SET Register is set to 0(h '000000) when power on reset of VB_STBY occurs.

EOT function 1
EOT Function 1 - count “stand” time: After the start of the counter, the counter starts to count
up till the value that has to be set before starting it using Wake_up_timer_SET. If ECU
switches on before the counter reaches the wake up timer_set value, the µC can read the
“stand” time via MSC. If the counter reaches the wake up timer_set value before ECU
switches on, the count keeps the wake up timer_set value.
This function is selected with MSC CONFIG_REG6[6]=EOT_MODE=0. The EOT function 1
does not set WAKE_UP_EOT_DET at 1. EOT_MODE bit can be correctly read only when
wake up timer logic is working, else it is read 0.
VB_STBY must be provided to correctly read the EOT_MODE bit. If VB_STBY is removed
the register content will be lost.

EOT function 2
EOT Function 2 - wake-up via WAKE_UP_TIMER_SET. Set WAKE_UP_TIMER_SET
(CONFIG-REG15-0 / CONFIG-REG15-1/ CONFIG-REG15-2) to a certain value, then start
the counter before shutting down the ECU. The counter counts up until the
WAKE_UP_TIMER_SET is reached. The reaching of WAKE_UP_TIMER_SET activates the
wake signal and will start a wake-up sequence. This function is selected with MSC
CONFIG_REG6[6]=EOT_MODE=1. EOT_MODE bit can be correctly read only when
wake-up timer logic is working, else it is read 0.
VB_STBY supply must be provided to correctly read the EOT_MODE bit.

34/264 DS12308 Rev 4

L9788 Operation behavior

Figure 7. Wake up timer block diagram

STBY block
STBY
V3V3 regulator
Wake Up Timer Register
(read only)
comparator
Oscillator
32KHz Wake Up SET Timer Register
(read and write)

Wake Up Timer
internal
RC
MSC Register in STBY block

MSC Register in VB block

Main Relay Driver

VB block

GADG2411161451PS

Table 12. Wake up timer resolution

range resolution

0 - 16777215 1 second

WAKE_UP_TIMER_CNT Register can be read via MSC. Wake up timer_SET Register can
be read and write via MSC.

3.1.8 Power on with PHOLD_EN (EOT function 3)

The chip is kept switched on by an MSC command (PHOLD_EN CONFIG_REG1[0]) even
though one of the power down sources has been asserted (KEY_IN, WK_IN,
WAKE_UP_TIMER, WAKE_UP_CAN). The chip is kept on in power hold mode for a time
programmed (default is infinity) by MSC (PHOLD_TIME[0:1] CONFIG_REG1 (D1;D2)). This
is also EOT function 3. The power hold mode is enabled by MSC and is cleared by the
conditions reported in the reset matrix.
After setting the PHOLD_EN=CONFIG_REG1[0]=1 the PHOLD and the PHOLD timer are
enabled when the KEY_DET, WK_IN_DET, WAKE_UP_EOT_DET, WAKE_UP_CAN_DET
detections are not active. The PHOLD_TIMER[14:0]=READ12.FRAME[2:1] starts counting
when the KEY_DET, WK_IN_DET, WAKE_UP_EOT_DET, WAKE_UP_CAN_DET
detections are cleared. When the PHOLD_TIME=CONFIG_REG1[2:1] is configured as 00
(default) the timeout is disabled and the PHOLD_TIMER[14:0]=READ12.FRAME[2:1] is
read always at 0.

DS12308 Rev 4 35/264

263
Operation behavior L9788

Figure 8. Power hold diagram

KEY_IN_DET
WK_IN_DET
WAKE_UP_EOT_DET
WAKE_UP_CAN_DET

ON (2) OFF ON OFF ON OFF

CHIP STATUS

PHOLD_EN (2) (4)

MSC_CONFIG_REG1[0]

PHOLD_TIMEOUT
MSC_CONFIG_REG1[2:1] 10
01

PHOLD_STATUS
(2) (4)
MSC_READ12_FRAME1[0]

timeout (3)

PHOLD_COUNTER (1) (2) (5)

(internal counter)

t
POWER HOLD FUNCTION

(1) The timeout counter is cleared on the detection of at least one of the power up sources.
(2) The timeout counter is cleared if MSC disables the PHOLD function, MRD is switched off, a power down sequence is started.
(3) The counter has reached the timeout, MRD is switched off, a power down sequence is started.
(4) The PHOLD_EN and the PHOLD_STATUS bits are clear along with the power down sequence.
(5) A new MSC setting for the timeout makes the timeout counter clear and restart.
GADG2411161503PS

36/264 DS12308 Rev 4

L9788 Operation behavior

3.1.9 Power down from WAKE_UP_TIMER when PHOLD_EN=0

The chip is powered down if the MSC clears, by the MSC command WAKE_UP_EOT_RST,
WAKE_UP_EOT_DET (The counter counts up until the WAKE_UP_TIMER_SET is
reached) if no other power up source is active and PHOLD_EN = 0. The detection reset by
MSC command, WAKE_UP_EOT_RST=CONFIG_REG12[6], is active at level not at
change, so from when MSC writes them at 1 they keep on clearing the detections. If there is
further wake detection signal, the detection signal will be cleared, until the MSC writes 0 in
the bits.

3.1.10 Power down from PHOLD

The chip is powered down after the power hold timer programmed by MSC has expired or if
the PHOLD function is disabled by MSC. The PHOLD timer can be programmed as timeout
disabled so that the chip stays powered up.

3.1.11 Power up from CAN

The chip can be powered up from CAN according to what reported in the Wake Up (From
CAN) chapter. To allow the power up from CAN the pins VB_CAN, VB_STBY must be
supplied. In case the power up of the chip is not completed in a MRD_EN_TIMEOUT from
CAN valid pattern detection the Main Relay Driver is switched off and the chip goes in OFF
state
When U chip is already in on state (the logic is out of power on reset), the validation of a
valid CAN pattern only sets a flag, with no impact on power supply. This flag is named
WAKE_UP_CAN_DET (detection of a valid can pattern) and is cleared by VDD5/VDDIO
under voltage or by the MSC command WAKE_UP_CAN_RST. In this case if no other
power on source is active a power down sequence is started.
The Main Relay Driver is not switched on by WAKE_UP_CAN if the device is powered in
permanent battery.

3.1.12 Power down from WAKE_UP_CAN when PHOLD_EN=0

The chip is powered down if the MSC clears, by the MSC command WAKE_UP_CAN_RST,
WAKE_UP_CAN_DET (the detection of WAKE_UP_CAN high) if no other power up source
is active and PHOLD_EN = 0. The detection reset by MSC command,
WAKE_UP_CAN_RST=CONFIG_REG12[5], is active at level, so from when MSC writes
them at 1 they keep on clearing the detections. If there is further wake detection signal, the
detection signal will be cleared, until the MSC writes 0 in the bits.

3.1.13 Finish wake function

There is a Finish wake function (auto clear mechanism) of WK_IN_DET,
WAKE_UP_EOT_DET and WAKE_UP_CAN_DET. The purpose is to ensure the system
could power down from wake up state after the impulse timer timeout (typ. 1s).
If the software does not stop the impulse timer before time out, the WK_IN_DET,
WAKE_UP_EOT_DET and WAKE_UP_CAN_DET will be cleared as long as time out. If the
software stops the impulse timer (FIN_WAKE = 1) before time out, the WK_IN_DET,
WAKE_UP_EOT_DET and WAKE_UP_CAN_DET will not be cleared.
The impulse timer is not affected by watchdog(ERR_CNT>4) and EOT. The Finish wake
function is not disabled by RSTN pulled low externally and MSC_SW_RESET active. The

DS12308 Rev 4 37/264

263
Operation behavior L9788

Finish wake function can be disabled by power supply undervoltage. The reset sources of
FIN_WAKE bit are the same as fin_wake function.
Software can decide to clear the WK_IN_DET, WAKE_UP_EOT_DET or
WAKE_UP_CAN_DET before or after the impulse timer timeout, through set WK_IN_RST,
WAKE_UP_EOT_RST or WAKE_UP_CAN_RST to 1
FIN_WAK function is stopped by
1. FIN_WAKE time out,
2. FIN_WAKE BIT =1,
3. WK_IN_RST / WK_EOT_RST /WK_CAN_RST of relevant detect signal.
When WK_IN_DET & WK_EOT_ DET &WK_CAN_ DET =0, FIN_WAK can be re-triggered
by any detection of WK_IN_DET / WK_EOT_ DET /WK_CAN_ DET. The counter is
restarted from 0.

Figure 9. Impulse timer clear WAKE_IN_DET after time out

WK_IN pin

WAKE_IN_DET

Impulse timer

Tfin_wk

The time out of impulse timer

clears the WAKE_IN_DET
GADG1403171445PS

Figure 10. Impulse timer disabled before time out

WK_IN pin

WAKE_IN_DET

Impulse timer

Tfin_wk
MSC
MSC Command to stop
the impulse Counter
GADG1403171500PS

38/264 DS12308 Rev 4

L9788 Operation behavior

Figure 11. Timer enabled for a new detection

WK_IN pin

WAKE_CAN_DET

WAKE_IN_DET

Impulse timer
Tfin_wk Tfin_wk

The time-out of impulse timer

clears the WAKE_IN_DET GADG2511160723PS

Note: Same mechanism applied to WAKE_IN_DET, WAKE_UP_EOT_DET and

WAKE_UP_CAN_DET.

Table 13. Finish wake timer electrical characteristics

Symbol Parameter Min Typ Max Unit

Tfin_wk Finish wake timer 0.94 1 1.06 s

3.2 Secure Engine Off (SEO) function

Secure Engine Off functional switches off, with a certain delay from KEY_OFF, the engine
by a hardware path and without any dependence on external micro and no matter what are
the other conditions (e.g. the power hold mode).
After the falling edge of the filtered KEY_IN a programmable counter is started. The clock of
the timer does not depend on any micro clock or function.
SEO_OUT pin is the output of KEY_IN after a T_SEO_DELAY (CONFIG_REG3 [6:7])delay.
Input pin INJ_ENA enables the internal drivers as listed above (INJ[1:4], is configured), so
the configuration of enable/disable of SEO function is realized by hardware in the following
way:
For PFI application, SEO_OUT is connected to INJ_ENA, when key goes off internal drivers
can be switched off.
For GDI application, SEO_OUT is connected to GDI injector driver enable if present,
INJ_ENA is always enabled. When key off, only the external GDI injector driver is switched
off.
During SEO time the external micro can switch on/off the drivers
SEO output is implemented with a push pull output stage, the T_SEO_DELAY can be
programmed according to Table 14.

DS12308 Rev 4 39/264

263
Operation behavior L9788

Table 14. SEO timing

Symbol Parameter MSC_CONF Min Typ Max Unit Pin

T_SEO_DELAY default 00 100 - 140 ms SEO_OUT

T_SEO_DELAY - 01 200 - 250 ms SEO_OUT
T_SEO_DELAY - 10 400 - 480 ms SEO_OUT
T_SEO_DELAY - 11 800 - 920 ms SEO_OUT

Condition:
5.5 V ≤ VB_IN ≤ 18 V, 4.75 V ≤ VDD_IO ≤ 5.25V, Tj -40 to 175 °C unless otherwise
specified.

Table 15. SEO Circuit electrical characteristic

Symbol Parameter Test condition Min Typ Max Unit Pin

SEO_OUT
VDDIO = 5 V or 3.3 V
SEO_OUT_L output low - - 0.5 V SEO_OUT
Isink current = 2 mA
level
SEO_OUT VDDIO = 5 V or 3.3 V VDDIO
SEO_OUT_H - - V SEO_OUT
high level Isink current = 2 mA -0.5

Figure 12. SEO delay

KEY

VDD5

VDDIO

SEO_OUT T_SEO_DELAY

GADG2511160800PS

40/264 DS12308 Rev 4

 3.3 Reset strategies

L9788
Figure 13. Reset table

VB_STBY
SUPPLY DOMAIN WAKE_UP_EOT V3V3 BUCK 6V REG 5V V3V3D TRACK 5V
WAKE_UP_CAN
afterrun
WATCHDOG EN_P FAULT
VB_STBY VB_IN/VB_IN_SW V3V3A V3V3D VPRE VDD5 VDDIO OSC GND WDA_QA MSC_ACT SW_RESET reset RSTN (IN)
internal reset EN_N WARNING
active

WDA_CNT_RST

WDA_REG_RST
PWR_CNT>7
EVENT OV OV
UV UV OV UV OV UV OV UV UV FAULT LOSS WDA(IN) ERR_CNT>4 ERR_CNT>7 and IN IN OV/UV

RST_PRL
t>tTBOV2 tTBOV1<t<tTBOV2
KEY_IN=0

MSC en/dis (for BUCK, VDD5, TRK) MSC MSC

MSC en/dis BID PIN MSC en/dis BID PIN
VB_IN_OV_RST_EN wda_init=1 en/dis

TRK[1:4]_OV/UV
(POWER LOSS)
VB_STBY_UV

power_down
VDD5_RST
V3V3D_UV
V3V3D_OV

V3V3A_UV
V3V3A_OV
VB_IN_UV
VB_IN_OV

VB_IN_OV

WDA_RST
VDD5_OV
VPRE_OV

TRANS_F
VPRE_UV

WDA_INT
VB_STBY FLAG READ BY MSC

VB_STBY x ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż

wake_up_timer(EOT) Ÿ no rese t ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż
KEY_IN_DET ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż ż
POWER HOLD ż ż ż ż Ÿ Ÿ ż ż Ÿ Ÿ Ÿ ż ż ż Ÿ Ÿ ż Ÿ Ÿ ż ż ż Ÿ ż ż ż
WAKE_IN_DET/WAKE_UP_E
OT_DET/WAKE_UP_CAN_DET ż ż ż ż ż ż ż ż ż Ÿ Ÿ ż ż ż ż Ÿ ż ż ż ż ż ż ż ż ż ż

V3V3 V3V3A V3V3D ż ż ż ż x x ż ż ż ż ż ż ż ż ż Ÿ ż ż ż ż ż ż ż ż ż ż

BOOST ż - - Ÿ Ÿ Ÿ ż Ÿ ż ż ż ż ż ż ż Ÿ ż ż ż ż ż ż ż ż ż ż
BUCK ż Ÿ ż Ÿ Ÿ Ÿ x x ż ż ż ż ż ż ż Ÿ ż ż ż ż ż ż ż ż ż ż
VCP ż Ÿ ż ż Ÿ Ÿ ż ż ż ż ż ż ż ż ż Ÿ ż ż ż ż ż ż ż ż ż ż
DS12308 Rev 4

VDD5 VDD5(5V) ż Ÿ ż Ÿ *1 5 Ÿ Ÿ ż Ÿ x x x ż ż ż ż Ÿ ż ż ż ż ż ż ż ż ż ż
TRACK 5V TRACK(5V) ż Ÿ ż Ÿ Ÿ Ÿ ż ż ż ż ż ż ż ż ż Ÿ ż ż ż ż ż ż ż ż ż x
WDA (OUT) - - - - - - - x - ż ż - - -
WDA sequence ż ż ż ż Ÿ Ÿ ż ż Ÿ Ÿ Ÿ ż ż ż ż Ÿ ż ż ż ż Ÿ ż ż ż ż ż
WDA error counter ż ż ż ż Ÿ Ÿ ż ż Ÿ Ÿ Ÿ ż ż ż Ÿ Ÿ ż Ÿ Ÿ Ÿ ż ż Ÿ ż ż ż
WDA power down counter ż ż ż ż Ÿ Ÿ ż ż Ÿ Ÿ Ÿ ż ż ż ż Ÿ ż INC+1 ż ż Ÿ ż ż ż ż ż
WDA reset counter ż ż ż ż Ÿ Ÿ ż ż Ÿ Ÿ Ÿ ż ż ż ż Ÿ ż ż ż ż Ÿ ż ż ż ż ż
WDA WDA question register ż ż ż ż Ÿ Ÿ ż ż Ÿ Ÿ Ÿ ż ż ż ż Ÿ ż ż ż ż Ÿ ż ż ż ż ż
WDA config register ż ż ż ż Ÿ Ÿ ż ż Ÿ Ÿ Ÿ ż ż ż Ÿ Ÿ ż Ÿ Ÿ Ÿ ż Ÿ Ÿ ż ż ż
WDA diagnostic register ż ż ż ż Ÿ Ÿ ż ż Ÿ Ÿ Ÿ ż ż ż ż Ÿ ż ż ż ż Ÿ ż ż ż ż ż
RST_PRL - - - - - - ż - - - x - - - - -
WDA_CNT_RST - - - - - - - - - - - - - - x - - - - -
WDA_REG_RST - - - - - - - - - - - x - - -
afterrun reset enable bit (TNL)
ż ż ż ż Ÿ Ÿ ż ż Ÿ Ÿ Ÿ ż ż ż ż Ÿ ż ż ż ż ż ż ż ż ż ż
(default enabled )
MSC communication*5 ż ż ż ż Ÿ Ÿ ż ż Ÿ Ÿ Ÿ ż ż ż Ÿ Ÿ ż ż Ÿ ż ż ż Ÿ ż ż ż
VB

MSC MSC_ACT ż ż ż ż Ÿ Ÿ ż ż Ÿ Ÿ Ÿ ż ż ż ż Ÿ x ż ż ż ż ż ż ż ż ż
MSC REGISTERS*14 ż ż ż ż Ÿ Ÿ ż ż ż Ÿ Ÿ ż ż ż ż Ÿ ż Ÿ Ÿ ż ż ż Ÿ ż ż ż
FIN_WAKE ż ż ż Ÿ Ÿ ż ż ż Ÿ Ÿ ż ż ż ż Ÿ ż ż ż ż ż ż ż ż ż ż
RSTN (OUT) - - - - - - - - - - ż ż x - - -
RSTN (OUT) pull down time Td_UV_RST Td_UV_RST Td_UV_RST Td_UV_RST Td_UV_RST Td_UV_RST Td_UV_RST TWDA_RST TNL_RST
RSTC (OUT) - - - - - - - - - - - - - - - - ż ż - - - -
FAULT WARNING - - - - - - - - - - - - - - - - - ż ż - x x -
MRD ż ż ż ż Ÿ Ÿ ż ż ż ż ż ż ż ż ż Ÿ ż ż ż ż ż ż ż ż ż ż
INJ[1:4] ż Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ ż ż ż
O2H[1:2] ż Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ ż ż ż
SOL[1:2] ż Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ ż ż ż
RLY[1:5] ż Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ ż ż ż
LED[1:2] ż Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ ż ż ż
HSD/LSD[1:2:3] ż Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ ż ż ż
RLY4 STR[2:3] *7 ż Ÿ Ÿ ż Ÿ Ÿ ż ż ż ż ż Ÿ ż Ÿ*1 1 Ÿ*1 1 Ÿ ż Ÿ Ÿ Ÿ ż ż ż Ÿ*1 6 Ÿ ż
DELAY OFF FUNCTION - - - - - - - - - - - - - - - - ż ż - - -
PRD[1:5] ż Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ ż ż ż
IGN[1:6] ż Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ ż ż Ÿ ż ż ż
K/LIN ż Ɣ *9 ż Ÿ Ÿ Ÿ ż ż Ɣ *9 Ɣ *9 Ɣ *9 Ɣ *9 ż Ɣ *8 Ɣ *8 Ÿ ż ż Ɣ *9 Ɣ *8 ż ż Ɣ *9 ż ż ż
VRS ż Ÿ ż Ÿ Ÿ Ÿ ż ż Ÿ Ÿ Ÿ Ÿ ż ż ż Ÿ ż ż Ÿ ż ż ż Ÿ ż ż ż
CAN Ɣ *1 3 Ɣ *1 3 ż Ɣ *1 3 Ɣ *1 3 Ɣ *1 3 ż ż Ɣ *1 2 Ɣ *1 3 Ɣ *1 3 Ɣ *1 2 ż Ɣ *1 0 Ɣ *1 0 Ÿ ż ż Ɣ *1 2 Ɣ *1 0 ż ż Ɣ *1 2 ż ż ż

x detection *5 At the rising edge of reset, the MSC communication is reset. un-sent up stream frame should be discard.
ż normal operation *6 SEO_OUT is triggered by KEY_IN=0

Operation behavior
- not active *7 RLY4 and STR[2:3] are MSC configured as starters (CONFIG3[0]=CONFIG3[4:5]=1)
Ɣ partial functionality *8 LIN works as receiving mode only (if the disable of the transmitting mode is enabled by MSC)
stop/reset *9 LIN works as receiving mode only
active due to watchdog BOSCH IP the WDA_ERR_CNT can be reset if also RST_PRL is activated
*10 CAN works as receiving-only mode only if bit CAN_TDI =1
*11 If the related delay off function is active the driver stays ON
*12 CAN works as receiving-only mode
*13 CAN works as Low-power mode
*14 excluded WAKE_UP_TIMER_START_STOP, EOT_MODE, CAN parameters, WAKE_UP_TIMER_EN_SEL, KEY_OC_RERTY_MAX_EN
*15 When VDD5_OFF_SEL=1, VDD5 does not depend on VB_IN UV. If VDD5_OFF_SEL=0, VDD5 depends on VB_IN UV
*16 RLY4 and STR[2:3] are stop by EN_N/EN_P if they are configured or not as starter

GADG2511160811PS
41/264

Note: When VB_STBY_UV happens, it stops the EOT counter.The EOT counter will resume when vb_stby_uv goes low (no undervoltage).
Operation behavior L9788

3.4 Smart reset circuit

There are two Reset pins:
1. RSTN: reset pin linked to VDD5 supply;
2. RSTC: reset pin linked to VDDIO supply.

3.4.1 Smart reset RSTN pin

The RSTN pin is an input/output active low. As output pin the Smart Reset circuit takes into
account several events in the device in order to generate the proper reset signal at RSTN
pin for the microcontroller and for portion of the internal logic as well.
The RSTN in output (RSTN(OUT) is activated by the contributions described by the reset
matrix and is intended as reset for the external microcontroller.
The RSTN in input (RSTN(IN)) is filtered Trst_flt_RST and stops the internal logic as
described in the reset matrix.
The internal RSTN(OUT) has higher priority respect to the external RSTN(IN). The
RSTN(IN) is masked until Tmsk_RSTN after RSTN(OUT) has been released.
RSTN(OUT) and RSTN(IN) are recombined on the pad according to the scheme.

Figure 14. Reset circuit

RSTN(OUT)

100μs RSTN pin

RSTN(IN)
0
1

GADG2511160825PS

The RSTN activates on the contributions specified by the reset matrix:

Figure 15. Reset matrix

VDDIO

5 Nȍ

VDDIO uv = 0 pull up connected

VDDIO uv = 1 pull up disconnected
RSTC

Nȍ
LOGIC

VDDIO uv = 0 LS OFF
VDDIO uv = 1 LS ON

GADG2511161010PS

42/264 DS12308 Rev 4

L9788 Operation behavior

3.4.2 Smart Reset RSTC pin

The RSTC pin is an output active low. As output pin the Smart Reset circuit takes into
account several events in the device in order to generate the proper reset signal at RST pin
for the microcontroller and for portion of the internal logic as well.
The RSTC activates on the contributions specified by the reset matrix:

3.4.3 After run reset

Figure 16. RSTN/RSTC after run reset timing

WAKE_IN_DET or
WAKE_UP_EOT_DET or
WAKE_UP_CAN_DET or
PHOLD active

KEY_IN_DET
TNL

RSTN/RSTC

GADG2511161017PS

As output:
4.8 ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified;

Table 16. Smart reset circuit electrical characteristic table 1

Symbol Parameter Test condition Min Typ Max Unit Pin

VUV_LO RSTN Output low voltage 1 < VDD5 < VDD_UV - - 0.6 V RSTN
VUV_LO RSTC Output low voltage 1 < VDDIO< VDDIO_UV - - 0.6 V RSTC
VDD5 = VDD_UV
IUVres_max_RSTN Input current 1 - - mA RSTN
VUV_reset = 0,6V
VDDIO= VDDIO_UV
IUVres_max_RSTC Input current 1 - - mA RSTC
VUV_reset = 0,6V

As input:
4.8 ≤ VB_IN ≤ 18V, 4.5 ≤ VDD_IO ≤ 5.5 V, Tj -40 to 175°C unless otherwise specified;

Table 17. Smart reset circuit electrical characteristic table 2

Symbol Parameter Test condition Min Typ Max Unit Pin

RST_L RST input low voltage - -0.3 1.1 V RSTN

VDD_IO
RST_H RST Input high voltage - 2.3 V RSTN
+0.3
Trst_flt_RST Reset RST filter time Tested by scan 7.5 10 11.5 µs RSTN

DS12308 Rev 4 43/264

263
Operation behavior L9788

Table 17. Smart reset circuit electrical characteristic table 2 (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

RST pull up resistor +

RRST_PU RSTN / RSTC pins to 0V 0.95 - 2.5 kΩ RSTN RSTC
HS Ron
RSTN / RSTC pin to
RRST_PD RST pull down resistor 100 - 320 kΩ RSTN RSTC
VDDIO
TNL RST After run reset time - 1.4 2 2.6 ms RSTN RSTC
watchdog RST reset
TWDA_RST - 1.4 2 2.6 ms RSTN RSTC
time
Power on RST reset
Td_UV_RST - 17 - 30 ms RSTN/RSTC
delay
Masking time on
Tmsk_RST RST(IN) after - 95 100 105 µs RSTN
RTN(OUT) is released.

44/264 DS12308 Rev 4

 3.5 Thermal shutdown

L9788
Table 18. Thermal shutdown
Overtemperature flags

OVT[18] or OVT[19]
OVT[8] or OVT[9]

OVT[14]**
OVT[10]

OVT[12]

OVT[13]

OVT[15]

OVT[16]

OVT[17]
OVT[11]
Block

OVT[1]

OVT[2]

OVT[3]

OVT[4]

OVT[5]

OVT[6]

OVT[7]
REGULATOR BUCK ▲ ▲
REGULATOR VDD5, ▲
REGULATOR TRACK ▲ ▲
DS12308 Rev 4

DRIVER INJ1 ▲ ▲
DRIVER INJ2 ▲ ▲
DRIVER INJ3 ▲ ▲
DRIVER INJ4 ▲ ▲
DRIVER O2H1 ▲ ▲
DRIVER O2H2 ▲ ▲
DRIVER SOL1 ▲ ▲
DRIVER SOL2 ▲ ▲
DRIVER RLY[1:2] ▲ ▲
DRIVER RLY[3:5] ▲ ▲

Operation behavior
DRIVER MRD ▲ ▲
DRIVER STR[1:3] ▲ ▲
DRIVER LED[1:2] ▲
LIN ▲ ▲
45/264

VRS ▲
Operation behavior L9788

Legenda:
▲ Shutdown
<blank> Not shutdown
OVT[1-16] Dedicated temperature sensor for the power
OVT[3] OVT[3] is used as a common thermal sensor for the three Tracking Regulators
OVT[17] Central Temperature sensor
OVT[14]** Over temperature protection MRD is available only when VB_IN is present.

46/264 DS12308 Rev 4

L9788 Watchdog

4 Watchdog

4.1 Basic feature

L9788 has an internal query and answer (Q&A) watchdog with the aim of monitoring the
correctness of microcontroller activity. Via MSC bus a WDA “question” shall be read from a
MSC-WDA register. A correct response shall then be written back via MSC in a well defined
timing. If response or timing is not correct, then the WDA error counter EC (or ERR_CNT) is
increased. If the error counter is increased to values greater than 4, some output functions
are shut off. If the error counter reaches values greater than 7 (overflow), then a RST reset
may be generated if this is previously configured via MSC.
The first sequence of questions and responses starts from VDD5 higher than the UV
threshold.
Other way round, with a RST event also the WDA output pin goes to low.
Note that after startup, reset or an RST_CNT overflow the initial value of the error counter is
6.
If WDA resets are enabled via MSC (WDA_INIT CONFIG-REG 9_1 D3): the number of RST
events generated by an error counter overflow is limited by the reset counter RST_CNT. If
RST_CNT reaches the value of 7, then RST resets via WDA are no longer generated.
With each error counter overflow, the PWR_CNT counter is increased. If it reaches a value
greater than 7, then the power latch mode is terminated.
Watchdog legenda:
ERR_CNT, EC error 3-bit counter;
RST_CNT reset 3-bit counter;
WDA_RST internal reset generated by Watchdog;
PWR_CNT power off 3-bit counter;
PWR_INT internal signal indicating PWR_CNT overflow;
WDA WDA open drain pin (low active);
WDA_INT WDA internal signal, when high it drives WDA = low, when low it sets
WDA= Hi-z;
Sequencer-run current state of WDA when it is active.

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263
Watchdog L9788

4.1.1 Monitoring module - WDA Functionality

Figure 17. WDA block diagram

Depending on MSC configuration CAN

is disabled in WDA case or not
MSC CONFIG
VDD

& CAN
disable

inhibit WDA
>1 100μs

RST

WDA_INT •
Error counter

EC > 4 RST_CNT

EC > 7 PWR_CNT

Injection
disable drivers

Ignition
disable drivers

Other
disable drivers

GADG2511161150PS

Note: Delay-off function is not considered in this Block Diagram.

48/264 DS12308 Rev 4

L9788 Watchdog

Figure 18. WDA state flow

Power
Down

Power On and Reset release

RST_CNT = 0 PWR_CNT > 7
PWR_CNT = 0
yes
yes
Safety loads = disabled
no
WDA pin = Low ERR_CNT = 6 KEY OFF?

Answer0 Answer1
no
Configure WDA Time Window and ERR_CNT > 7
Request first Query no
WDA Sequencer starts yes
Write Answer
Increment ERR_CNT Increment PWR_CNT (max 7)

Right
Answer ?
WDA Time Reference no
(Typ 64 kHz +/-5%)
yes

Generate next Query yes

RST_CNT =7

no
Decrement ERR_CNT

no INIT_WDR=1 ?
ERR_CNT < 5
no
yes yes
Safety Loads = Enabled
WDA pin = High
RST_CNT = 0 Increment RST_CNT
PWR_CNT = 0

Request for Query

Generate Reset
Drive RST pin to Low
GADG2511161203PS

Each time the watchdog error counter is EC > 7 counter PWR_CNT counter increases.
When this counter is PWR_CNT=7 and a further error occurs, the power-latch will be
terminated if KEY_IN is low. The PWR_CNT-counter is not cleared when EC <7.
PWR_CNT-counter is cleared when EC < 5 or by RST_UV.
The monitoring module works independently of the controller functionality. The monitoring
module generates various questions, which the controller must fetch and correctly respond
to within a defined time window. The monitoring module checks whether the response is
returned in a time window and if the response is fully correct.
The question is a 4-bit word. This 4-bit word can be fetched by the controller using a read
access to register WDA REQULO. The monitoring module also calculates the expected
correct response, which is compared to the actual response from the controller.
The response is a 32-bit word consisting of the 4 bytes RESP_BYTE3, RESP_BYTE2,
RESP_BYTE1 and RESP_BYTE0. The 4 bytes are sent to the monitoring module via MSC
in the order RESP_BYTE3 - RESP_BYTE2 - RESP_BYTE1 - RESP_BYTE0 using four
times the command WDA_RESP - once for each answer byte.
The monitoring cycle phase is initialized by (the end of) writing of RESP_BYTE0 (least
significant response byte) or by a write access to the RESPTIME register. The cycle starts
with a variable wait time (response time, set by register RESPTIME), followed by a fixed
time window. When a monitoring cycle ends (the end of the fixed time window has been
reached) a new monitoring cycle is started automatically.
A correct response within the time window (at a response time > 0 ms) decreases an
ERROR COUNTER by one. An incorrect response, a response outside the time window or
response time = 0 ms leads to the incrementing of the ERROR COUNTER by one.

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263
Watchdog L9788

"… within the time window" means that the end of writing the last answer byte - i.e.
RESP_BYTE0 - falls into the fixed time window mentioned above (see picture below).
Except the last answer byte, the previous answer bytes may also be written earlier than the
beginning of the fixed time window.
The question sequence is deterministic. A question will be repeated until it is answered
correctly both in value and in time. Then the next question is placed in the sequence.
The ERROR COUNTER (EC) is a 3-bit counter. Various actions are activated depending on
the value of the counter.
The result of the comparison of the controller response and the calculated correct response,
as well as the next question, are available in registers REQULO after receiving the µC
response (LSB of RESP_BYTE0) and can be read by the controller.

Figure 19. Monitoring cycle diagram

1.6 ms < response time window < 100.8 ms @ 64 kHz ±5% time window = 12.8 ms @ 64 kHz ±5%

start monitor cycle CPU response

end of writing RESP_BYTE0
starts next monitor cycle
GADG2511161221PS

4.1.2 ERR CNT (EC) and reactions, PWR COUNTER (PWR_CNT) and
generation of the monitoring module reset
Various actions are initiated for specific counter states of the ERROR COUNTER EC. The
counter reset state is 6.
For ERROR COUNTER (EC) > 4, the open drain output WDA is pulled low (active).

Table 19. Error counter

Overflow
ERR_CNT 0…4 5 6…7
ERR_CNT > 7

WDA Hi-Z Low Low Low

PWR_CNT 0 unchanged unchanged Incremented by 1

If PWR_CNT = 7 PWR_CNT < 7 Low (inactive)

If PWR_CNT = 7 and
Internal and ERR_CNT PWR_CNT 6->7 Low
Low (not ERR_CNT increase
PWR_CNT active) increase => High (inactive)
=> High (active)
signal (active) PWR_CNT 7 -> 7 High
Else unchanged
Else unchanged (active)

If the ERROR COUNTER reaches the value “7” and a further error occurs the PWR_CNT is
incremented by one during a sequencer-run.
The state "EC = 7 and a further error occurs" is also called ERROR COUNTER overflow
("EC" > 7).

50/264 DS12308 Rev 4

L9788 Watchdog

The counter PWR_CNT is a 3 bit counter.

Behaviour of PWR_CNT:
 asynchronous reset to "000" with RST_UV
 synchronous reset to "000" IF (EC < 5)
 IF (PWR_CNT < 7) AND (sequencer-run AND "EC" > 7) THEN PWR_CNT =
PWR_CNT + 1 ELSE unchanged.
The counter cannot be decremented and can be only reset to "000" by an active RST_UV
signal (asynchronous) or <WDA_INT> = '0' (synchronous).The signal PWR_INT becomes
active '1' when PWR_CNT = "111" and a further error is detected. When KEY_IN =0, the
active PWR_INT signal causes a shut-down of the main relay and the voltage regulators.
This function ensures a secure shutdown of the system in an error state of the µC in "power-
latch". Signal PWR_INT is set to '0' again only when <WDA_INT> = '0'.

4.1.3 Generation of a monitoring module reset

The monitoring module may cause a reset at the pin [RSTN] named "monitoring module
reset" in conjunction with the internal signal WDA_RST. The generation of a monitoring
module reset depends on the state of the bit <WDA_INT>.
< WDA_INT> = '0' (reset state):
If < WDA_INT> = '0', the signal <WDA_RST> remains always inactive '0' and the monitoring
module can never generate a reset. The error counter can only be decremented via correct
responses. If < WDA_INT> = '0' the state of the reset counter <RST_CNT> remains
unchanged when an ERROR COUNTER overflow occurs (description of the reset counter
<RST_CNT> see below).
< WDA_INT> = '1':
If < WDA_INT> = '1', an ERROR COUNTER overflow activates a reset [RST] (signal
<WDA_RST> becomes active). The signal <WDA_RST> becomes active (i.e. '1') due to an
ERROR COUNTER overflow when the value of the 3 bit reset counter <RST_CNT(2-0)> is
0..6. If the value of <RST_CNT> = "111" and an ERROR COUNTER overflow occurs
<WDA_RST> remains inactive (i.e. '0') and no reset is generated. The "reset counter"
<RST_CNT> is incremented by one during a sequencer-run due to an ERROR COUNTER
overflow when < WDA_INT> = '1' and <RST_CNT> is between 0 and 6. If <RST_CNT> = 7
and an ERROR COUNTER overflow occurs, the counter state remains 7. The counter can
not be decremented and can only reset to zero by an active RST_UV signal. The
occurrence of a monitoring module reset is indicated via the flag <WDA_RST> = '1'.
Reading the flag via MSC clears it automatically. In effect maximum 7 monitoring module
resets can be generated between 2 active RST_UV signal. (see also state table for <
WDA_INT> = '1' below).The state of the "reset counter" <RST_CNT> can be read via MSC
but cannot be changed.

Table 20. Internal states for WDA_INIT=1

RST_CNT old value EC>7 and sequencer-run RST_CNT new value WDA_RST

000 … 111 False = RST_CNT old 0, no monitoring module reset

1, monitoring module reset
000 … 110 True = RST_CNT old + 1
generated
111 True = 111 0, no monitoring module reset

DS12308 Rev 4 51/264

263
Watchdog L9788

4.1.4 Question generation

The generation of the 4-bit question (REQU[3-0]) is realized as in the table below. The 4-bit
counter only changes to the next state during the sequencer-run when the previous
question has been answered correctly in value and in time. The state is changed by a
sequencer-run because of a write-access to the RESPTIME register or the expiration of the
time window.
When RST_UV is active the state is set to 0000b

4.1.5 Response comparison

The 2-bit counter <RESP_CNT (1-0)> counts the received bytes of the 32-bit response and
controls the generation of the expected response. Its default value is "11" (corresponds to
"waiting for RESP_BYTE3").
The <RESP_ERR> flag is set '1' when a response byte is incorrect. The flag remains '0' if
the 32-bit response is correct. The ERROR COUNTER is updated with the flag. The default
state of the flag is '0'.
The 2-bit counter <RESP_CNT (1-0)> and the <RESP_ERR> flag are reset to their
corresponding default values at a sequencer-run. The reset condition of the counter
<RESP_CNT (1-0)> and the <RESP_ERR> flag are the corresponding default states.
Procedure of the sequential response comparison:
<RESP_CNT (1-0)> = "11": switch the expected response for RESP_BYTE3 to the
comparator
Write access: RESP_BYTE3
Set <RESP_CNT> to "10", update <RESP_ERR> flag
<RESP_CNT (1-0)> = "10": switch the expected response for RESP_BYTE2 to the
comparator
Write access: RESP_BYTE2
set <RESP_CNT> to "01", update <RESP_ERR> flag
<RESP_CNT (1-0)> = "01": switch the expected response for RESP_BYTE1 to the
comparator
Write access: RESP_BYTE1
set <RESP_CNT> to "00", update <RESP_ERR> flag
<RESP_CNT (1-0)> = "00": switch the expected response for RESP_BYTE0 to the
comparator
"update <RESP_ERR> flag" previously described means that it sets <RESP_ERR> flag to 1
if a response byte is incorrect. Once <RESP_ERR> flag is set to 1 it maintains its value until
next sequencer run.
Write access: RESP_BYTE0
Start sequencer (SEQU_START signal), set <RESP_CNT> to "11", update <RESP_ERR>
flag, update ERROR COUNTER
Sequencer clears <RESP_ERR> flag to '0
SEQU_START = (RESP_CNT1=0) AND RESP_CNT0=0) AND "response byte write"

52/264 DS12308 Rev 4

L9788 Watchdog

Table 21. Question and answer

question REQU (3-0) RESP_BYTE3 RESP_BYTE2 RESP_BYTE1 RESP_BYTE0

0 FF 0F F0 00
1 B0 40 BF 4F
2 E9 19 E6 16
3 A6 56 A9 59
4 75 85 7A 8A
5 3A CA 35 C5
6 63 93 6C 9C
7 2C DC 23 D3
8 D2 22 DD 2D
9 9D 6D 92 62
A C4 34 CB 3B
B 8B 7B 84 74
C 58 A8 57 A7
D 17 E7 18 E8
E 4E BE 41 B1
F 01 F1 0E FE

4.1.6 Reset behaviour

All monitoring module registers are reset by RST_UV. The following monitoring module
components are also reset by RST_PRL (internal partial reset).

Table 22. Watchdog reset behaviour

Component Reset Condition

ERROR COUNTER 110b

Register for “EC>7” ‘0’
Register RESPTIME Maximum value:0011 1111b

RST_PRL is active when at least one of the following signals is active: RSTN or SW_RST.

DS12308 Rev 4 53/264

263
Watchdog L9788

4.1.7 Access during a sequencer-run

A sequencer-run (which means the same as a monitoring cycle) is initiated by the writing of
a response (i.e. all answer bytes <RESP_BYTE3..0>) or a write to <RESPTIME> or by
reaching "end of time window". It's not interrupted by a new access, i.e. the monitoring
module completes the action already started:
 A sequencer-run was initiated by a "response write": The sequencer completes its task
with the data of the previous access and the new data are ignored.
 A sequencer-run was initiated by a "response-time write": The sequencer uses the
response-time of the previous access, the error counter is correspondingly
incremented by one and the <CHRT> bit (REQUHI register) is set and the new data are
ignored. <CHRT> will be reset by reading and by the next start of a sequencer run (not
reset by the sequencer run that is started by a "response-time write")
 A sequencer-run was initiated by "end of time window": The sequencer finishes the
started run, the error counter is incremented by one and the new data are ignored.
The writing of a response-time during a sequencer-run will not set the <CHRT> bit (REQUHI
register). The new response-time value is also not accepted.
At the end of the sequencer run W_RESP bit is set to 0 if the response is correct, it is set to
1 if the response is incorrect.

4.1.8 Clock and time references

The monitoring module works independently by the micro-controller clock so that it can
monitor the timing of the micro-controller.
This oscillator is integrated in the U-chip and it provides a clock CLK1 for the monitoring
module.
Clocked with CLK1, a divider generates the base time of 1.6 ms @ 64 kHz for the response-
time and 8*1.6 ms = 12.8 ms @ 64 kHz for the fixed time window. Accuracy of CLK1 is ±
5%.
The response-time is adjustable by the controller in the range 0ms to about 100ms (register
RESPTIME).
The response-time can be calculated with the equation
Response_Time = RESPTIME [5:0]) *1.6 ms
If 39 kHz clock is selected by wda_win_sel configuration bit, the base time changes
becoming 2.6ms @ 39 kHz. This implies the change of all related timing values: 8*2.6 ms =
20.8 ms @ 39 kHz for the fixed time window and response time becomes RESPTIME [5:0]
*2.6 ms.
The WDA_RESPTIME (CONFIG_REG9_0) register is set to '0011 1111'b after a reset. The
ERROR COUNTER is incremented by one if the controller changes the response-time. If
the response-time is set to 0 ms, then the ERROR COUNTER is incremented by one even if
a correct response is received within the time window. The maximum error reaction time is
given by: maximum response-time, response at the end of a time-window and ERROR
COUNTER 0 Is 5 *(100.8 ms + 12.8 ms) = 568 ms.
In order to assure correct response write, there must be a minimum distance between 2
consecutive writes equal to 5us, this time does not depend on WDA_WIN_SEL
(CONFIG_REG9_1 D2).

54/264 DS12308 Rev 4

L9788 Watchdog

Note: These clock-tolerances have to be taken into account additionally.

As output (open drain):
5.5 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified;

Table 23. WDA circuit electrical characteristic

Symbol Parameter Test condition Min Typ Max Unit Pin

1 < VDD5 < VDD_UV

WDA_UV_LO Output low voltage - - 0.6 V WDA
Rreset = 4.7 kΩ
VDD5 = VDD_UV
WDA_IUVres_max Input current 5 - - mA WDA
VUV_reset = 0.6 V
WDA_IlkUV_reset Input leakage current VUV_reset> VDD_UV - - 1 µA WDA

As input:
5.5 V ≤ VB_IN ≤ 18V, 4.75 V ≤ VDD_IO ≤ 5.25 V Tj -40 to 175 °C unless otherwise specified;

Table 24. WDA reset circuit electrical characteristic

Symbol Parameter Test condition Min Typ Max Unit Pin

WDA_RST_L WDA input low voltage - -0.3 - 1.1 V WDA

VDD_IO
WDA_RST_H WDA input high voltage - 2.3 - V WDA
+0.3
WDA_Trst_flt WDA Reset filter time Tested by scan - 10 - µs WDA
WDA pull up external Application note,
- 50 - 250 kΩ WDA
resistor parameter not tested

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263
Main relay driver (low-side driver) L9788

5 Main relay driver (low-side driver)

This driver is used to drive the main relay only.

The on/off status of the driver depends on the following sources of power on: KEY_IN
WK_IN WAKE_UP_TIMER POWER_HOLD (MSC), CAN see Table 20. The Main Relay
Driver can be also switched on/off by a MSC command protected by lock. This is intended to
use in the permanent battery supply scheme only if power up was done by wk_in/EOT/ CAN
according to Table 25. MSC micro commands protected by lock are available for fast on and
off diagnosis.

Figure 20. Main relay low-side driver stage

OFF state
OL & STG detection VBAT
ON state
OC & OT protection
LOAD L/R

OUTx

MSC Command
Driver

Ground loss
detection PGND

MAIN RELAY DRIVER

GADG2911161143PS

The low-side (main relay) can work down to VB_IN= VOFF_VB_IN, during cold crank
conditions. The driver has integrated diagnosis, with over-current and overtemperature
protection circuit during the driver on. The driver turn on/off slew-rate is internally controlled.
The Main Relay Driver on/off status is controlled by the power up/down modes or by the
msc commands according to Table 25.
These notes are linked to Table 25

56/264 DS12308 Rev 4

L9788 Main relay driver (low-side driver)

1. The battery status can be determined at power up only.

2. The key detection switches on always MRD and does not determine the battery status.
3. Once the key detection has switched on MRD, MRD is switched off by one of these
events:
– Clearing of all detections and phold not active (power down),
– Watchdog power counter timeout,
– MSC MRD OFF command when phold is active (all detections cleared).
4. The msc_enable_driver command or trans_f error or clock monitor error does not affect
the MRD even if it is controlled by MSC commands.

5.1 ON state diagnostic

Table 25. ON state diagnostic
MSC
command
- - MRD OVC OVT
ON OFF

Auto restart without

restart by MSC
limit of number
Permanent Supply ON Y N scenario 19
scenario 21
(see Figure 109)
(see Figure 111)
Auto restart without
Before limit of number
ON N/A N/A N/A
KEY_DET=1 Power up scenario 12/13
Non (see Figure 102)
Permanent Auto restart without Auto restart without
Supply limit of number limit of number
After
ON N N scenario 14/27/15 scenario 26/27
Power up
(see Figure 102, 104 (see Figure 100 and
and 105) Figure 104)
Auto restart without
restart by MSC
limit of number
Permanent Supply OFF Y Y scenario 19
scenario 21
(see Figure 109)
(see Figure 111)
Auto restart for
MRD_EN_TIMEOUT
WAKE_IN_DET / min 331 ms
WAKE_EOT_DET /
Before typ 500 ms
WAKE_CAN_DET =1 ON N/A N/A N/A
Power up max 650 ms
KEY_DET=0 Non
Permanent Scenario 17/18
Supply (see Figure 102 and
107)

No restart No restart
After
ON N N scenario 31 scenario 28
Power up
(see Figure 108) (see Figure 115)

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263
Main relay driver (low-side driver) L9788

Table 25. ON state diagnostic (continued)

MSC
command
- - MRD OVC OVT
ON OFF

Auto restart without

Keep restart by MSC
limit of number
Permanent Supply the Y Y scenario 20 (see
scenario 29 (see
PHOLD_EN =1 status Figure 110)
Figure 112)
KEY_DET/WAKE_IN_
DET/ Before
N/A N/A N/A N/A N/A
WAKE_EOT_DET/ Non Power up
WAKE_CAN_DET = 0 Permanent
Keep No restart No restart
Supply After
the N Y scenario 16 (see scenario 30 (see
Power up
status Figure 105) Figure 116)

5.1.1 Overcurrent protection

When overcurrent fault is detected the Main Relay Driver MRD is switched off.
The MRD is automatically restarted every T_res if KEY_IN is still active in not permanent
battery supply scheme. No restart is done in permanent battery supply schemes.
In non permanent supply system waked up by WK_IN or WAKE_UP_EOT or
WAKE_UP_CAN, MRD OVC retry is just done before VB_IN present. No restart of MRD
after VB_IN power loss due to OVC, unless a next rising edge at WK_IN or WAKE_UP_EOT
or WAKE_UP_CAN.
The retry is done for MRD_EN_TIMEOUT from the detection of WK_IN or WAKE_UP_EOT
or WAKE_UP_CAN.
In permanent battery supply scheme in case of power up from WK_IN or
WAKE_UP_TIMER or WAKE_UP_CAN the MRD is not switched on at power up. In case of
permanent battery supply scheme and OVC protection is activated the driver is restarted by
a positive transition on the MSC MRD_ON command. It is not restarted by MSC reading.

5.1.2 Thermal protection

The overtemperature fault is detected only when VB_IN is present and the logic is out of
power on reset, so when the device is in ON state.
When overtemperature fault is detected the Main Relay Driver is switched off. In not
permanent battery supply schemes the switching off of the Main Relay Driver produces a
power down. If KEY is still active, a new power up sequence is started. If wake up from
WK_IN or EOT or CAN, or PHOLD_EN =1, no power up sequence is started. In permanent
battery supply schemes the switching off of the Main Relay Driver does not produce a power
down. The MRD is switched on again when temperature decreases to T_SD_LOW.

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L9788 Main relay driver (low-side driver)

5.2 OFF state diagnostic

The OFF diagnosis is performed only in the supply scheme with battery permanently
connected.
The off diagnosis is the same as other low-side drivers.
There is a bit Ipupd_EN which is controlled by a MSC bit (CONFIG_REG2 D6), it is used by
external µController if it is needed to switch on/off both pull up and pull down diagnosis
current.
There is a bit Ipupd_MODE which is controlled by a MSC bit(CONFIG_REG2 D7), it is used
by external uController if it is needed to switch on/off the bigger diagnosis current
(I_LS_PU1) in fast mode. It is possible to define the maximum number of retry in case of
OVC after wake up by KEY. It can be done setting KEY_OC_RETRY_MAX_EN bit in
CONFIG-REG 20.
Conditions:
5.5 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified;

Table 26. Main relay low-side driver electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

Main relay

Low-side out VB_IN = 3.9 V 

MRD_out_voltage_low - - 0.9 V MRD
voltage Iload = 0.1 A
Low-side out 5.5 V < VB_IN < 18 V
MRD_out_voltage_nom - - 1.35 V MRD
voltage Iload = 0.3 A
Output leakage Output disabled,
MRD_lkg -10 - +10 µA MRD
current diagnostic off

rev_MRD - Reverse battery - - -16 V MRD

I_load Output current Application Info - - 0.5 A MRD

From 80% to 30% of

Voltage slew ON VOUT VB_IN = 14 V,
SR_ON_20 2 - 6 V/µs MRD
State Rload = 20 Ω
Cload = 10 nF
From 30% to 80% of
Voltage slew OFF VOUT VB_IN = 14 V,
SR_OFF_20 2 - 6 V/µs MRD
State Rload = 20 Ω
Cload = 10 nF
Propagation
Delay from
VB_IN = 14 V, 
Chip_EN rising
Ton_MRD_20 Rload = 20 Ω - - 10 µs MRD
edge to 80%
Cload = 10 nF
output MRD
voltage

DS12308 Rev 4 59/264

263
Main relay driver (low-side driver) L9788

Table 26. Main relay low-side driver electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Propagation
Delay from
VB_IN=14V,
Chip_EN falling
Toff_MRD_20 Rload = 20 Ω - - 10 µs MRD
edge to 20%
Cload = 10 nF
output MRD
voltage
MRD clamping
Vclamp_MRD Iload = 0.3 A 48 55 V MRD
Voltage
Iload = 1 A
Guaranteed by
MRD clamping design, provided
Vclamp_MRD_high_curr 48 - 55 V MRD
Voltage single pulse energy
limits are not violated
by clamping action
Over current
IOVC_MRD - 1 - 2 A MRD
driver threshold
LS overcurrent
I_LS_ocv_flt Guaranteed by scan 4 - 7 µs MRD
filter time
Self retry time
after OVC with
KEY_IN on or
TfT_Res Guaranteed by scan 15.2 16 16.8 ms MRD
WK_IN active or
WKE_UP_EOT
active
Maximum number
of retry when
NRes_NN Guaranteed by scan - 32 - - MRD
KEY_OC_RETRY
_MAX_EN=1
Temperature shut
T_SD_HIGH - 185 200 °C MRD
down
Temperature shut
T_SD_LOW - 175 - 190 °C MRD
down recover
Temperature shut
T_SD_hys - 5 - 10 °C MRD
down hysteresis
Thermal
Guaranteed by
tmsd_pre_an shutdown analog 1.5 - 4 µs MRD
design
filter time
Digital deglitch
filter time on
t_SD_deglitch Guaranteed by scan 30 - - µs MRD
Temperature shut
down detection

OFF state diagnostic

VOUTO
Short to GND Driver tristate, diag
VLVT 1.9 - PEN V MRD
threshold voltage enabled
-190mV

60/264 DS12308 Rev 4

L9788 Main relay driver (low-side driver)

Table 26. Main relay low-side driver electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Open load Driver tristate, diag VOUTOPEN

V_OL - 3.0 V MRD
threshold voltage enabled +160 mV
Open load output Driver tristate, diag
VOUTOPEN 2.3 2.5 2.7 V MRD
voltage enabled
In OFF condition,
Diagnostic pull up OUTx < VLVT,
I_LS_PU1 2.5 3.6 4.7 mA MRD
current Ipupd_EN = ENB,
Ipupd_MODE = ”1”
In OFF condition,
Diagnostic pull up OUTx < VLVT,
I_LS_PU2 40 70 100 µA MRD
current Ipupd_EN = ENB,
Ipupd_MODE = ”0”
In OFF condition,
Diagnostic pull OUTx >
I_LS_PD1 60 85 110 µA MRD
down current VOUTOPEN,
Ipupd_EN = ENB

Tflt_diagoff1 DIAG Filter time Filter Mode=0 75 100 125 µs MRD

Tflt_diagoff2 DIAG Filter time Filter Mode=1 450 600 750 µs MRD

Minimum OFF Application note 

- time for correct (esd cap < 10 nF) 175 - - µs MRD
diagnostic Filter Mode = 0
Fast OFF
- diagnostic Filter Mode = 0 175 200 240 µs MRD
ON→OFF→ON
Fast ON
- diagnostic - 65 - 90 µs MRD
OFF→ON→OFF

Driver Reliability Data

I_OT_n = 0.3 A
Energy Repetitive Freq = 1 Hz ;
EnergyRep MRD - - 6.5 mJ MRD
Pulses 4 Miopulses
Tj =150 °C

5.3 Error handling

The Main Relay Driver follows the same error handling table as other low-side drivers.

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263
Multi-voltage regulator supplies L9788

6 Multi-voltage regulator supplies

The chip has one pre-boost regulator and one pre-buck regulator, which will supply a 5 V
regulator with external MOS. Three 5 V tracking regulators are included. One charge pump
is used for HS channel and by the 5 V linear regulator to drive the external MOS. See the
diagram in Figure 21. The chip becomes to be supplied and the regulators are enabled in
the sequence: VB_in grows till is higher than VB_IN_uv threshold, then internal 3V3 supply,
charge pump and buck, pre-boost regulator, 5 V linear regulator, 5 V tracking regulator 1, 2
and 3 are switched on. Then the power on reset is released and the chip is working.

Figure 21. Power supply block diagram with pre-boost regulator and MRD

VB_IN_SW
VBAT
MRD

VB_IN BUCK_C_BST

C_BST
Boost_G Boost 6V
Rg_pd Buck
Rg BUCK_SW
VBsense
.Ÿ
VPRE
KEY

5V Regulator
Linear 5V
Internal
Supply
WK_IN

VB_STBY
WK Track Regulator

Vtrack 1/2/3

U-chip power structure

GADG2911161223PS

62/264 DS12308 Rev 4

L9788 Multi-voltage regulator supplies

Figure 22. Power supply block diagram with pre-boost regulator permanent VBAT
VB_IN_SW
VBAT VB_IN

BUCK_C_BST

C_BST
Boost_G Boost 6V
Rg_pd Buck
Rg BUCK_SW
VBsense
Nȍ
VPRE
KEY

5V Regulator
Linear 5V
Internal
Supply
WK_IN

VB_STBY
WK Track Regulator

Vtrack 1/2/3

U-chip power structure

GADG2911161230PS

The pre-boost regulator is an optional choice. It can be disabled (BOOST_EN (CONFIG-

REG 1 D5) in case battery voltage is high enough in cranking phase to supply the pre-buck
regulator. See the diagram in Figure 23

Figure 23. Power supply block diagram with charge pump without pre-boost
VB_IN_SW

VBAT Anti-Reverse
VB_IN BUCK_C_BST

CP C_BST
Charge Pump 6V
Buck

KEY Vpre

5V Regulator
Internal Linear 5V
Supply
WK_IN

VB_STBY Track Regulator

WK

Vtrack 1/2/3

U-chip power structure

GADG2911161241PS

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263
Multi-voltage regulator supplies L9788

Figure 24. Power supply block diagram with charge pump and MRD without pre-boost
VB_IN_SW

VBAT
VB_IN
BUCK_C_BST

CP Charge Pump C_BST

6V
Buck

KEY
Vpre

Internal 5V Regulator
Linear 5V
Supply
WK_IN

VB_STBY
WK Track Regulator

Vtrack 1/2/3

U-chip power structure

GADG2911161247PS

6.1 Pre-boost regulator

The boost regulator will provide a higher voltage than battery to the buck regulator when
battery voltage is too low to maintain 5 V regulator out of reset conditions. Once the output
of the pre-boost is higher than VB_IN_th (typ 8.5 V), the pre-boost will stop working.
The boost is disabled at the beginning of the power down sequence. When Boost_EN
(CONFIG_REG 1 D5) = 0 the internal driver keeps OFF the external MOS.
The parameters of Pre-boost regulator can be guaranteed when Vbat goes down to 3.0 V
during cranking phase. The block diagram of the pre-boost is Figure 25.

Figure 25. Pre-boost block diagram

L_Boost D1_Boost
VBAT SW
Cout_boost_ALU

VB_sense Vpre
Cout_boost

Rg
Boost_G
ADC buffer Q1_Boost

Duty cycle control Boost

Logic PWM
AND driver
Rg_pd
Enable stage
Vth Boost_En

Output voltage sense VB_IN

Inside chip
GADG2911161323PS

64/264 DS12308 Rev 4

L9788 Multi-voltage regulator supplies

3.0 V ≤ VBAT(*) < 18 V, Tj -40 to 175 °C unless otherwise specified.

(*)
Note: VBAT is the battery line of Figure 25 in front of the limiting 22 kΩ resistor (not shown in the
figure).

Table 27. Pre-boost regulator output electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

When VB_IN <

VB_IN_TH, the boost
starts for time (tON).
BOOST When VB_IN ≥
VB_IN_th enable/disable VB_IN_TH, Boost is 8.07 8.5 8.93 V VB_IN
threshold disabled after tON is
completed. tON
depends on different
duty cycle
BOOST
Enable/disable
tdBOOST_EN - 0.19 - 2 μs VB_IN
comparator
delay time
43 cycles of 15 MHz
Switching
Fsw_BOOST main clk, Guaranteed 334 352 370 kHz VB_IN
frequency
by SCAN
0V < VBAT_SENSE <
Vcomp_th1 33 out of
Boost Duty 43 cycles of 15MHz
Boost_DC1 - 76.74 - % VB_IN
cycle 1 main clk (100% DC is
43 clk cycles)
Guaranteed by SCAN
VBAT_SENSE
Vcomp_th1 comparator - 3.95 4.15 4.35 V VBAT_SENSE
threshold 1
Vcomp_th1 <
VBAT_SENSE <
Boost Duty
Boost_DC2 Vcomp_th2 25 out of - 58 - % VB_IN
cycle 2
43 clk cycles
Guaranteed by SCAN
VBAT_SENSE
Vcomp_th2 comparator - 5 5.36 5.7 V VBAT_SENSE
threshold 2
Vcomp_th2 <
VBAT_SENSE <
Boost Duty
Boost_DC3 Vcomp_th3 18 out of - 41.86 - % VB_IN
cycle 3
43 clk cycles
Guaranteed by SCAN
VBAT_SENSE
Vcomp_th3 comparator - 6.25 6.6 6.95 V VBAT_SENSE
threshold 3

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263
Multi-voltage regulator supplies L9788

Table 27. Pre-boost regulator output electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Vcomp_th3 <
VBAT_SENSE <
Boost Duty
Boost_DC4 Vcomp_th4 10 out of - 23.85 - % VB_IN
cycle 4
43 clk cycles
Guaranteed by SCAN
VBAT_SENSE
Vcomp_th4 comparator - 7.4 7.8 8.2 V VBAT_SENSE
threshold 4
Vcomp_th4 <
Boost Duty VBAT_SENSE 4 out of
Boost_DC5 - 9.3 - % VB_IN
cycle 5 43 clk cycles
Guaranteed by SCAN
VBAT_SENSE
Vcomp_th1/2/3/4
tdBAT_SENS comparators 0.19 - 2 μs VBAT_SENSE
comparators
delay time

LS driver sink
IBOOST_LS_sink BOOST_G = 6 V 30 50 70 mA BOOST_G
current

HS driver
IBOOST_HS_source BOOST_G = 0 V 30 50 70 mA BOOST_G
source current

LS driver sink
IBOOST_LS_sink BOOST_G = 0.5 V 15 - 43 mA BOOST_G
current

HS driver
IBOOST_HS_source BOOST_G = 5.5 V 10 - 43 mA BOOST_G
source current

Leakage From 0 V to max pin

BOOST_G_Ileak - - 1.2 µA BOOST_G
current voltage

Current
leakage on
I_VBAT_Sense_stby - - - 1 µA VBAT_SENSE
VBAT_sense
pin in st-by
Pull down
current on
I_VBAT_Sense VBAT_sense - - - 100 µA VBAT_SENSE
operative
mode
Pull-down
resistor from
R_VBAT_sense - 438 880 1320 kΩ VBAT_SENSE
VBAT_sense
to GND
Resistor
R1_VBAT_sense divider string Design info, not tested 311 622 933 kΩ -
element
Resistor
R2_VBAT_sense divider string Design info, not tested 28.75 57.5 86.25 kΩ -
element

66/264 DS12308 Rev 4

L9788 Multi-voltage regulator supplies

Table 27. Pre-boost regulator output electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Resistor
R3_VBAT_sense divider string Design info, not tested 18.15 36.3 54.45 kΩ -
element
Resistor
R4_VBAT_sense divider string Design info, not tested 12.5 25 37.5 kΩ -
element
Resistor
R5_VBAT_sense divider string Design info, not tested 67.5 135 202.5 kΩ -
element

Boost application information table:

Table 28. Pre-boost regulator external components electrical characteristics

Symbol Parameter Min Typ Max Unit Note Pin

Min 4*10 µF,

Capacitance at
COUT_BOOST 36 40 150 µF 10%,25 V, X7R, 1206, VB_IN
VB_IN
CER CAP;
Option ALU ALU 35 V ESR 10 mΩ--3 Ω¸
COUT_BOOST_ALU Capacitance at 0 330 470 µF 330 µF, 20%, 25 V, VB_IN
VB_IN SMD,AL,ELEC CAP
triangular ripple @ 10 kHz
1.2 and 25 kHz @ 50 kHz @
1.1 100 kHz @ 350 kHz. All
VBoost_ripple - - - Vpp VB_IN
1.0 characteristics of all blocks
0.8 supplied by VB_IN
guaranteed
Load current at
IBOOST 0.05 - 1.8 A - VB_IN
VB_IN

Q1_Boost - - - - - Choice: STD20NF06L VB_IN

D1_Boost - - - - - Choice: STPS10H100C VB_IN

BOOST
L_boost 0.8 1 1.2 µH ESR = 10 mΩ VB_IN
inductance
BOOST
L_boost1 - 2.5 - µH ESR = 25 mΩ, Isat = 23 A VB_IN
inductance
BOOST
L_boost1 - 3.3 - µH - VB_IN
inductance
Resistor for
Rsense VB_sense pin 10 22 30 kΩ - VBAT_Sense
protection

Rg - - 2.2 - Ω - BOOST_G

Rg_pd - - 150 - kΩ - BOOST_G

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263
Multi-voltage regulator supplies L9788

Figure 26. Boost threshold comparator's schematic

VBAT_sense

R1
Vcomp_th1
Vbg
R2
Vcomp_th2
Vbg
R3
Vcomp_th3
Vbg
R4
Vcomp_th4
R5 Vbg

EN

GADG2911161610PS

6.2 Pre-buck regulator with internal MOS

Vpre features:
 6 V regulated output voltage (VPRE);
 1.6 A maximum output current;
 PWM block (ramp generator, comparator and main latch) with one fixed PWM
frequency (Fsw_vpre);
 Internal error amplifier;
 Internal Power FET including Bootstrap;
 dV/dt Control on gate drivers to fulfill EMC requirements;
 Maximum Duty cycle 100%, to allow to charge Bootstrap capacitor;
 Protection by over temperature;
 Soft Start.
The Vpre regulator is a buck regulator which supplies Pre-boost driver/VDD5/Vtrack1.2.3.
When the OV of VB_IN is detected, the Vpre(Buck) will be switched off. This function is
selectable by a dedicated MSC bit (VB_IN_OV_RST_EN in CONFIG_REG12). A bit is also
available (BUCK_SLOW_SR in CONFIG_REG 21) in order to select slew rate for output
voltage; the default value corresponds to fast slew rate, slow slew rate helps to improve
emission performance
The Vpre regulator includes a soft start. Range of dV/dt at VPRE is specified in electrical
parameters.
Pulse skipping mode: the Vpre regulator can go to pulse skipping mode when the load is too
low to avoid that output voltage (VPRE) rises too much. The principle of the pulse skipping
mode is to skip some pulses during the switching phase, when the loop can't keep itself the
output voltage regulated with a very low load because it is limited by the minimum duty
cycle.
VB_IN_OV fault can trigger the turn OFF of Buck regulator, as specified into reset matrix.
This effect can be masked with bit VB_IN_OV_RST_EN in CONFIG_REG 12.

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L9788 Multi-voltage regulator supplies

Conditions:
5.5 V< VB_IN_SW < 18 V, Tj -40 to 175 °C unless otherwise specified.

Table 29. Pre-buck regulator output electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

VPRE regulated VB_IN_SW = 7 V to

voltage (including 18 V, Ivpre = 50 mA 5.82 6.18
VPREdc 6 V VPRE
aging and static ~1.6 A, C = 20 µF, (-3%) (+3%)
line/load regulation) L = 22 µH

Total VPRE voltage

Vdrift_VPRE - -0.8 - 0.8 % VPRE
aging drift

7 V < VB_IN_SW < 18V

Ivpre = 50 mA, 1600 mA
Line regulation
Vline_VPRE C=20 µF,  -25 - 25 mV VPRE
voltage
L = 22 µH, T = 27 °C,
175 °C
7 V < VB_IN_SW < 18V
Line regulation Ivpre = 50 mA, 
Vline_VPRE -25 - 25 mV VPRE
voltage 1600 mA C=20 µF, 
L = 22 µH,T = -40 °C
7 V < VB_IN_SW < 18V
Line regulation Ivpre = 50 mA,
Vline_VPRE -60 - 60 mV VPRE
voltage 1600 mA C=20 µF, 
L = 22 µH,T = -40 °C
VB_IN_SW = 7 V, 18V,
Load regulation 50 mA<Ivpre<1600 mA,
Vload_VPRE -25 - 25 mV VPRE
voltage C = 20 µF, L = 22 µH,
T = 27 °C, 175 °C
VB_IN_SW = 7 V, 18 V,
Load regulation 50mA<Ivpre<1600 mA,
Vload_VPRE -25 - 25 mV VPRE
voltage C = 20 µF,
L = 22 µH, T= -40 °C
VB_IN_SW = 7 V, 18 V,
Load regulation 50 mA<Ivpre<1600 mA,
Vload_VPRE -60 - 60 mV VPRE
voltage C = 20 µF,
L = 22 µH, T=-40°
VB_IN_SW step 12 V to
18 V; 18 V to 12 V,
Transient line dVB_IN_SW/dt = 3 V/µs,
Vline_VPRE_tr -8 VPRE 8 % VPRE
regulation accuracy Ivpre = 50 mA,1.3 A,
C = 20 µF, L = 22 µH,
Guaranteed by design(1)
VB_IN_SW = 13 V,
Ivpre = 50 mA to 1.3 A
Transient Load
Vload_VPRE_tr dI/dt = 500 mA/µs, -8 VPRE 8 % VPRE
regulation accuracy
C = 20 µF, L = 22 µH,
Guaranteed by design(1)

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263
Multi-voltage regulator supplies L9788

Table 29. Pre-buck regulator output electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

ILIMVPRE Current limit - 2.4 - 3.5 A VPRE

VB_IN_SW from 0 to
VPRE capacitive 13 V in 100 µs,
VPRE_coupling coupling during C = 40 µF, L = 22 µH, - - 3 V VPRE
battery transients device off
Design info, not tested
VPRE under
voltage hysteresis
threshold high;
Test condition:
Vuv_vpre_h VPRE voltage at 4.38 - 4.65 V VPRE
VB_IN_SW = 5.4 V
Power up to allow
Boost activation
threshold
VPRE under
Test condition:
Vuv_vpre_l voltage hysteresis 4.25 - 4.51 V VPRE
VB_IN_SW = 5.4 V
threshold low

VPRE under
Tuv_filter_vpre 10.1 12 13.3 us VPRE
voltage filter time (2)

VPRE_slope Slope control VB_IN_SW = 13 V 5 - 30 V/ms VPRE

Comparator threshold
Thermal
Tmsd_VPRE_H and functionality are 185 - 200 °C VPRE
shutdown_High
tested in production
Comparator threshold
Thermal
Tmsd_VPRE_L and functionality are 175 - 190 °C VPRE
shutdown_Low
tested in production

Thermal hysteresis
Tmsd_hyst - 5 - 10 °C VPRE
for shutdown

Thermal shutdown
tmsd_pre_an - 1.5 - 4 us VPRE
analog filter time

Thermal shutdown
tmsd_pre_dig - 10 20 30 us VPRE
digital filter time

To keep VPRE below

VPRE pulldown
VPRE_rpd 10 V with Buck switch 0.2 - 1.05 MΩ VPRE
resistor
leakage in OFF state
Fosc from main 15 MHz
Switching
Fsw_VPRE oscillator, typical 450 Fosc/32 500 kHz BUCK_SW
frequency
462.5 kHz

DCVPRE(BUCK) Duty cycle range - 3% - 100% - BUCK_SW

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L9788 Multi-voltage regulator supplies

Table 29. Pre-buck regulator output electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

VPRE (Buck_POW
RVPRE ER MOS) transistor - - - 200 mOhm BUCK_SW
RDSON

TRVPRE Rise Time (10-90%) BUCK_SLOW_SR=0 5 - 25 ns BUCK_SW

TRVPRE_slow Rise Time (10-90%) BUCK_SLOW_SR=1 10 - 30 ns BUCK_SW

TFVPRE Fall Time (10-90%) Iload = 1 A 5 - 27 ns BUCK_SW

From 0 V to max pin

VPRE_SW_Ileak Leakage current - - 1 μA BUCK_SW
voltage

1. Fault detection during power up sequence is masked until RSTN release to avoid false triggering at ramp-up phase.
2. No VDD5 UV/OV violation is expected during specified transient.

Note: When 18 < VB_IN_SW< VOV_VB_IN_L, the function of Vpre is guaranteed and no reset
happens.

Table 30. Pre-buck regulator external components electrical characteristics (Vpre application
information)
Symbol Parameter Note Min Typ Max Unit Pin

Min 2*10 µF Ceramic X7R 16 V in

External parallel
CVPRE capacitor on 15 40 150 µF VPRE
CER,X7R,10 µF, 10%,16 V,1206,
Vbuck supply
Sn
Switching
LVPRE regulator external - 15 22 29 µH VPRE
inductor
Ceramic X7R 16V
Bootstrap
CBST 47nF, 10%, 16 V, X7R, 0603, - 47 - nF BUCK_C_BST
capacitor
TINNED, CER CAP/
Switching
regulator external
DVBUCK_CTRL Schottky Diode STPS5L60-Y - - - - -
diode (Schottky
or ultrafast)

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Multi-voltage regulator supplies L9788

6.3 Tracking regulator for sensors supply

There are three 5V tracking regulators with self protection from over-current, over-voltage
and short to battery. STB/OVC/OV don't disable tracking, but set a flag readable by MSC.
Those three tracking regulators track VDD5_in voltage with 150mA output. There is one
thermal sensor, shared between the three tracking regulators, to provide the thermal shut
down protection for those three tracking sensor supplies. The switching off of one internal
tracking occurs if that tracking is also in OVC.
Once the thermal shut down has happened, the tracking sensor in over-current condition
will be off until temperature decreases to thermal shut down threshold low. Those three
tracking regulators can be singularly disabled by dedicated MSC bit (TRK_EN
CONFIG_REG7 [3:5] in CONFIG_REG 7). VB_IN_OV fault can trigger the turn OFF of
Tracking regulators, as specified into reset matrix. This effect can be masked with bit
VB_IN_OV_RST_EN in CONFIG_REG 12.
Conditions:
5.5 V < VB_IN_SW ≤ 18 V, Tj -40 to 175 °C unless otherwise specified.

Table 31. Tracking sensor supplies electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

Output voltage tracking

error (including voltage
Vpre = 5.6 – 18 V VDD5 VDD5
∆VTRK aging and static V VSENSE1/2/3
1 mA<IVSENS<150 mA -15m +15m
load/line transient
regulation)(1)

IMAX_VS Output current limitation VSENS = -1 V 150 250 mA VSENSE1/2/3

Output over-current Imax

ITH_VS Vpre = 5.6 – 18 V 150 mA VSENSE1/2/3
threshold _vs

Vpre = 5.6 – 18 V
Vline_VS Line regulation voltage IVSENS=50mA 15 mV VSENSE1/2/3
Ctrk=470nF (2)
Vpre = 6 V
Vload_VS Load regulation voltage 1 mA<IVSENS<150 mA 15 mV VSENSE1/2/3
Ctrk = 470 nF Note(2)
Vpre = 6 V IVSENS =1 mA
to 150 mA and viceversa
Transient load
Vload_tran dI/dt = 150 mA/µs -15 +15 % VSENSE1/2/3
regulation
Ctrk = 470 nF Guaranteed
by design(3)
VPRE step 5.6V to 7V and
viceversa
dVPRE/dt=3V/µs IVSENS
Vline_tran Transient line regulation -15 +15 % VSENSE1/2/3
=1mA, 150mA Ctrk=470nF
Guaranteed by design(4),
(3)

Short circuit reverse Output shorted to

Isink_VS - - -4 mA VSENSE1/2/3
current VB_IN+2V

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L9788 Multi-voltage regulator supplies

Table 31. Tracking sensor supplies electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Short to battery Vpre

VSCB_TH_VS - Vpre V VSENSE1/2/3
threshold +0.2

VSENSE1/2/3
VUV_VS_l undervoltage hysteresis - 4.5 4.65 4.75 V VSENSE1/2/3
threshold low
VSENSE1/2/3
VUV_VS_h undervoltage hysteresis - 4.7 4.8 4.9 V VSENSE1/2/3
threshold high

VSENSE1/2/3
VOV_VS - 5.3 5.4 5.5 V VSENSE1/2/3
overvoltage threshold

Supply voltage tracking

PSRRVS f =10 kHz -35 dB VSENSE1/2/3
rejection

Over shoot during

VOS_VS - 5.5 V VSENSE1/2/3
power up

TUV_filter_VS_ Undervoltage filter

cover by SCAN TEST 16 24 32 µs VSENSE1/2/3
running time(2)

TOV_filter_VS_
Overvoltage filter time(2) cover by SCAN TEST 16 24 32 µs VSENSE1/2/3
running

TOC_filter_VS_
Overcurrent filter time cover by SCAN TEST 16 24 32 µs VSENSE1/2/3
running

Comparator threshold and

Thermal
Tmsd_VPRE_H functionality are tested in 185 200 °C VSENSE1,2,3
shutdown_High
production
Comparator threshold and
Tmsd_VPRE_L Thermal shutdown_Low functionality are tested in 175 190 °C VSENSE1,2,3
production

Thermal hysteresis for

Tmsd_hyst - 5 10 °C VSENSE1,2,3
shutdown

Thermal shutdown
tmsd_pre_an Guaranteed by design 1.5 4 µs VSENSE1,2,3
analog filter time

Thermal shutdown
tmsd_pre_dig Implemented in VHDL 10 20 30 µs VSENSE1,2,3
digital filter time

1. No oscillation expected with 0mA load current.

2. line and load regulation are guaranteed until the loop is able to regulate after they are defined by low drop parameters;
ITH_VS < IMAX_VS which is guaranteed by design; Over shoot during power up should not be triggered over voltage
warning. When Vtrk output is higher than VSCB_TH_VS, The Vtrk output structure will be switched off automatically in
order to block the big inrush current into chip through Vtrk circuit. When Vtrk output is higher than VOV_VS, an over voltage
flag will be set. UV/OV fault detection during power up sequence is masked until RSTN release to avoid false triggering at
ramp-up phase.
3. No UV/OV violation is expected during specified transient.
4. Specification valid until Tracking regulator is in regulation range, or, in other words, until Vsense X output voltage is
determined by the effect of voltage regulation loop and not by secondary effects on other regulators.

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Table 32. VTrack external components characteristics

Symbol Parameter Note Min Typ Max Unit Pin

ESR_max<20 mΩ Suggest
VSENSE external 470nF
CVS1/2/3 part numbers: 0.47 20 µF VSENSE1/2/3
capacitor -20%
GCM188R71C105KA49D

6.4 External tracking regulator monitor

Vsense4_mon is an input pin for monitoring an external tracking regulator output voltage.
Conditions:
5.5 V < VB_IN_SW ≤ 18 V, Tj -40 to 175 °C unless otherwise specified.

Table 33. External VTrack monitor

Symbol Parameter Test condition Min Typ Max Unit Pin

VSENSE4 undervoltage
VUV_VS_l - 4.55 4.65 4.75 V VSENSE4_MON
threshold low

VSENSE4 undervoltage
VUV_VS_h - 4.7 4.8 4.95 V VSENSE4_MON
threshold high

VSENSE4 overvoltage
VOV_VS - 5.3 5.4 5.55 V VSENSE4_MON
threshold

Covered by
TUV_filter_VS_running(1) Undervoltage filter time 16 24 32 µs VSENSE4_MON
SCAN TEST

Covered by
TOV_filter_VS_running(1) Overvoltage filter time 16 24 32 µs VSENSE4_MON
SCAN TEST

1. Fault detection during power up sequence is masked until RSTN release to avoid false triggering at ramp-up phase.

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L9788 Multi-voltage regulator supplies

6.5 VDD5 linear regulator with external MOSFET

VDD5 voltage is generated by a linear controller with internal pre-driver and external MOS
FET.
Electrical characteristics are available in Table 34 and Table 35. VB_IN_OV fault can trigger
the turn OFF of VDD5 regulator, as specified into reset matrix. This effect can be masked
with bit VB_IN_OV_RST_EN in CONFIG_REG 12.
VB_IN_UV fault triggers the turn OFF of VDD5 regulator, as specified into reset matrix. This
effect can be masked with bit VDD5_OFF_SEL in CONFIG_REG 11.
VDD5_OV fault has effects into the device specified into reset matrix. These effects can be
masked with bit VDD5_OV_RST_EN in CONFIG_REG 12.
Conditions:
5.5 V< VB_IN_SW ≤ 18 V, 5.5 V < VB_IN ≤ 18 V, Tj -40 to 175°C unless otherwise specified.

Table 34. VDD5 linear controller pre-driver electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

5 V regulated
voltage including
VVDD5 Iload = 10 mA, 1 A 4.9 5 5.1 V VDD5_IN
static load / line
regulation
Output voltage
Cvdd5 = 10 µF; from
SRp-up_VDD5 slew rate at 2 - 25 V/ms VDD5_IN
VDD5*10% to VDD5*90%
power-up
Controller
stability over
IVDD5 - 1 - - A VDD5_IN
VDD5 output
current range

Line regulation 5.6 V < VPre < 18 V Iload

Vline_VDD5 -25 - 25 mV VDD5_IN
voltage 10mA, 1A Cvdd5 = 10 µF (1)

Load regulation VPre 5.6 V, 18 V 10 mA <

Vload_VDD5 -25 - 25 mV VDD5_IN
voltage Iload < 1 A Cvdd5 = 10 µF (1)

Vpre from 5.6 V to 7 V by 1 µs

Line transient Iload = 10 mA, 800 mA 
Vline_VDD5_tran regulation Cvdd5 =10µF Ext MOS - - 300 mV VDD5_IN
voltage STD20NF06L Guaranteed by
design (1)

VPre = 6 V Iload from 10 mA

Load transient to 800 mA by 1.5us
Vload_VDD5_tran regulation Cvdd5=10µF Ext MOS - - 280 mV VDD5_IN
voltage STD20NF06L Guaranteed by
design (1)

Total VDD5
Vdrift_Vdd5 - -0.8 - 0.8 % VDD5_IN
voltage aging drift

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Table 34. VDD5 linear controller pre-driver electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Supply voltage Cout = 10 µF, ESR = 0.1Ω

PSRRVDD5 - - -35 dB VDD5_IN
rejection ratio Iload = 600 mA f = 10 kHz

VDD5 voltage
with overshoot
VOS_VDD5 - 0 0.1 0.2 V VDD5_IN
admitted at
switch on

Undervoltage
TUV_filter_VDD5 - 16 24 32 µs VDD5_IN
filter time(1)

Overvoltage filter
TOV_filter_VDD5 - 16 24 32 µs VDD5_IN
time(1)

VDD5
undervoltage
VUV_VDD5_L - 4.5 4.65 4.75 V VDD5_IN
hysteresis
threshold low
VDD5
undervoltage
VUV_VDD5_H - 4.7 4.8 4.9 V VDD5_IN
hysteresis
threshold high
VDD5
VOV_VDD5 overvoltage - 5.3 5.4 5.5 V VDD5_IN
threshold
Pre-driver gate VPre = 4.8 V to force
VVDD5_GATE_Min 8 - - V VDD5_GATE
voltage regulator in low drop condition
Pre-driver gate
VVDD5_GATE_MAX Force 5 mA into VDD5_GATE - - 15 V VDD5_GATE
voltage
VGS OFF VDD5_GATE-
Device off - - 0.5 V VDD5_GATE
condition VDD5_IN
1. line and load regulation are guaranteed until the loop is able to regulate after they are defined by low drop parameters;
Over shoot during power up should not be triggered over voltage warning. UV/OV fault detection during power up
sequence is masked until RSTN release to avoid false triggering at ramp-up phase. With external MOS different from
STD20NF06L regulated voltage could violate UV threshold but for a time shorter than digital deglitch, so it would not be
able to trigger UV/OV fault. With STD20NF06L MOS no UV/OV violation is expected on this and other regulators.

Table 35. Linear controller pre-driver. External components characteristics

Symbol Parameter Note Min Typ Max Unit Pin

10 µF to guarantee
External VDD5
CVDD5 ESR = 50 mΩfor load 5 20 60 µF VDD5_IN
capacitor
transient response

VDD5_IN,
- External n-MOS STD20NF06L - - - -
VDD5_GATE

76/264 DS12308 Rev 4

L9788 Multi-voltage regulator supplies

Table 35. Linear controller pre-driver. External components characteristics (continued)

Symbol Parameter Note Min Typ Max Unit Pin

- Rgate_source - - 1 - MΩ -

- Rgate_source - - 1 - MΩ --

Forward
gfs Transconductanc VDS = 25 V, ID = 10 A 4.5 - - S -
e

Gate Threshold VDS = VGS, ID =

VGS(th) 2.0 - 4.0 V -
Voltage 250 μA

input capacitance
Ciss - - 370 1020 pF VDD5_GATE
of external FET

6.6 VDD_IO
VDD_IO pin is the external supply pin for internal I/O circuit.

Table 36. VDD_IO electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

Input current of VB=14V, all VDD_IO

IVDD_IO 2 4.8 8 mA VDD_IO
VDD_IO related pin without load

VVDD_IO Operation range - 3.1 - 5.5 V VDD_IO

Under voltage
VDDIO_UV_LOW threshold on pin - 2.9 3.0 3.1 V VDD_IO
VDDIO

Under voltage
Tf_VDD_IO_UV Tested by scan 3 - 10 µs VDD_IO
filter time(1)

1. Fault detection during power up sequence is masked until RSTN release to avoid false triggering at ramp-up phase.

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6.7 VB_IN and VB_IN_SW SUPPLY

VB_IN pin is the power supply pin for internal circuit.
During cranking phase even the VB_IN is = 3.1 V the chip can keep the status, the internal
POR is not triggered and also the internal supply under voltage is not triggered (internal 3V3
regulator undervoltage), the PHOLD timer value is also kept.

Table 37. VB_IN electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

VB_IN current in functional

IVB_IN - - - 60 mA VB_IN
mode
VB_IN current in OFF
IVB_IN_STBY - - - 10 µA VB_IN
state.
VB_IN=VB_IN_S
VB_IN_SW current in
IVB_IN_SW W=13.5V, Vpre 200 - 350 mA VB_IN_SW
functional mode
load = 500mA
Min VB_IN voltage to keep
VOFF_VB_IN - - - 3.1 V VB_IN
the MRD, start relay status
VB_IN undervoltage
VUV_VB_IN_L - 4.7 4.8 4.9 V VB_IN
hysteresis threshold low
VB_IN undervoltage
VUV_VB_H - 4.8 4.9 5.05 V VB_IN
hysteresis threshold high
VUV_VB_IN_HYST - - - 0.1 - V VB_IN
VB_IN over voltage
VOV_VB_IN_L - 28 - - V VB_IN
threshold low
VB_IN over voltage
VOV_VB_IN_H - - - 32 V VB_IN
threshold high
VOV_VB_IN_HYST - - - 2 - V VB_IN
Filter time1 for VB_IN
tVBOV1 Tested by scan 70 85 100 µs VB_IN
overvoltage(1)
Filter time2 for VB_IN
tVBOV2 Tested by scan 11 15 19 ms VB_IN
overvoltage(1)
Filter time 1 for VB_IN
tVBUV1 undervoltage Tested by scan 5 - 15 µs VB_IN
VUV_VB_IN_L(1)
Filter time 2 for VB_IN
tVBUV2 undervoltage Tested by scan 5 - 15 µs VB_IN
VUV_VB_IN_H(1)
VB_IN threshold for main
VUV_VB_CP_ON Charge Pump ON 2.4 2.7 3 V VB_IN
logic reset
VB_IN threshold for main Charge Pump
VUV_VB_CP_OFF 3.9 4.4 4.8 V VB_IN
logic reset OFF
1. Fault detection during power up sequence is masked until RSTN release to avoid false triggering at ramp-up phase.

78/264 DS12308 Rev 4

L9788 Multi-voltage regulator supplies

When VB_IN is higher than 3.1 V (Voff_vb_in), the starter relay and MRD can hold the state.
VB_IN_SW pin is the dedicated supply pin for pre-buck regulator.
Note: VB_IN_SW must be shorted to VB_IN in PCB layout.

Conditions:
4.8 V ≤ VB_IN ≤ 18 V; Tj -40 to 175° C unless otherwise specified;

Table 38. VB_IN_SW electrical characteristics

Test
Symbol Parameter Min Typ Max Unit Pin
Condition

IVB_IN_sw_STBY VB_IN_SW current in OFF state. - - - 10 µA VB_IN_SW

6.8 Charge pump

Charge pump provides a permanent voltage of at least 4.8 V above VB_IN when VB_IN is
higher than 5.5 V, the VDD5 linear regulator, H-side switch and so on.
Once VB_IN overvoltage is detected (VB_IN > VOV_VB_IN_H for t>tVBOV2), the charge
pump will be switched off automatically.
Charge pump can provide voltage of 4V above VB_IN when VB_IN in low power condition
(3.1V<VB_IN<5.5V)
This charge pump is for internal use only.
Note: It is forbidden to use this charge pump pin for external load.

Figure 27. Power up charge pump behavior

Key_Tfilter Key_Tfilter

KEY_IN KEY_IN

WK_IN_DET WK_IN_DET
WAKE_UP_EOT_DET WAKE_UP_EOT_DET
WAKE_UP_CAN_DET WAKE_UP_CAN_DET

MRD out MRD out

VCP VCP

VB_IN VB_IN
VB_IN / V_CP
VUV_VB_CP_OFF VUV_VB_IN
VB_IN / V_CP

Power On Reset Power On Reset

VPRE VPRE

CHARGE PUMP during Power Up t

CHARGE PUMP during Power Up t
not permanent battery permanent battery
GADG0112160905PS

DS12308 Rev 4 79/264

263
Multi-voltage regulator supplies L9788

Figure 28. Power down charge pump behavior

Key_Tfilter Key_Tfilter

KEY_IN KEY_IN

WK_IN_DET WK_IN_DET
WAKE_UP_EOT_DET WAKE_UP_EOT_DET
WAKE_UP_CAN_DET WAKE_UP_CAN_DET

MRD out MRD out

VCP VCP

VB_IN VB_IN

VB_IN / V_CP VB_IN / V_CP

Power On Reset Power On Reset

Vuv_vpre+ Vuv_vdd5 Vuv_vpre+ Vuv_vdd5

VPRE (filtered) VPRE (filtered)

CHARGE PUMP during Power Down t CHARGE PUMP during Power Down t
not permanent battery permanent battery
GADG0112160944PS

Conditions:
4.8 V≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified;

Table 39. Charge pump characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

External
charge
CP - -20% 100 +20% nF CP
pump
capacitor
VB_IN = 5.5 V-18 V Driver
Starter 1 & 2 & 3 configured as VB_IN+4.8V - VB_IN+8V V CP
Output HS and switching
Vcp
voltage VB_IN_OFF(3.1V)<VB_IN<5.
5 V with 2 Driver Starter VB_IN+4V - VB_IN+8V V CP
configured as HS and fully ON
Leakage
Icp_leakage current in off CP = VB_IN; chip off -3 - 3 µA CP
state

80/264 DS12308 Rev 4

L9788 Multi-voltage regulator supplies

6.9 Main oscillator

The device uses an internal oscillator, called MAIN Oscillator, to synchronize internal logic
and internal charge pump. A second oscillator is used to check internally if the Main
oscillator is working correctly. The Main Oscillator output is continuously verified by the
Auxiliary Oscillator output. The two clocks frequency are measured and compared so that
out of range frequency values can be detected. In case of frequency error greater than 20%
a flag "freq_err" (Upstream Read11) is set and read and cleared by MSC. In case of
frequency error greater than 30% another flag "clk_mon_fault" (Upstream Read11) is set
and read and cleared by MSC, drivers are disabled when this error occurs. The monitor
circuit is able also to detect a stuck condition in the reference clock, moreover the check is
done on both the main and the auxiliary oscillator so that a failure in any of the two
oscillators is able to set the fault flag.

Figure 29. Clock monitor block diagram

Main
Clock divider
oscillator To high

To low
Window counter
Stuck at

Fault logic OSC_fail_SPI_flag

management
To high

To low
Window counter
Stuck at

Auxiliary
Clock divider
oscillator

GADG0112161042PS

The Main and Auxiliary oscillators are kept independent using redundant circuits, biased by
independent current sources, and layouted in different floor plan regions kept isolated
thanks to deep trench usage. The only common point between the oscillators is the digital
supply that is however monitored by the independent mechanisms.
Aux oscillator is used just for safety purpose and connected to a small digital portion (no
impact on EMC performance). The main oscillator has spread spectrum solution applied by
default to reduce emissions; it means that oscillator frequency has and average value equal
to MainOSCIL with a triangular modulation applied, so final frequency is MainOSCIL ± 3.5%
and a triangular variation of about 111 kHz frequency
Conditions:
4.8 ≤ VB_IN ≤ 18V, Tj -40 to 175 °C unless otherwise specified;

Table 40. Clock monitor characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

Internal MAIN oscillator

MainOSCIL VB_IN = 4.8 V-18 V 14.25 15 15.75 MHz -
frequency
Internal redundant
MainOSCIL VB_IN = 4.8 V-18 V - 15 - MHz -
oscillator frequency

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Table 40. Clock monitor characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

VB_IN = 4.8 V-18 V “freq_err=

- Delta 1 Oscillator CHECK 20 - - % -
1”
VB_IN=4.8V-18V
- Delta 2 Oscillator CHECK “FREQ_ERR=1”& 30 - - % -
“clk_mon_fault=1”(drivers OFF)

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L9788 Low-side drivers

7 Low-side drivers

Low-side drivers are used for power stages driving and they include:
 4-channel Low-side Injectors INJ[1:4];
 2-channel Low-side O2 Heaters O2H[1:2];
 2-channel Low-side Solenoids SOL[1:2];
 5-channel Low-side Relays RLY[1:5];
 2-channel Low-side LED[1:2].
All drivers support the same failure diagnosis.

7.1 Diagnosis
The driver has the following fault diagnosis:
Overcurrent (Short To Vbat) protection in On Phase (OVC);
Open Load in Off phase (DIAGOL);
Short to Ground in Off Phase (DIAGLV);
Over Temperature Protection in On phase (OT).
When an overcurrent fault is detected the driver switches off with higher slew rate (FAST
SR) to reduce the power dissipation.

7.1.1 ON state - overcurrent protection

An overcurrent protection is present for LS transistors of each driver channel. Once the
overcurrent fault is detected the faulted power MOS is switched off and a fault bit is set. This
bit can be reset by every Read Diag Communication to re-activate the power stage in this
two condition:
 The MSC command still High, when the Fault OVC Bit is read by MSC communication.
 The MSC command becomes Low and then again High.
To increase EMC robustness and avoid unwanted fault triggering a small deglitch filter is
applied.
In order to avoid false OVC detection during the turn on slew rate phase, an analog blanking
time filtering strategy is implemented. This means that the OVC comparator output is
masked until the driver gate voltage has reached a threshold value which guarantees that
the slew rate phase is ended.

7.1.2 ON state - thermal protection

To protect power stages from temperature overheat (high battery range of operation, soft
short conditions, etc.) a dedicated thermal sensor placed close to power MOS is present in
the layout sensing FET temperature; One threshold is implemented (T_SD_H) with
Hysteresis (T_SD_hys). When the T_SD_H threshold is detected the Driver switches OFF.
Once the power stage has been switched-off for over-temperature detection, it will be able
to switch on again when temperature is decreased below thermal shut down threshold plus
hysteresis value to avoid high frequency on-off cycling.

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Low-side drivers L9788

7.1.3 ON/OFF state - Error in on status diagnosis

To avoid unwanted driving of power stages the consistency of gate driving signal with digital
command is always monitored inside the device. Each time a turn-on/turn-off signal is
output by the logic core its effectiveness is verified comparing it with the status of the output
voltage.
The main logic can check the consistence between inner logic and actual signal at output
pin reading the OpenLoad comparator or Short-To-Ground Comparator according to
Table 42.
The driver status diagnosis (STA) is activated by the MSC on command, the relative
comparator is filtered for Tsta filter time to validate the diagnosis. In case of MOS pre-driver
the selected blanking time Tblank is applied before filtering.

Table 41. Driver status diagnosis

Symbol Parameter Test condition Min Typ Max Unit Pin

Driver status
Tsta Tested by scan 30 32.5 35 µs -
diagnosis filter time

Table 42. STA diagnosis for drivers

STA diagnosis for drivers
INJ,SOL,O2H, RLY,
STR in high-side
- STR in Low-side MOS pre-driver IGN
configuration.
configuration
Detected by STG Detected by Open load Detected by STG
comparator, if the comparator, if the comparator, if the
Same information
ON state output pin voltage is output pin voltage is MOS_DRN pin voltage
as STG bit.
higher than VLVT, STA lower than V_OL, STA is higher than VLVT,
fault is detected fault is detected. STA fault is detected.
Detected by Open load
OFF state comparator or Short To Detected by STG Detected by Open
(for LS/HS/PDRV) Ground comparator. If comparator, if the load comparator, if the
the output pin voltage output pin voltage is MOS_DRN pin voltage Not able to detect.
LS_ON state
is lower than V_OL or higher than VLVT, STA is lower than V_OL,
(for IGN) lower than VLVT STA fault is detected. STA fault is detected.
fault is detected.
STA processing filtering filtering blanking+filtering filtering

Note: In case of activation of OVT[17] the STA diagnosis is not available.

In case of activation of relative driver OVC the STA diagnosis is available.

7.1.4 OFF state - short load and open load

The device provides off-state diagnosis for each driver channel. Simplified schematic of
implemented diagnosis is shown in Figure 30.

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L9788 Low-side drivers

Figure 30. Low-side driver OFF state diagnosis schematic

Vdd
+
VTOPEN Fast Pull Up
DIAGOL VBAT
-
I_LS_PU
VOUTOPEN +

gm
LOAD L/R
-
+ I_LS_PD
VTGND
DIAGLV OUTx
-

MSC Command
Driver

PGND
LowSide DRIVER
GADG0112161144PS

In the Low-Side Driver we can have three different load conditions as shown in Figure 31:

Figure 31. Low-side driver OFF state diagnosis load thresholds

V_OUTx
(low-side)

Normal
function
3V
V_OL min
VOUTOPEN max

VOUTOPEN Open Load

VOUTOPENmin

VLVTmax
1.9V

Short to
GND

GADG0112161201PS

_Normal Load: it means output driver connected to the load, No Fault Present, VOUT ≥
V_OL Threshold
_Open Load: It means output driver disconnected from the load, Open Load Fault Present,
VLVT ≤ VOUT ≤ V_OL Threshold
_Short To Ground: it means output driver shorted to GND voltage, Short To Gnd Fault
Present, VOUT ≤ VLVT Threshold
There is a bit IPUPD_EN in CONFIG_REG2 which is controlled by a MSC bit, that it is used
by external µController if it is needed to switch on/off both pull up and pull down diagnosis
current.

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The Diagnostic in Off state is done by the following blocks:

 An internal Buffer using the pull up/down currents is able to force the VOUTOPEN
voltage on the Low-Side Driver Output when the driver is in Open Load Condition.
 A comparator to detect the Open load Condition. The Open Load fault is detected when
the Low-Side output pin is VLVT ≤ VOUT ≤ V_OL Threshold for a time longer than Diag
Filter Time.
 A comparator to detect the Short to GND Condition. The Short to GND fault is detected
when the Low-Side output pin is VOUT <= VLVT Threshold for a time longer than Diag
Filter Time.
There is a bit IPUPD_MODE in CONFIG_REG2 which is controlled by a MSC bit, it is used
by external µController if it is needed to switch on/off the bigger diagnosis
current(I_LS_PU1) in fast mode.
The Fast pull up current is used to avoid the false short to tGND diagnosis when the driver
switches off in Open load condition. This current switches on after the falling edge of MSC
command (driver in off state) and remains on until the Diag Filter Time is expired or until the
VOUT is > VLVT Threshold.(note: if fast pull up current is selected, the filter time
Tflt_diagoff1 is suggested. Otherwise, the filter time Tflt_diagoff2 is suggested)

Figure 32. Low-side driver OFF state fast pull up current behavior

I_diag I_diag

I_LS_PU1 + I_LS_PU2 I_LS_PU1 + I_LS_PU2

I_LS_PU2 I_LS_PU2

Tflt_diagoff1 t t

Voutx Voutx

VLVT VLVT

Tflt_diagoff1 t Tflt_diagoff1 t

GADG0112161208PS

Despite the fast mode of all drivers in off diagnostic condition (Ipupd_MODE bit), for Injector
and Solenoid drivers there is a dedicated MSC bit (IDIAG_HIGH_SOL/IDIAG_HIGH_INJ in
CONFIG_REG13) for each kind of driver to select off diagnostic high or low pull up/down
current
By default diagnostic pull up/down currents are disabled and comparator outputs are
masked by internal logic, to enable OFF state diagnostic the channel must be put first in
tristate condition and then (if not already done with previous MSC frames) diagnostic must
be enabled.
A Filter Time (Diag Filter Time) is implemented in order to avoid detecting false diagnosis as
shown in Figure 33.

86/264 DS12308 Rev 4

L9788 Low-side drivers

Figure 33. Low-side driver OFF state diagnosis timings

LOW SIDE OUTPUT VOLTAGE LOW SIDE OUTPUT VOLTAGE

COMMAND OFF COMMAND OFF

V_OL V_OL
OPEN LOAD

VLVT VLVT

SHORT-TO-GROUND LOAD

VOUT VOUT

DIAG NO FAULT NO FAULT OFF FAULT DIAG NO FAULT OFF FAULT

OPEN LOAD SHORT-TO-GROUND LOAD

< Tflt_diagoff Tflt_diagoff t Tflt_diagoff t

LOW SIDE OUTPUT VOLTAGE LOW SIDE OUTPUT VOLTAGE

COMMAND OFF COMMAND OFF

NORMAL LOAD

V_OL V_OL

VLVT VLVT

SHORT-TO-GROUND LOAD
FASTCHARGE

VOUT VOUT

DIAG FAULT FAULT OFF FAULT

DIAG NO FAULT NO FAUT
SHORT-TO-GROUND LOAD

< Tflt_diagoff t < Tflt_diagoff Tflt_diagoff t

GADG0112161213PS

If DiagOL or DiagLV signals remain high for a time higher than Diag Filter Time the fault bit
is set and can be read by Read Diag Communication.
This bit is reset by every Read Diag Communication.

7.1.5 Error handling

Table 43. Low-side driver error handling

Detection Clear MSC
Type of error Action Restart condition
condition flag

Driver Diagnostic

Driver is put in off At MSC read of diagnosis

state. The fault is register if MSC command is
Overcurrent (OVC) Driver on On read
latched in MSC still high. If MSC command
diagnosis register. is low and high again.
The fault is latched in
Short to ground (STG) Driver off MSC diagnosis On read -
register.
The fault is latched in
Open load (OPL) Driver off MSC diagnosis On read -
register.

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Table 43. Low-side driver error handling (continued)

Detection Clear MSC
Type of error Action Restart condition
condition flag

Driver on/off
When the driver The fault is latched in
Driver Status Error (STA) output level is not MSC diagnosis On read -
aligned with the register.
command on/off
Driver is put in off
The driver restarts when the
Overtemperature (OVT) state. The fault is
Driver on On read temperature decreases. The
Shutdown latched in MSC
fault is cleared at MSC read.
diagnosis register.

7.2 Low-side driver - INJECTOR INJ[1:4]

These 4 low-side drivers are designed to driver Injector Load. They are driven by MSC
command. The output voltage is clamped to voltage limit by internal clamp circuit.

Figure 34. INJECTOR LowSide driver stage

OFF state
OL & STG detection VBAT
ON state INJ LOAD
OC & OT protection
Safety BIST control L/R

OUT1/2/3/4

MSC Command
Driver

PGND

INJECTOR DRIVER

GADG0212160751PS

Conditions:
5.5 V ≤ VB_IN ≤ 18 V; Tj -40 to 175 °C unless otherwise specified;

Table 44. Low-side driver - INJECTOR electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

INJECTOR

LS_RdsON Low-side RdsON Tj = 150 °C, ILOAD = 3 A 0.35 0.44 0,6 Ω INJ1/2/3/4

LS_RdsON - Tj = 25°C,ILOAD = 3 A 0.22 0.3 0.31 Ω INJ1/2/3/4

LS_RdsON - Tj = -40 °C, ILOAD = 3 A 0.15 0.2 0.25 Ω INJ1/2/3/4

88/264 DS12308 Rev 4

L9788 Low-side drivers

Table 44. Low-side driver - INJECTOR electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Output leakage Output disabled,

OUTx_lkg -10 - 10 µA INJ1/2/3/4
current diagnostic off
Body Diode
Irev_OUTx reverse current ILOAD = -2 A - - 2 V INJ1/2/3/4
voltage drop
From 80% to 30% of
Voltage slew ON VOUT, VB_IN = 14 V,
SR_ON 0.6 - 1.84 V/µs INJ1/2/3/4
State Rload = 15Ω,
Cload = 10 nF
From 80% to 30% of
Voltage slew OFF VOUT, VB_IN = 14 V,
SR_OFF 0.6 - 1.84 V/µs INJ1/2/3/4
State Rload = 15Ω,
Cload = 10 nF
From 30% to 80% of
FAST VS/R off
VOUT, VB_IN = 14 V,
S/RGkill_LSH when and OVC 5 - 20 V/µs INJ1/2/3/4
Rload = 15Ω,
fault happens
Cload = 10 nF
Propagation Delay
from MSC_EN VB_IN = 14 V,
Ton_OUTx rising edge to 80% Rload = 15Ω, - - 8 µs INJ1/2/3/4
output OUTx Cload = 10 nF
voltage
Propagation Delay
from MSC_EN VB_IN = 14 V,
Toff_OUTx falling edge to 20% Rload = 15Ω, - - 8 µs INJ1/2/3/4
output OUTx Cload = 10 nF
voltage
OUTx clamping
clamp_OUTx ILOAD = 1.3 A 50 55 60 V INJ1/2/3/4
Voltage
ILOAD = 3 A
Guaranteed by design,
Vclamp_OUTx_ OUTx clamping provided single pulse 50 55 60 V INJ1/2/3/4
high_curr Voltage energy limits are not
violated by clamping
action
Over Current
IOVC_OUTx - 3 - 6 A INJ1/2/3/4
Driver Threshold
LS overcurrent
I_LS_ocv_flt Guaranteed by scan 4 - 7 µs INJ1/2/3/4
filter time
Temperature shut
T_SD_HIGH - 185 - 200 °C INJ1/2/3/4
down
Temperature shut
T_SD_LOW - 175 - 190 °C INJ1/2/3/4
down recover
Temperature shut
T_SD_hys - 5 10 °C INJ1/2/3/4
down hysteresis

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263
Low-side drivers L9788

Table 44. Low-side driver - INJECTOR electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Thermal shutdown
tmsd_pre_an Guaranteed by design 1.5 - 4 µs INJ1/2/3/4
analog filter time
Digital deglitch
filter time on
t_SD_deglitch Guaranteed by scan - 10 - µs INJ1/2/3/4
Temperature shut
down detection

Driver Reliability Data

Tcase = 30 °C;
Energy repetitive
EnergyRep INJ I_OUT_n = 1.8 A,  - - 7.5 mJ INJ1/2/3/4
pulse
18 Miopulses
Tcase= 115 °C; 
Energy repetitive
EnergyRep INJ I_OUT_n = 1.4 A  - - 4 mJ INJ1/2/3/4
pulse
648 Miopulses
Tcase= 130 °C;
Energy repetitive
EnergyRep INJ I_OUT_n = 1 A - - 3 mJ INJ1/2/3/4
pulse
96 Miopulses
Tcase= 140 °C;
Energy repetitive
EnergyRep INJ I_OUT_n = 1 A - - 3 mJ INJ1/2/3/4
pulse
4 Miopulses

Driver Reliability Data Generator Defect

Tcase= 25 °C ;
Energy repetitive
EnergyRep INJ I_OUT_n = 2 A - - 9 mJ INJ1/2/3/4
pulse
0.5 Miopulses
Tcase= 135 °C;
Energy repetitive
[EnergyRep INJ I_OUT_n = 1.5 A - - 8 mJ INJ1/2/3/4
pulse
0.5 Miopulses

Driver Reliability Data jump start

Tcase= 25 °C;
I_OT_n = 3.0 A
Energy repetitive
EnergyRep INJ MAX.0.021Mio cycles - - 17.5 mJ INJ1/2/3/4
pulse
10 jumps starts over
liftime, each start < 2min
Tc=75°C ; I_OT_n=2.3A
Energy repetitive MAX.0.021Mio cycles
EnergyRep INJ - - 10 mJ INJ1/2/3/4
pulse 10jumps starts over
liftime,each start<2min

OFF state diagnostic

Short to GND Driver tristate, diag VOUTOPEN

VLVT 1.9 - V INJ1/2/3/4
threshold voltage enabled -180 mV
Open load Driver tristate, diag VOUTOPEN
V_OL - 3 V INJ1/2/3/4
threshold voltage enabled +160 mV
Open load Driver tristate, diag
VOUTOPEN 2.3 2.5 2.7 V INJ1/2/3/4
threshold voltage enabled

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L9788 Low-side drivers

Table 44. Low-side driver - INJECTOR electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

In OFF condition, OUTx

Diagnostic pull up < VLVT, Ipupd_EN
I_LS_PU1 2.5 3.6 4.7 mA INJ1/2/3/4
current =ENB,
Ipupd_MODE = "1"
In OFF condition, 
OUTx < VLVT,
Diagnostic pull up
I_LS_PU2 Ipupd_EN = ENB, 40 70 100 µA INJ1/2/3/4
low current
Ipupd_MODE = "0" and
IDIAG_HIGH_INJ = "0"
In OFF condition,
OUTx < VLVT,
Diagnostic pull up
I_LS_PU3 Ipupd_EN = ENB, 100 - 200 µA INJ1/2/3/4
high current
Ipupd_MODE = "0" and
IDIAG_HIGH_INJ = "1"
In OFF condition,
Diagnostic pull OUTx > VOUTOPEN,
I_LS_PD1 60 85 110 µA INJ1/2/3/4
down low current Ipupd_EN = ENB
IDIAG_HIGH_INJ = "0"
In OFF condition,
Diagnostic pull OUTx > VOUTOPEN,
I_LS_PD2 325 - 550 µA INJ1/2/3/4
down high current Ipupd_EN = ENB
IDIAG_HIGH_INJ = "1"
Tflt_diagoff1 DIAG Filter time Filter Mode = 0 75 100 125 µs INJ1/2/3/4

Tflt_diagoff2 DIAG Filter time Filter Mode = 1 450 600 750 µs INJ1/2/3/4

Minimum OFF time Application note (esd

- for correct cap < 10nF) 175 - - µs ESVx
diagnostic Filter Mode=0

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7.2.1 Enable pin INJ_ENA

The Pin INJ_ENA is a digital input pin that is used as enable of Injector driver. If this pin is at
low digital level the internal logic drives all injector drivers in OFF state. If this pin is at high
digital, all injector drivers can be switched on by dedicated MSC bit. This pin can be used
also as a SEO function for injector driver. If the application doesn't use this enable function,
the INJ_ENA pin have to be pulled up externally to VDD5 by a resistor of 10 kΩ.
Conditions:
5.5 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified.

Table 45. INJ_ENA electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

VIH_TX HIGH_level input voltage - 1.75 - - V INJ_ENA

VIL_TX LOW_level input voltage - - - 0.75 V INJ_ENA

VHYS_TX Input voltage hysteresis - 0.1 0.5 - V INJ_ENA

PDOWN_TX Pull-down resistance - 50 100 200 kΩ INJ_ENA

7.3 Low-side driver - O2 HEATER O2H[1:2]

These 2 LowSide drivers are designed to driver O2 heater Load. They are driven by MSC
command. The Output voltage is clamped to voltage limit by internal clamp circuit. O2
channel can be configured as valve driver with faster slew rate and lower over current
threshold by MSC commands. Current sense generates on Curr_sense_O2H pin a reduced
copy of the current flowing through O2H Power. Current sense current generator is done
with a P-channel current mirror connected to VDD5_IN, for this reason voltage on
Curr_sense_O2H1 and Curr_sense_O2H2 pins can never exceed VDD5_IN.

Figure 35. O2 heater LowSide driver stage

OFF state
OL & STG detection VBAT
ON state O2 heater
OC & OT protection
Safety BIST control L/R

OUTx

MSC Command
Driver

PGND

O2H DRIVER
GADG0112161309PS

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L9788 Low-side drivers

Figure 36. O2 Heater LowSide driver current sense block

VDDS_IN

Curr_sense_O2H1/2

+ O2H1/2
Nȍ -

PGND

MSC_Command driver

GADG0212160756PS

Conditions:
5.5 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified.

Table 46. Low-side driver - O2 HEATER electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

O2H

Tj = 150 °C, ILOAD = 3 A 0.047 0.16 0.216 Ω O2H1/2

LS_RdsON Low-side RdsON Tj = 25 °C, ILOAD = 3 A 0.04 0.12 0.155 Ω O2H1/2
Tj = -40 °C, ILOAD = 3 A 0.03 0.9 0.12 Ω O2H1/2
Output leakage Output disabled, diagnostic
OUTx_lkg -10 - +10 µA O2H1/2
current off Vpin = 13.5 V
Body diode reverse
Irev_OUTx I = -2 A - - 2 V O2H1/2
current voltage drop LOAD
From 80% to 30% of VOUT
Voltage slew ON VB_IN = 14 V, Rload = 3 Ω,
SR_ON 0.2 - 0.8 V/µs O2H1/2
State Cload = 10 nF; configure as
O2
From 80% to 30% of VOUT
Fast voltage slew VB_IN = 14 V, Rload = 3 Ω,
SR_ON_fast 2 - 6 V/µs O2H1/2
ON State Cload = 10 nF; configure as
sol, fast slew rate
From 30% to 80% of VOUT
Voltage slew OFF VB_IN = 14 V, Rload = 3 Ω,
SR_OFF 0.2 - 0.8 V/µs O2H1/2
state Cload = 10 nF; configure as
O2
From 30% to 80% of VOUT
Fast Voltage slew VB_IN = 14 V, Rload = 3 Ω,
SR_OFF_fast 2 - 6 V/µs O2H1/2
OFF State Cload = 10 nF; configure as
sol, fast slew rate

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Table 46. Low-side driver - O2 HEATER electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

FAST VS/R off when From 30% to 80% of VOUT

S/RGkill_LSH an OVC fault VB_IN = 14 V, Rload = 3 Ω, 5 - 20 V/µs O2H1/2
happens Cload = 10 nF
Propagation Delay
from MSC_EN rising VB_IN = 14 V, Rload = 3 Ω,
Ton_OUTx - - 12 µs O2H1/2
edge to 80% output Cload = 10 nF
OUTx voltage
Propagation Delay
from MSC_EN VB_IN = 14 V, Rload = 3 Ω,
Toff_OUTx - - 10 µs O2H1/2
falling edge to 20% Cload = 10 nF
output OUTx voltage
OUTx clamping
Vclamp_OUTx ILOAD = 1.3 A 45 50 55 V O2H1/2
Voltage
ILOAD = 1.3 A
Guaranteed by design,
Vclamp_OUTx_ OUTx clamping
provided single pulse energy 45 50 55 V O2H1/2
high_curr Voltage
limits are not violated by
clamping action
Over current driver
I_ovc1_o2h configure as sol 3 4.5 6 A O2H1/2
threshold 1
Over current driver
I_ovc2_o2h Tj = -40 °C configured as O2 8.6 - 12.4 A O2H1/2
threshold 2
Over current driver Tj = +25 °C configured as
I_ovc2_o2h 8.0 - 11.2 A O2H1/2
threshold 2 O2
Over current driver Tj = +150 °C configured as
I_ovc2_o2h 7.8 - 10.5 A O2H1/2
threshold 2 O2
LS overcurrent filter
I_LS_ocv_flt Guaranteed by scan 4 - 7 µs O2H1/2
time
Temperature shut
T_SD_HIGH - 185 - 200 °C O2H1/2
down
Temperature shut
T_SD_LOW - 175 - 190 °C O2H1/2
down recover
Temperature shut
T_SD_hys - 5 - 10 °C O2H1/2
down hysteresis
Thermal shutdown
tmsd_pre_an Guaranteed by design 1.5 - 4 µs O2H1/2
analog filter time
Digital deglitch filter
t_SD_deglitch time on Temperature Guaranteed by scan - 10 - µs O2H1/2
shut down detection

Driver reliability data

Energy repetitive Tcase = 25 °C ; I_OT_n

EnergyRep O2H - - 15 mJ O2H1/2
pulses =1.5A 18 Miopulses
Energy repetitive Tcase= 115 °C ; I_OT_n =
EnergyRep O2H - - 10 mJ O2H1/2
pulses 1.2A 648 Miopulses

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L9788 Low-side drivers

Table 46. Low-side driver - O2 HEATER electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Energy repetitive Tcase= 130 °C ; I_OT_n =

EnergyRep O2H - - 9 mJ O2H1/2
pulses 1.0A 96 Miopulses
Energy repetitive Tcase= 140 °C ; I_OT_n =
EnergyRep O2H - - 9 mJ O2H1/2
pulses 1.0A 4 Miopulses

Driver Reliability Data jump start

Tcase= 25 °C ; I_OT_n =
Energy repetitive 2.2A 0.021 Miopulses 10
EnergyRep O2H - - 30 mJ O2H1/2
pulses jumps starts over lifetime,
each start<2
Tcase = 75 °C ; I_OT_n =
Energy repetitive 1.8A 0.021 Miopulses 10
EnergyRep O2H - - 18 mJ O2H1/2
pulses jumps starts over lifetime,
each start < 2

Driver reliability data generator defect

Energy repetitive Tcase = 25 °C ; I_OT_n =

EnergyRep O2H - - 17.5 mJ O2H1/2
pulses 1.6A 0.5 Miopulses
Energy repetitive Tcase = 135 °C ; I_OT_n =
EnergyRep O2H - - 10 mJ O2H1/2
pulses 1.1 A 0.5 Miopulses

OFF state diagnostic

VOUT
Short to GND OPEN
VLVT Driver tristate, diag enabled 1.9 2.1 V O2H1/2
threshold voltage -180
mV
VOUT
Open load threshold OPEN
V_OL Driver tristate, diag enabled 2.9 3.0 V O2H1/2
voltage +160
mV
VOL Open load voltage Driver tristate, diag enabled 2.3 2.5 2.7 V O2H1/2
In OFF condition,
Diagnostic pull up OUTx < VLVT,
I_LS_PU1 2.5 3.6 4.7 mA O2H1/2
current Ipupd_EN = ENB,
Ipupd_MODE = ”1”
In OFF condition,
Diagnostic pull up OUTx < VLVT,
I_LS_PU2 40 70 100 µA O2H1/2
current Ipupd_EN = ENB,
Ipupd_MODE = ”0”
In OFF condition,
Diagnostic pull down
I_LS_PD1 OUTx > VOUTOPEN, 60 85 105 µA O2H1/2
current
Ipupd_EN = ENB
Tflt_diagoff1 DIAG Filter time Filter Mode = 0 75 100 125 µs O2H1/2
Tflt_diagoff2 DIAG Filter time Filter Mode = 1 450 600 750 µs O2H1/2

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Table 46. Low-side driver - O2 HEATER electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Minimum OFF time Application note (esd cap <

- for correct 10 nF,) 175 - - µs O2H1/2
diagnostic Filter Mode = 0

Current sensing characteristics

Transresistance Curr_Sense
Gain_sense - 0.8 V/A
sense gain _O2H1/2
Output voltage AD Curr_Sense
V_OUT_0p5A Rext = 5.1 kΩ 0.32 0.4 0.55 V
for Ipower = 0.5 A _O2H1/2
Output voltage AD Curr_Sense
V_OUT_1A Rext = 5.1 kΩ 0.64 0.8 0.96 V
for Ipower = 1 A _O2H1/2
Output voltage AD Curr_Sense
V_OUT_2A Rext = 5.1 kΩ 1.44 1.6 1.76 V
for Ipower = 2 A _O2H1/2
Output voltage AD Curr_Sense
V_OUT_3A Rext = 5.1 kΩ 2.16 2.4 2.64 V
for Ipower = 3 A _O2H1/2
Output voltage AD Curr_Sense
V_OUT_4A Rext = 5.1 kΩ 2.88 3.2 3.52 V
for Ipower = 4 A _O2H1/2

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L9788 Low-side drivers

7.4 Low-side driver - SOLENOID SOL [1:2]

These 2 LowSide drivers are designed to driver Solenoid Valves Load. They are driven by
MSC command.The Output voltage is clamped to voltage limit by internal clamp circuit.

Figure 37. Solenoid valves LowSide driver stage

OFF state
OL & STG detection VBAT
ON state Valve
OC & OT protection
Safety BIST control L/R

OUT7/8

MSC Command
Driver

PGND

Solenoid Valve DRIVER

GADG0212160929PS

Conditions:
5.5 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified.

Table 47. Low-side driver - SOLENOID VALVE electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

Solenoid valves

LS_RdsON Low-side RdsON Tj = 150 °C, ILOAD = 3 A 0.24 0.35 0.47 Ω SOL1/2
LS_RdsON Low-side RdsON Tj = 25 °C, ILOAD = 3 A 0.17 0.22 0.29 Ω SOL1/2
LS_RdsON Low-side RdsON Tj = -40 °C, ILOAD = 3 A 0.12 0.17 0.2 Ω SOL1/2
Output disabled, diagnostic
OUTx_lkg Output leakage current -10 - +10 µA SOL1/2
off Vpin = 13.5 V
Body diode reverse
Irev_OUTx ILOAD = -2 A - - 2 V SOL1/2
current voltage drop
From 80% to 30% of VOUT
SR_ON Voltage slew ON state VB_IN = 14 V, Rload = 15 Ω, 0.6 - 1.75 V/µs SOL1/2
Cload = 10 nF
From 30% to 80% of VOUT
SR_OFF Voltage slew OFF state VB_IN = 14 V, Rload = 15 Ω, 0.6 - 1.75 V/µs SOL1/2
Cload = 10 nF
From 30% to 80%of VOUT
FAST VS/R off when an
S/RGkill_LSH VB_IN = 14 V, Rload = 15 Ω, 5 - 20 V/µs SOL1/2
OVC fault happens
Cload = 10 nF

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263
Low-side drivers L9788

Table 47. Low-side driver - SOLENOID VALVE electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Propagation delay from

MSC_EN rising edge to VB_IN = 14 V, Rload = 15 Ω,
Ton_OUTx - - 8 µs SOL1/2
80% output OUTx Cload = 10 nF
voltage
Propagation delay from
MSC_EN falling edge to VB_IN = 14 V, Rload = 15 Ω,
Toff_OUTx - - 8 µs SOL1/2
20% output OUTx Cload = 10 nF
voltage
Vclamp_OUTx OUTx clamping voltage ILOAD = 1.3 A 50 55 60 V SOL1/2
ILOAD = 3 A
Vclamp_OUTx Guaranteed by design,
OUTx clamping voltage provided single pulse 50 55 60 V SOL1/2
_high_curr
energy limits are not
violated by clamping action
Over current driver
I_ovc_sol - 3 4.5 6 A SOL1/2
threshold
I_LS_ocv_flt LS overcurrent filter time Guaranteed by scan 4 - 7 µs SOL1/2
T_SD_HIGH Temperature shut down - 185 - 200 °C SOL1/2
Temperature shut down
T_SD_LOW - 175 - 190 °C SOL1/2
recover
Temperature shut down
T_SD_hys - 5 - 10 °C SOL1/2
hysteresis
Thermal shutdown
- Guaranteed by design 1.5 - 4 µs SOL1/2
analog filter time
Digital deglitch filter time
t_SD_deglitch on Temperature shut Guaranteed by scan - 10 - µs SOL1/2
down detection

OFF state diagnostic

VOUT
Short to GND threshold
VLVT Driver tristate, diag enabled 1.9 2.1 OPEN V SOL1/2
voltage
-180mV
VOUT
Open load threshold
V_OL Driver tristate, diag enabled OPEN 2.9 3.0 V SOL1/2
voltage
+160mV
VOL Open load voltage Driver tristate, diag enabled 2.3 2.5 2.7 V SOL1/2
In OFF condition,
Diagnostic pull up OUTx < VLVT,
I_LS_PU1 2.5 3.6 4.7 mA SOL1/2
current Ipupd_EN = ENB,
Ipupd_MODE =”1”
In OFF condition,
OUTx < VLVT,
Diagnostic pull up
I_LS_PU2 Ipupd_EN = ENB, 40 70 100 µA SOL1/2
current
Ipupd_MODE =”0” and
IDIAG_HIGH_SOL =”0”

98/264 DS12308 Rev 4

L9788 Low-side drivers

Table 47. Low-side driver - SOLENOID VALVE electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

In OFF condition,
OUTx < VLVT,
Diagnostic pull up high
I_LS_PU3 Ipupd_EN=ENB,Ipupd_MO 100 200 µA SOL1/2
current
DE=”0” and
IDIAG_HIGH_SOL =”1”
In OFF condition,
Diagnostic pull down OUTx > VOUTOPEN,
I_LS_PD1 60 85 105 µA SOL1/2
current Ipupd_EN = ENB and
IDIAG_HIGH_SOL =”0”
In OFF condition,
Diagnostic pull down OUTx > VOUTOPEN,
II_LS_PD2 325 - 550 µA SOL1/2
high current Ipupd_EN = ENB
IDIAG_HIGH_SOL =”1”
Tflt_diagoff1 DIAG filter time Filter mode = 0 75 100 125 µs SOL1/2
Tflt_diagoff2 DIAG filter time Filter mode = 1 450 600 750 µs SOL1/2
Application note
Minimum OFF time for
- (esd cap < 10nF,) 175 - - µs SOL1/2
correct diagnostic
Filter Mode=0

Driver reliability data

Energy_Rep_ Tcase = 25 °C ; I_OT_n

Energy repetitive pulses - - 15 mJ SOL1/2
SOL =1.5A 18 Miopulses
Energy_Rep_ Tcase = 115 °C ; I_OT_n =
Energy repetitive pulses - - 10 mJ SOL1/2
SOL 1.2 A 648 Miopulses
Energy_Rep_ Tcase = 130 °C ; I_OT_n =
Energy repetitive pulses - - 9 mJ SOL1/2
SOL 1.0 A 96 Miopulses
Energy_Rep_ Tcase = 140 °C ; I_OT_n =
Energy repetitive pulses - - 9 mJ SOL1/2
SOL 1.0 A 4 Miopulses

Driver reliability data generator defect

Energy_Rep_ Tcase = 25 °C ; I_OT_n =

Energy repetitive pulses - - 17.5 mJ SOL1/2
SOL 1.6 A 0.5 Miopulses
Energy_Rep_ Tcase = 135 °C ; I_OT_n =
Energy repetitive pulses - - 10 mJ SOL1/2
SOL 1.1 A 0.5 Miopulses

Driver reliability data JUMP START

Tcase = 25 °C ; I_OT_n =
Energy_Rep_ 2.2 A 0.021 Miopulses 10
Energy repetitive pulses - - 30 mJ SOL1/2
SOL jumps starts over lifetime,
each start < 2 min
Tcase = 75 °C ; I_OT_n =
Energy_Rep_ 1.8 A 0.021 Miopulses
Energy repetitive pulses - - 18 mJ SOL1/2
SOL 10jumps starts over
lifetime, each start < 2 min

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Low-side drivers L9788

7.5 Low-side driver - RELAY RLY [1:5]

These 5 LowSide drivers are optimized for relay or generic low current loads driving. They
are driven by MSC command. The Output voltage is clamped to voltage limit by internal
clamp circuit.
Each relay driver is separately put in on or off state by the MSC CONFIG-REG 14 [0:4] just
for the time required to perform on or off diagnosis (Fast Diagnosis). At the end of the
diagnosis it is automatically put in the state determined by the current value of MSC data
frame.
The micro command is activated by writing 1 from 0 in the MSC registers (both for ON and
OFF).

Figure 38. Relay LowSide driver stage

OFF state
OL & STG detection VBAT
ON state
OC & OT protection
Relay

OUTx

MSC Command
Driver
Chip en

PGND

RELAY DRIVER

GADG0212161126PS

Conditions:
5.5 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified; the RLY4 can be
associated to DELAY_OFF function if the MSC CONFIG_REG_3 [0] = RLY4_DLY_OFF_EN
is set. In this case the RLY4 is configured as starter and can work down to VB_IN = 3.1 V for
THOLD.

Table 48. Low-side driver - RELAY electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

Relay

LS_RdsON Low-side RdsON Tj = 150 °C, ILOAD = 1 A - - 1.5 Ω RLY/1/2/3/4/5

LS_RdsON Low-side RdsON Tj = 25 °C, ILOAD = 1 A - - 0.82 Ω RLY/1/2/3/4/5

LS_RdsON Low-side RdsON Tj = 40 °C, ILOAD = 1 A - - 0.63 Ω RLY/1/2/3/4/5

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L9788 Low-side drivers

Table 48. Low-side driver - RELAY electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

LS_RdsON_ VB_IN = 3.1 V,

Low-side RdsON - - 3 Ω RLY4
RL4 ILOAD = 0.6 A

Output leakage Output disabled,

OUTx_lkg -10 - +10 µA RLY/1/2/3/4/5
current diagnostic off

Body diode reverse

Irev_OUTx ILOAD = -0.6 A - - 2 V RLY/1/2/3/4/5
current voltage drop

From 80% to 30% of

Voltage slew ON VOUT, VB_IN = 14 V,
SR_ON 0.4 - 2.1 V/µs RLY/1/2/3/4/5
State Rload = 68 Ω
Cload = 10 nF
From 30% to 80% of
Voltage slew OFF VOUT, VB_IN = 14 V,
SR_OFF 0.4 - 2.1 V/µs RLY/1/2/3/4/5
State Rload = 68 Ω
Cload = 10 nF
From 30% to 80% of
FAST VS/R off when
VOUT, VB_IN = 14 V,
S/RGkill an OVC fault 5 - 20 V/µs RLY/1/2/3/4/5
Rload = 68 Ω
happens
Cload = 10 nF
Propagation Delay
VOUT, VB_IN = 14 V,
from MSC_EN rising
Ton_OUTx Rload = 68 Ω - - 10 µs RLY/1/2/3/4/5
edge to 80% output
Cload = 10 nF
OUTx voltage
Propagation Delay
VB_IN = 14 V,
from MSC_EN falling
Toff_OUTx Rload = 68 Ω - - 10 µs RLY/1/2/3/4/5
edge to 20% output
Cload = 10 nF
OUTx voltage

OUTx clamping
Vclamp_OUTx ILOAD = 0.6 A 45 - 55 V RLY/1/2/3/4/5
Voltage

ILOAD = 1 A
Guaranteed by design,
Vclamp_OUTx OUTx clamping provided single pulse 45 - 55 V RLY/1/2/3/4/5
_high_curr Voltage energy limits are not
violated by clamping
action

Over current driver

- - 1 1.5 2 A RLY/1/2/3/4/5
threshold

LS overcurrent filter
I_LS_ocv_flt Guaranteed by scan 4 - 7 µs RLY/1/2/3/4/5
time

Temperature shut
T_SD_HIGH - 185 - 200 °C RLY/1/2/3/4/5
down

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263
Low-side drivers L9788

Table 48. Low-side driver - RELAY electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Temperature shut
T_SD_LOW - 175 - 190 °C RLY/1/2/3/4/5
down recover

Temperature shut
T_SD_hys - 5 - 10 °C RLY/1/2/3/4/5
down hysteresis

Thermal shutdown
- Guaranteed by design 1.5 4 µs RLY/1/2/3/4/5
analog filter time

Digital deglitch filter

t_SD_deglitch time on Temperature Guaranteed by scan - 10 - µs RLY/1/2/3/4/5
shut down detection

Driver reliability data

Tcase = 25 °C;
Energy repetitive
EnergyRep RLY I_OT_n = 0.45 A - - 9 mJ RLY/1/2/3/4/5
pulses
1.1 Miopulses
Tcase = 115 °C;
Energy repetitive
EnergyRep RLY I_OT_n = 0.3 A - - 6.5 mJ RLY/1/2/3/4/5
pulses
40 Miopulses
Tcase = 130 °C;
Energy repetitive
EnergyRep RLY I_OT_n = 0.3 A - - 6.5 mJ RLY/1/2/3/4/5
pulses
9 Miopulses
Tcase = 140 °C;
Energy repetitive
EnergyRep RLY I_OT_n = 0.3 A - - 6.5 mJ RLY/1/2/3/4/5
pulses
1 Miopulses

Driver reliability data generator defect

Tcase = 25 °C;
Energy repetitive
EnergyRep RLY I_OT_n = 0.5 A - - 11 mJ RLY/1/2/3/4/5
pulses
0.02 Miopulses
Tc=135°C;
Energy repetitive
EnergyRep RLY I_OT_n = 0.35 A - - 8 mJ RLY/1/2/3/4/5
pulses
0.02 Miopulses

Driver reliability data JUMP START

Tcase = 25 °C;
I_OT_n = 0.75 A
Energy repetitive 0.001 Miopulses,
EnergyRep RLY - - 25 mJ RLY/1/2/3/4/5
pulses 10 jumps starts over
lifetime,
each start < 2 min
Tc=75°C ; I_OT_n=0.5A
0.001Miopulses, 
Energy repetitive
EnergyRep RLY 10 jumps starts over - - 17 mJ RLY/1/2/3/4/5
pulses
lifetime,
each start < 2 min

102/264 DS12308 Rev 4

L9788 Low-side drivers

Table 48. Low-side driver - RELAY electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

OFF state diagnostic

VOUTO
Short to GND Driver tristate, diag
VLVT 1.9 PEN V RLY/1/2/3/4/5
threshold voltage enabled
-180mV
VOUTO
Open load threshold Driver tristate, diag
V_OL PEN 3.0 V RLY/1/2/3/4/5
voltage enabled
+160mV

Open load output Driver tristate, diag

VOUTOPEN 2.3 2.5 2.7 V RLY/1/2/3/4/5
voltage enabled

In OFF condition,
Diagnostic pull up OUTx < VLVT,
I_LS_PU1 2.3 3.6 4.7 mA RLY/1/2/3/4/5
current Ipupd_EN = ENB,
Ipupd_MODE =”1”
In OFF condition,
Diagnostic pull up OUTx < VLVT,
I_LS_PU2 40 70 100 µA RLY/1/2/3/4/5
current Ipupd_EN = ENB,
Ipupd_MODE = ”0”
In OFF condition,
Diagnostic pull down
I_LS_PD1 OUTx > VOUTOPEN, 60 85 105 µA RLY/1/2/3/4/5
current
Ipupd_EN = ENB

Tflt_diagoff1 DIAG Filter time Filter Mode=0 75 100 125 µs RLY/1/2/3/4/5

Tflt_diagoff2 DIAG Filter time Filter Mode=1 450 600 750 µs RLY/1/2/3/4/5

Application note (esd cap

Minimum OFF time < 10 nF,)
- 175 - - µs RLY/1/2/3/4/5
for correct diagnostic
Filter Mode = 0

Fast OFF diagnostic

- Filter Mode = 0 175 200 225 µs RLY/1/2/3/4/5
ON→OFF→ON

Fast ON diagnostic
- - 72 90 µs RLY/1/2/3/4/5
OFF→ON→OFF

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263
Low-side drivers L9788

7.6 Low-side driver - LED[1:2]

These 2 LowSide drivers are designed to drive LED Load. They are driven by MSC
command. The Output voltage is clamped to voltage limit by internal clamp circuit.
The pull down diagnostic current of LED driver is configurable by MSC (LEDx_PD_EN
CONFIG_REG1 D3;D4). Overcurrent and Short to Ground diagnostic function are available,
open load diagnostic function is not available when pull down diagnostic current is disabled.

Figure 39. LED LowSide driver stage

OFF state
OL & STG detection VBAT
ON state LOAD
OC & OT protection
Safety BIST control L/R

OUTx

MSC Command
Driver

PGND

LED DRIVER

GADG0212161301PS

Conditions:
5.5 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified;

Table 49. Low-side driver - LED electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

LED

Tj = 150 °C, ILOAD = 70 mA 10 14 20 Ω LED1/2

Low-side
LS_RdsON Tj = 25 °C, ILOAD = 70 mA 6 8 12 Ω LED1/2
RdsON
Tj = -40 °C, ILOAD = 70 mA 4.9 6 9 Ω LED1/2
Output leakage Output disabled, diagnostic
OUTx_lkg -10 - +10 µA LED1/2
current off
Body diode
Irev_OUTx reverse current ILOAD = -50 mA - - 2 V LED1/2
voltage drop
Voltage slew From 80% to 30% of VOUT
SR_ON 10 - 25 V/µs LED1/2
ON state VB_IN = 14 V, Rload = 270 Ω,
Voltage slew From 30% to 80%of VOUT
SR_OFF 14 - 21 V/µs LED1/2
OFF state VB_IN = 14 V, Rload = 270 Ω

104/264 DS12308 Rev 4

L9788 Low-side drivers

Table 49. Low-side driver - LED electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Propagation
Delay from
MSC_EN rising
Ton_OUTx VB_IN = 14 V, Rload=270 Ω, - - 5 µs LED1/2
edge to 80%
output OUTx
voltage
Propagation
Delay from
MSC_EN
Toff_OUTx VB_IN = 14 V, Rload=270 Ω, - - 5 µs LED1/2
falling edge to
20% output
OUTx voltage
OUTx clamping
Vclamp_OUTx ILOAD = 50 mA 40 45 50 V LED1/2
Voltage
ILOAD = 70 mA
Vclamp_OUTx_ OUTx clamping Guaranteed by design,
provided single pulse energy 40 45 50 V LED1/2
high_curr Voltage
limits are not violated by
clamping action
Over current
IOVC_OUTx - 70 - 110 mA LED1/2
driver threshold
LS overcurrent
I_LS_ocv_flt Guaranteed by scan 4 - 7 µs LED1/2
filter time
Short to GND
VOUTOPEN
VLVT threshold Driver tristate, diag enabled 1.9 - V LED1/2
-180mV
voltage
Open load
VOUTOPEN
V_OL threshold Driver tristate, diag enabled - 3 V LED1/2
+160mV
voltage
Open load
VOUTOPEN Driver tristate, diag enabled 2.3 2.5 2.7 V LED1/2
voltage
In OFF condition,
Diagnostic pull OUTx < VLVT,
I_LS_PU1 2.5 3.6 4.7 mA LED1/2
up current Ipupd_EN = ENB,
Ipupd_MODE = ”1”
In OFF condition,
Diagnostic pull OUTx < VLVT,
I_LS_PU2 40 70 100 µA LED1/2
up current Ipupd_EN = ENB,
Ipupd_MODE =”0”
In OFF condition,
Diagnostic pull OUTx > VOUTOPEN,
I_LS_PD1 60 85 105 µA LED1/2
down current Ipupd_EN = ENB
LEDx_PD_EN = 1
Tflt_diagoff1 DIAG filter time Filter Mode = 0 75 100 125 µs LED1/2

DS12308 Rev 4 105/264

263
Low-side drivers L9788

Table 49. Low-side driver - LED electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

DIAG Filter
Tflt_diagoff2 Filter Mode = 1 450 600 750 µs LED1/2
time

Minimum OFF Application note

- time for correct (esd cap < 10nF,) 175 - - µs LED1/2
diagnostic Filter Mode=0

106/264 DS12308 Rev 4

L9788 High/low-side drivers - STARTER STR[1:3]

8 High/low-side drivers - STARTER STR[1:3]

These 3 high/low-side drivers with diagnosis and overcurrent protection have a floating
architecture and can be used in high-side or low-side mode.
The configuration is defined by MSC bit (LSD/HSD_DRVx-CFG CONFIG_REG3 D1~D3).
The driver is optimized for relay and low-current loads, and it can be associated to smart
starter functional block.
They are driven by MSC command. The Output voltage is clamped to voltage limit by
internal clamp circuit. In order to guarantee a negligible output current in case of LED
application an internal dedicated comparator is present. This comparator, in case of high-
side configuration, Diagoff disabled and channel OFF, determines the disabling of internal
driver in case of output voltage (STR_SRC) pin in the range of -0.4V typ < STR_SRC< 1.8V
typ. This implementation guarantees a negligible output current down to 0V on STR_SRC
pin (where internal compensation is no more effective) and at the same time the correct re-
enabling of the driver when the output voltage goes negative, in order to guarantee the
correct clamping functionality during recirculation. In any other condition (Low-side
configuration, or Diagoff enabled, or channel ON) the effect of this comparator is masked
and an output current will be observed.

Figure 40. Configurable high/low -side Driver block schematic

VBAT
LS_CONF HS_CONF
OFF state - LS
OL & STG detection
LOAD
ON state
OC & OT protection
STRx_DRN

WD reset

Command
Driver
Chip en

STRx_SRC
OFF state - HS
OL & STG detection
LOAD
STR DRIVER LS_CONF
HS_CONF
GND GADG0212161507PS

The driver has the following detection diagnosis in low-side mode:

 Overcurrent (Short to Vbat) protection in On Phase (OVC);
 Open Load in Off phase (DIAGOL);
 Short to Ground in Off Phase (DIAGLV);
 Over Temperature Protection in On phase (OT);
 The driver has the following detection diagnosis in high-side mode:
Overcurrent (Short To GND) protection in On Phase (OVC);
 Open Load in Off phase (DIAGOL);
 Short to battery in Off Phase (DIAGHV);
 Over Temperature Protection in On phase (OT);

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263
High/low-side drivers - STARTER STR[1:3] L9788

In low-side configuration, if they are configured as starter CONFIG_REG3[4]=STR2_EN=1

and CONFIG_REG3[5]=STR3_EN=1, the driver STR2 and STR3 can work down to VB_IN
= 3.1 V. for THOLD.
In high-side configuration, if they are configured as starter CONFIG_REG3[4]=STR2_EN=1
and CONFIG_REG3[5]=STR3_EN=1, the driver STR2 and STR3 can work down to VB_IN
= 3.1 V for THOLD.
Furthermore, the driver can latch its ON state for THOLD even if the main microcontroller is
temporarily not working due to low-battery conditions.
HS/LS are intended to be used as starter relay driver. One for high-side, one for low-side.
STR2/3 should keep the status till VOFF_VB_IN.(3.1 V).
Each starter driver is separately put in on or off state by the MSC CONFIG-REG 14[5:7] just
for the time required to perform on or off diagnosis (Fast Diagnosis). At the end of the
diagnosis it is automatically put in the state determined by the current value of MSC data
frame.
The micro command is activated by writing 1 from 0 in the MSC registers (both for ON and
OFF).

8.1 ON state diagnosis

The ON state diagnosis has the same features as the low-side driver ON state diagnosis
described in chapter Section 7.1.1 and Section 7.1.2.

8.2 ON/OFF state - Error in on status diagnosis

Refer to paragraph Section 7.1.3.

8.3 OFF state diagnosis LS mode

The OFF state diagnosis in LS mode has the same features as the low-side driver OFF
state diagnosis described in paragraph Section 7.1.4.

8.4 OFF state diagnosis HS mode

The device provides off-state diagnostic for HS mode, simplified schematic of implemented
diagnostic is shown in Figure 41.

108/264 DS12308 Rev 4

L9788 High/low-side drivers - STARTER STR[1:3]

Figure 41. OFF state diagnostic HS config block schematic

VBAT

MSC Command
Driver

+ VTVB
DIAGHV

-
I_LS_PU
VOUTOPEN +
OUTx LOAD
gm
-
+ VTOPEN
I_LS_PD

DIAGOL
L/R
-

HLS DRIVER in HS configuration

PGND
GADG0212161526PS

In the HS mode we can have three different load conditions:

 Normal Load, it means output driver connected to the load, No Fault Present, VOUT≤
V_OL Threshold;
 Open Load, It means output driver disconnected to the load, Open Load Fault Present,
VHVT ≥ VOUT ≥ V_OL Threshold;
 Short To VB, it means output driver shorted to VB voltage, Short To VB Fault Present,
VOUT > VHVT.
There is a bit IPUPD_EN_STRx in CONFIG_REG13 which is controlled by a MSC bit, it is
used by external µController if it is needed to switch on/off both pull up and pull down
diagnosis current.
There is a bit IPUPD_MODE in CONFIG_REG2 which is controlled by a MSC bit, it is used
by external uController if it is needed to switch on/off the bigger diagnosis
current(I_HS_PD1) in fast mode.
The Diagnostic in Off state is done by the following block:
 An internal Buffer using the pull up/down currents is able to force the VOUTOPEN
voltage on the High-Side Driver Output when the driver is in Open Load Condition.
 A comparator to detect the Open load Condition. The Open Load fault is detected when
the OUTx pin is VHVT >= VOUT>= V_OL Threshold for a time longer than Diag Filter
Time.
 A comparator to detect the Short to VB Condition. The Short To VB fault is detected
when the OUTx pin is VOUT >= VHVT Threshold for a time longer than Diag Filter
Time.
 Fast pull down current, this current is used to avoid the false short to VB diagnosis
when the driver switches off in Open load condition. This current switches on after the
falling edge of MSC command (driver in off state) and remains on until the Diag Filter
Time is expired or until the VOUT is < VHVT Threshold. (Note: if fast pull down current
is selected, the filter time Tflt_diagoff1 is suggested. Otherwise, the filter time
Tflt_diagoff2 is suggested).

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High/low-side drivers - STARTER STR[1:3] L9788

Figure 42. OFF state diagnostic HS config

V_OUTx
(high-side)

Short to VB

3V
VHVTmin
VOUTOPEN max

VOUTOPEN Open Load

VOUTOPENmin

V-OL_TH max
1.9V

Normal function

GADG0512160753PS

Figure 43. High-side driver OFF state fast pull down current behavior
I_diag I_diag

I_HS_PD1+I_HS_PD2 I_HS_PD1+I_HS_PD2

I_HS_PD2 I_HS_PD2

Tflt_diagoff1 t Tflt_diagoff1 t
Voutx Voutx

VHVT VHVT

Tflt_diagoff1 t Tflt_diagoff1 t
GADG0512160803PS

By default diagnostic pull up/down currents are disabled and comparator outputs are
masked by internal logic, to enable OFF state diagnostic the channel must be put first in
tristate condition and then (if not already done with previous MSC frames) diagnostic must
be enabled. Once the desired channel is put in tristate a false diagnostic can be sensed due
to the time needed to discharge output voltage through the load.
A Filter Time (Diag Filter Time) is implemented in order to avoid detecting false diagnosis as
shown in Figure 44.

110/264 DS12308 Rev 4

L9788 High/low-side drivers - STARTER STR[1:3]

Figure 44. OFF state diagnostic high-side, timing

HIGH SIDE OUTPUT VOLTAGE HIGH SIDE OUTPUT VOLTAGE

COMMAND OFF COMMAND OFF

VOUT VOUT

SHORT-TO-BATTERY LOAD

VHVT VHVT

OPEN LOAD

V_OL_TH_H V_OL_TH_H
highside highside

DIAG NO FAULT NO FAULT OFF FAULT DIAG NO FAULT OFF FAULT

OPEN LOAD SHORT-TO-BATTERY LOAD

< Tflt_diagoff Tflt_diagoff t Tflt_diagoff t

HIGH SIDE OUTPUT VOLTAGE HIGH SIDE OUTPUT VOLTAGE

COMMAND OFF
COMMAND OFF

VOUT
VOUT

VHVT VHVT SHORT-TO-BATTERY LOAD

V_OL_TH_H V_OL_TH_H
highside highside
NORMAL LOAD FASTCHARGE

DIAG FAULT FAULT OFF FAULT

DIAG NO FAULT NO FAUT SHORT-TO-BATTERY LOAD

t < Tflt_diagoff Tflt_diagoff t

< Tflt_diagoff
GADG0512160807PS

If DiagOL or DiagHV signal remains high for a time higher than Diag Filter Time the fault bit
is set and can be read by Read Diag Communication.
This bit can be reset by every Read Diag Communication.
Conditions:
5.5 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified;

Table 50. High/low-side driver - STARTER electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

Body diode
Irev_OUTx reverse current ILOAD = -0.6 A - - 1 V STR1/2/3
voltage drop

Relay HS configuration

HS configuration
Drain-source
RdsON VB_IN = 13.5 V; - - 1.5 Ω STR1/2/3
resistance
Tj =150 °C, I_load = 1A
HS configuration
Drain-source
RdsON VB_IN = 13.5 V; - - 0.81 Ω STR1/2/3
resistance
Tj = 25 °C, I_load = 1 A
HS configuration
Drain-source
RdsON VB_IN = 13.5 V; - - 0.63 Ω STR1/2/3
resistance
Tj =40 °C, I_load = 1 A

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263
High/low-side drivers - STARTER STR[1:3] L9788

Table 50. High/low-side driver - STARTER electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

HS configuration 
Drain-source
RdsON VB_IN = 3.1 V - - 3 Ω STR1/2/3
resistance
I_load = 1 A
Driver disabled,
Output leakage
STR_SRC_lkg diagnostic off; HSide -10 - +10 µA STR1/2/3
current
configuration
HS
From 30% to 80% of
configuration
SR_ON VOUT VB_IN = 14 V, 0.7 - 2.1 V/µs STR1/2/3
Voltage slew ON
Rload = 68 Ω
State
HS
From 80% to 30% of
configuration
SR_OFF VOUT VB_IN = 14 V, 0.7 - 2.1 V/µs STR1/2/3
Voltage slew
Rload = 68 Ω
OFF State
FAST VS/R off
when an OVC From 80% to 30% of
S/RGkill_HS fault happens VOUT VB_IN = 14 V, 5 - 20 V/µs STR1/2/3
high-side Rload = 68 Ω
configuration
Propagation
Delay from
MSC_EN rising VB_IN = 14 V,
Ton_OUTx_Hside - - 10 µs STR1/2/3
edge to 20% Rload = 68 Ω
output OUTx
voltage
Propagation
Delay from
MSC_EN falling VB_IN = 14 V,
Toff_OUTx_Hside - - 10 µs STR1/2/3
edge to 80% Rload = 68 Ω
output OUTx
voltage
OUTx clamping
Vclamp_OUTx_HS voltage HS ILOAD = 0.6 A -4.1 - -2.5 V STR1/2/3
configuration
Over current
driver threshold
- - 1 1.5 2 A STR1/2/3
HS
configuration
HS overcurrent
I_HS_ocv_flt Guaranteed by scan 4 - 7 µs STR1/2/3
filter time

Relay LS configuration

LS configuration 
Drain-source
RdsON VB_IN = 13.5 V  - - 1.5 Ω STR1/2/3
resistance
Tj = 150 °C I_load = 1A

112/264 DS12308 Rev 4

L9788 High/low-side drivers - STARTER STR[1:3]

Table 50. High/low-side driver - STARTER electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

LS configuration 
Drain-source
RdsON VB_IN = 13.5 V, - - 0.81 Ω STR1/2/3
resistance
Tj = 25 °C, I_load = 1 A
LS configuration 
Drain-source
RdsON VB_IN = 13.5 V - - 0.63 Ω STR1/2/3
resistance
Tj = -40 I_load = 1 A
LS configuration 
Drain-source
RdsON VB_IN = 3.1 V - - 3 Ω STR1/2/3
resistance
I_load = 1 A
Output disabled,
diagnostic off ;
Output leakage Low-Side configuration,
STR_DRN_lkg -10 - +18 µA STR1/2/3
current DRN1=DRN2=DRN3=1
8 V, total current from 3
pins, T=-40 °C, 27 °C
Output disabled,
diagnostic off ;
Output leakage Low-Side configuration,
STR_DRN_lkg -10 - +48 µA STR1/2/3
current DRN1=DRN2=DRN3=1
8 V, total current from 3
pins, T = 175 °C
LS configuration From 80% to 30% of
SR_ON voltage slew ON VOUT VB_IN = 14 V, 0.8 - 2.5 V/µs STR1/2/3
State Rload = 68 Ω
LS configuration From 30% to 80% of
SR_OFF voltage slew VOUT VB_IN = 14 V, 0.8 - 2.5 V/µs STR1/2/3
OFF State Rload = 68 Ω,
FAST VS/R off
when an OVC From 30% to 80% of
S/RGkill_LS fault happens in VOUT VB_IN = 14 V, 5 - 20 V/µs STR1/2/3
low-side Rload = 68 Ω,
configuration
Propagation
Delay from
MSC_EN rising VB_IN =14 V,
Ton_OUTx_Lside - - 10 µs STR1/2/3
edge to 80% Rload = 68 Ω,
output OUTx
voltage
Propagation
Delay from
MSC_EN falling VB_IN=14V,
Toff_OUTx_Lside - - 10 µs STR1/2/3
edge to 20% Rload = 68 Ω,
output OUTx
voltage
OUTx clamping
Vclamp_OUTx_LS voltage LS ILOAD = 0.6 A 40 - 50 V STR1/2/3
configuration

DS12308 Rev 4 113/264

263
High/low-side drivers - STARTER STR[1:3] L9788

Table 50. High/low-side driver - STARTER electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

ILOAD = 1 A
Guaranteed by design,
OUTx clamping
Vclamp_OUTx_LS_hig provided single pulse
voltage LS 40 - 50 V STR1/2/3
h_curr energy limits are not
configuration
violated by clamping
action
Over current
driver threshold - 1 1.5 2 A STR1/2/3
LS configuration
LS overcurrent
I_LS_ocv_flt Guaranteed by scan 4 - 7 µs STR1/2/3
filter time

Driver reliability data as Low-Side

Tcase = 25 °C ;
Energy
EnergyRep I_OT_n = 0.45 A - - 9 mJ STR1/2/3
repetitive pulses
1.1 Miopulses
Tc = 115 °C ;
Energy
EnergyRep I_OT_n = 0.3 A - - 6.5 mJ STR1/2/3
repetitive pulses
40 Miopulses
Tc =130 °C ;
Energy
EnergyRep I_OT_n = 0.3 A - - 6.5 mJ STR1/2/3
repetitive pulses
9 Miopulses
Tc = 140 °C ;
Energy
EnergyRep I_OT_n = 0.3 A - - 6.5 mJ STR1/2/3
repetitive pulses
1 Miopulses

Driver reliability data as High-Side

Tcase = 25 °C ;
Energy
EnergyRep I_OUT_n = 0.45 A - - 12.5 mJ STR1/2/3
repetitive pulses
1.1 Miopulses
Tc = 115 °C ;
Energy
EnergyRep I_OT_n = 0.3 A - - 9 mJ STR1/2/3
repetitive pulses
40 Miopulses
Tc = 130 °C ;
Energy
EnergyRep I_OT_n = 0.3 A - - 9 mJ STR1/2/3
repetitive pulses
9 Miopulses
Tc = 140 °C ;
Energy
EnergyRep I_OT_n = 0.3 A - - 9 mJ STR1/2/3
repetitive pulses
1 Miopulses

Driver reliability data generator defect as Low-Side

Tc = 25 °C ;
Energy
EnergyRep STR I_OT_n = 0.5 A - - 11 mJ STR1/2/3
repetitive pulses
0.02 Miopulses
Tc = 135 °C ;
Energy
EnergyRep STR I_OT_n = 0.35 A - - 8 mJ STR1/2/3
repetitive pulses
0.02 Miopulses

114/264 DS12308 Rev 4

L9788 High/low-side drivers - STARTER STR[1:3]

Table 50. High/low-side driver - STARTER electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Driver reliability data generator defect as High-Side

Tc = 25 °C ;
Energy
EnergyRep STR I_OT_n = 0.5 A - - 15 mJ STR1/2/3
repetitive pulses
0.02 Miopulses
Tc = 135 °C ;
Energy
EnergyRep STR I_OT_n = 0.35 A - - 11 mJ STR1/2/3
repetitive pulses
0.02 Miopulses

Driver reliability data JUMP START as Low-Side

Tc = 25 °C ;
I_OT_n = 0.75A
Energy 0.001 Miopulses,
EnergyRep STR - - 25 mJ STR1/2/3
repetitive pulses 10 jumps starts over
lifetime, each start < 2
min
Tc = 75 °C ;
I_OT_n = 0.5 A
Energy 0.001 Miopulses,
EnergyRep STR - - 17 mJ STR1/2/3
repetitive pulses 10 jumps starts over
lifetime, each start < 2
min

Driver reliability data JUMP START as High-Side

Tc = 25 °C ;
I_OT_n = 0.75 A
Energy 0.001 Miopulses,
EnergyRep STR - - 31 mJ STR1/2/3
repetitive pulses 10 jumps starts over
lifetime, each start < 2
min
Tc = 75 °C;
I_OT_n = 0.5 A
Energy 0.001 Miopulses,
EnergyRep STR - - 21 mJ STR1/2/3
repetitive pulses 10 jumps starts over
lifetime, each start < 2
min

OFF state diagnostic – HS configuration

Short to VB VOUT
VHVT threshold HS configuration OPEN - 3.0 V STR1/2/3
voltage +160mV
Open load VOUT
V_OL_TH_Highside threshold HS configuration 1.9 - OPEN V STR1/2/3
voltage -180mV
Open load
VOUTOPEN_Highside threshold HS configuration 2.3 2.5 2.7 V STR1/2/3
voltage

DS12308 Rev 4 115/264

263
High/low-side drivers - STARTER STR[1:3] L9788

Table 50. High/low-side driver - STARTER electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

In OFF condition, OUTx

STRx_SRC >VHVT,
I_HS_PD1 Ipupd_EN 2.5 3.6 4.7 mA STR1/2/3
Diagnostic pull IPUPD_EN_STRx =ENB,
down current in Ipupd_MODE =”1”
high-side In OFF condition, OUTx
configuration STRx_SRC >VHVT,
I_HS_PD2 Ipupd_EN 40 70 100 µA STR1/2/3
IPUPD_EN_STRx =ENB,
Ipupd_MODE =”0”
In OFF condition, 
OUTx STRx_SRC
<VOUTOPEN,
I_HS_PU1 35 - 75 µA STR1/2/3
Ipupd_EN
Diagnostic pull IPUPD_EN_STRx =ENB
up current in STR_SRCx = 1.9 V
high-side In OFF condition, 
configuration OUTx STRx_SRC
<VOUTOPEN,
I_HS_PU2 100 - 180 µA STR1/2/3
Ipupd_EN
IPUPD_EN_STRx =ENB
STR_SRCx = 0 V
OFF condition, Diagoff
I_HS_OUT_Dis1 Output current disabled,  -15 - +15 µA STR1/2/3
in high-side STR_SRC > or = 0 V
configuration
(measured on OFF condition, Diagoff
I_HS_OUT_Dis2 STR_SRC) disabled,  -190 - +10 µA STR1/2/3
STR_SRC < 0 V
Output voltage OFF condition, Diagoff
of STR_SRC disabled
V_negative_threshold below which the - - -0.2 V STR1/2/3
output current is
measured again Guaranteed by design
Positive
threshold of
internal
comparator
responsible of
remove output OFF condition, Diagoff
current on disabled
V_positive_threshold STR_SRC pin - 1.8 - V STR1/2/3
(over this
voltage Guaranteed by design
negligible
current is
guaranteed by
compensation
circuit)

116/264 DS12308 Rev 4

L9788 High/low-side drivers - STARTER STR[1:3]

Table 50. High/low-side driver - STARTER electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Guaranteed by scan
Tflt_diagoff2 - 1000 1200 1500 us STR1/2/3
Cload = 15 nF
Guaranteed by scan
Tflt_diagoff1 - 130 160 200 us STR1/2/3
Cload = 15 nF

OFF state diagnostic – LS configuration

Short to GND VOUT

VLVT threshold LS configuration 1.9 - OPEN V STR1/2/3
voltage -180mV
Open load VOUT
V_OL_TH_Lowside threshold LS configuration OPEN - 3.0 V STR1/2/3
voltage +160mV
Open load
VOUTOPEN_Lowside LS configuration 2.3 2.5 2.7 V STR1/2/3
voltage
In OFF condition,
STRx_DRN < VLVT,
I_LS_PU1 2.5 3.6 4.7 mA STR1/2/3
IPUPD_EN_STRx =ENB,
Diagnostic pull Ipupd_MODE =”1”
up current in Ls
configuration In OFF condition,
STRx_DRN < VLVT,
I_LS_PU2 40 70 100 µA STR1/2/3
IPUPD_EN_STRx =ENB,
Ipupd_MODE =”0”
In OFF condition,
Diagnostic pull
STRx_DRN > VOUTO
I_LS_PD1 down current in 55 85 100 µA STR1/2/3
PEN,
Ls configuration
IPUPD_EN_STRx =ENB
DIAG Filter time
in Ls Guaranteed by scan
Tflt_diagoff2 450 600 750 µs STR1/2/3
configuration Cload = 15 nF
Filter Mode = 1
DIAG Filter time
in Ls
configuration
Guaranteed by scan
Tflt_diagoff1 fast discharge 75 100 125 µs STR1/2/3
Cload = 15 nF
enable Filter
Mode = 0 (fast
diag off)

Common diagnostic – LS/HS configuration

Temperature
T_SD_HIGH - 185 - 200 °C STR1/2/3
shut down
Temperature
T_SD_LOW shut down - 175 - 190 °C STR1/2/3
recover
Temperature
T_SD_hys shut down - 5 - 10 °C STR1/2/3
hysteresis

DS12308 Rev 4 117/264

263
High/low-side drivers - STARTER STR[1:3] L9788

Table 50. High/low-side driver - STARTER electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Thermal
- shutdown Guaranteed by design 1.5 - 4 µs STR1/2/3
analog filter time
Digital deglitch
filter time on
t_SD_deglitch Temperature Guaranteed by scan - 10 - µs STR1/2/3
shut down
detection
Fast OFF
- diagnostic Filter Mode=0 220 245 270 µs STR1/2/3
ON->OFF->ON
Fast ON
- diagnostic - 65 - 90 µs STR1/2/3
OFF->ON->OFF

8.5 Delay-off function

The Delay-off function involves the RLY4 and STR[2:3] drivers when they are configured as
starters by the bit MSC_CONFIG_REG3[0]=RLY4_DELAY_OFF_EN=1,
CONFIG_REG3[4]=STR2_EN=1, CONFIG_REG3[5]=STR3_EN=1. These drivers follow
the reset matrix as other drivers when they are not configured as starters.
If the drivers are configured as starter and it is in on state its delay-off timer starts when one
of the following events occurs:
 under-voltage of the main supply VDD5 is detected,
 over-voltage of the main supply VDD5 is detected,
 the MSC time out occurs,
 an active signal ("0") at pin WDA(IN),
 an active signal ("0") at pin RSTN(IN)
During the delay off time THOLD
 The driver is ON regardless of whether the ON/OFF command is reset.
 The starter configuration is held.
 The HSD/LSD configuration bit is held.
 The driver is ON even in case of Watchdog ERR_CNT>4 and ERR_CNT>7
 The driver is ON even in case of VDDIO_UV.
 Once it has started, the delay_off is not restarted by a new triggering event before
THOLD has expired.
The delay-off timer can be terminated by one of the following events:
 THOLD time expires.
 Driver is switched off by MSC command off.
After DELAY_OFF time the RLY4, STR[2:3] take the status of the on/off data command. If
before the delay off time expires, the above triggering sources are recovered, the delay-off
function remains valid.

118/264 DS12308 Rev 4

L9788 High/low-side drivers - STARTER STR[1:3]

Figure 45. DELAY_OFF timing

Start of delayed Delayed off timer
off mode overflow

MSC MSC
Drivers ON Drivers OFF

Delay off trigger status no trigger event Eg. VDD5_UV no trigger event

Delay off timer reset Count up reset

Delay off output ON ON OFF ON OFF

Remaining power stages ON OFF OFF ON OFF

GADG0512161117PS

Figure 46. DELAY_OFF timing terminated by MSC off command

Start of delayed
off mode

MSC MSC MSC MSC MSC

Drivers OFF Drivers ON Drivers OFF Drivers ON Drivers OFF

Delay off trigger status no trigger event Eg. VDD5_UV no trigger event

Delay off timer reset Count up reset

Delay off output ON ON OFF ON OFF ON OFF

Remaining power stages ON OFF OFF ON OFF ON OFF

< THOLD
GADG0512161118PS

Conditions:
5.5 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified;

Table 51. High/low-side driver delay-off function electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

THOLD Delay off time - 400 - 800 ms RLY4 STR2/3

DS12308 Rev 4 119/264

263
High/low-side drivers - STARTER STR[1:3] L9788

8.6 Starter control

To prevent unintended activation of starter relays at the same time a dual control
mechanism is implemented inside the logic by means of independent MSC commands for
on/off for each starter (RLY4_ON RLY4_OFF STR2_ON STR2_OFF STR3_ON
STR3_OFF). If the RLY4, STR2, STR3 are not configured as starter they are controlled by
data frame on/off as the other drivers
The starter control function comes with a dedicated failsafe management circuit to always
provide a safety switch off path able to disconnect the main supply in case of fault
conditions. Starter switch off path is implemented with dual polarity command acting on
drivers STR[2:3] and RLY4: if the EN_P pin is high or the EN_N pin is high or if the
FAULT_WARN is activated. RLY4, STR2, STR3 are switched off by the safety switched off
path independently if they are configured as starter.
Safety switch off path can be triggered both by the micro-controller through EN pins or by
the L9788 detection of an internal fault as described in the Figure 47.
The functionality of the switch off path is guaranteed through physical isolation from the rest
of the device: the circuit is kept layouted in a dedicated area surrounded by trench
isolations, avoiding top routing over this cell and keeping a safe distance respect to the
nearby functional top routing to ensure complete independency.
The switch off path generates locally its supply voltage to drive the safety turn-off switch in
order to avoid interactions with the rest of the L9788; the supply voltage is created starting
directly from battery line. All the circuits used inside the switch-off path are able to sustain
high voltage to prevent unwanted functionality in case of local failure, moreover no external
reference is routed to this area and the EN_N and EN_P control logic is located inside this
area as well to complete isolation and remove any dependency from the rest of the L9788.

120/264 DS12308 Rev 4

L9788 High/low-side drivers - STARTER STR[1:3]

Figure 47. Safety switch off

Isolated ECM Remote Location

Disable
L9788
WDA
Watchdog Function Switched
Battery
WDA
EN_RLY4
Configuration & Control

RLY4

SW_BAT

EN_STR2

STR2 Battery

EN_STR3

STR3

Throttle Starter
EN Control
H-Bridge
Driver IC

oscillator fault Status

Power Management

v3v3pre_mon_ov
v3v3pre_mon_uv
EN_N
& Control

v3v3pre_ov
v3v3pre_uv
v3v3ana_ov EN_P
v3v3ana_uv
v3v3dig_ov
v3v3dig_uv
gnd_dig_loss Isolated Circuitry

GADG0512161145PS

Conditions:
5.5 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified;

Table 52. EN_P and EN_N electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

VIH_TX HIGH_level input voltage - 1.75 - - V EN_P

VIL_TX LOW_level input voltage - - - 0.75 V EN_P
VHYS_TX Input voltage hysteresis - 0.06 0.5 - V EN_P
PULL_TX Pull-up resistance - 50 100 200 kΩ EN_P
VIH_TX HIGH_level input voltage - 1.75 - - V EN_N
VIL_TX LOW_level input voltage - - - 0.75 V EN_N
VHYS_TX Input voltage hysteresis - 0.06 0.5 - V EN_N
PULL_TX Pull-up resistance - 50 100 200 kΩ EN_N

Note: For this application the function is implemented, but kept disabled using external resistor to
pull EN_N and EN_P to low.

DS12308 Rev 4 121/264

263
Pre-drivers - ExtFET (MOS_Gate1/2/3/4/5) - PRD[1:5] L9788

9 Pre-drivers - ExtFET (MOS_Gate1/2/3/4/5) - PRD[1:5]

Figure 48. LS External MOSFET Pre-Driver Stage

VBAT

OFF state VB_IN

Drain short to Gnd, OL
Load
ON state
Drain short to battery
MOS_Drain

I_SOURCE
MOS_Gate

MSC Command
Driver

I_SINK MOS_Source

LS ExtNMOS Pre-Driver GND1

GADG0512161207PS

9.1 LS external MOSFET pre-driver

These 5 pre-drivers are designed to drive LS external MOSFET Load. They are driven by
MSC command.
The push-pull stage is made up of limited source current and sink current. The voltage of
MOS_Drain is monitored for diagnosis.
The driver has the following detection diagnosis:
 _Drain short to battery @ pre-driver = On state
 _Drain short to ground @ pre-driver = Off state
 _Drain open load @ pre-driver = Off state
Predriver1 & Predriver3 can be used to drive ExtMos for O2H Load.
For these two predrivers there is the possibility to select a lower gate current and sink
current (typ = 250 µA).
A dedicated MSC bit is used to select the predriver O2H function (Bit O2H_PDRV =
CONFIG_REG_16_1[7:6]). Considering that this sink/source current is very low the logic will
switch to the selected higher sink/source current after the cmd delay time (typ 150 µs for
CONFIG_REG20[7]=PDRV_O2H_DLY=0 or 300 µs
CONFIG_REG20[7]=PDRV_O2H_DLY=1). After the CMD delay time the current used is the
one selected by CONFIG_REG4=PRDx_IDRV[1:0].
When the Predriver is used for O2H load the overcurrent detection can't be done using a
VDS comparator due to slow voltage slew-rate, for this reason an external Rshunt has to be
used.

122/264 DS12308 Rev 4

L9788 Pre-drivers - ExtFET (MOS_Gate1/2/3/4/5) - PRD[1:5]

When the Predriver is used for O2H load no blanking time is applied to OVC detection.The
OVC dectection is done reading the voltage drop on this external Rshunt by the VDS
comparator of another predriver (not used).
This means that when the Predriver 1 and Predriver 3 are used for O2H load the Predriver 2
and Predriver 4 can't be used.
Bit O2H_PDRV = CONFIG_REG_16_1[7:6]= 00: all 5 predriver channels can be used
Bit O2H_PDRV = CONFIG_REG_16_1[7:6]= 11:
 predriver 2 & Predriver 4 can't be used;
 predriver 1 & predriver3 work with low gate current and sink current (typ = 250 µA);
 it is possible to read the Overcurrent on external Rshunt of Predriver1&3 using the Vds
comparator of Drain2 and Drain4;
 Predriver 5 works as in O2H_PDRV = CONFIG_REG_16_1[7:6]= 00.
There is a dedicated ground pin PDR_GND used for source pin of External Mos or ground
connection of External shunt resistor. The internal voltage reference for VDS comparator
threshold (Vth_VDS_xxx parameter) is connected to this ground pin PDR_GND. Application
has to connect this PDR_GND pin to the source of external MOS or ground of external
shunt resistor in order to obtain a good accuracy of overcurrent threshold.
Pre-driver after power up is OFF, output LOW.

Figure 49. PreDriver3 configured for O2H load bit O2H_PDRV_3 =

CONFIG_REG_16_1[7] = 1:

OFF Diag3

VDS3comp D3

NOT USED G3

VDS4comp

D4
Rshunt

GADG0512161223PS

Figure 50. PreDriver1 configured for O2H load bit O2H_PDRV_1 =

CONFIG_REG_16_1[6] = 1:
OFF Diag1

VDS1comp D1

NOT USED G1

VDS2comp

D2
Rshunt

GADG0512161253PS

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263
Pre-drivers - ExtFET (MOS_Gate1/2/3/4/5) - PRD[1:5] L9788

9.2 ON state diagnostic

In the On state of pre-driver, the diagnosis will compare the Drain-source voltage with the
threshold generated internal. If MOS_DRAIN_X>Vth_DS_XXX (PRDx_VDS[0:2]
CONFIG_REG5/ CONFIG_REG6 / CONFIG_REG7)for a filter time, the Drain short to
battery fault will be confirmed. The internal comparator reads the voltage on drain pin versus
a dedicated GND sense pin (PIN X) that at application should be connected on the source of
external mos. Starting from the condition ON state a programmable blanking time (MSC
CONFIG_REG16=PRDx_BLK[1:0]) is applied to prevent the detection of the short-to-
battery fault. The blanking time is not applied when the driver is already ON.The pre-driver
will switch OFF and the fault will be latched until the Read_Diag_CMD action. This bit can
be reset by every Read Diag Communication. To re-activate ON the power stage in this two
following conditions:
 The MSC command still High, when the Fault OVC Bit is read by MSC communication.
 The MSC command becomes Low and then again High.
When Bit MSC_O2HPredr_1 = 1 the VDS comparator of predriver 1 is ignored.
When Bit MSC_O2HPredr_3 = 1 the VDS comparator of predriver 3 is ignored.
When Bit MSC_O2HPredr = 1 the VDS comparator of predriver 2 (or 4) is enabled
immediately with the turn ON command of Predriver (and checked by logic after the
blanking time), while when Bit MSC_O2HPredr = 0 the VDS comparator of corresponding
channel is enabled after selected blanking time.
The over current protection can be done reading the voltage on external Rshunt using the
VDS comparator of predriver 2&4.

9.3 ON/OFF state - Error in status diagnosis

Refer to Section 7.1.3.

9.4 Error handling

Table 53. Pre-driver - ExtFET error handling
Detection Clear
Type of error Action Restart condition
condition MSC flag

Driver diagnostic

At MSC read of diagnosis

Driver is put in off state. register if MSC command
Overcurrent (OVC) Driver on The fault is latched in On read is still high. If MSC
MSC diagnosis register. command is low and high
again.
The fault is latched in
Short to ground (STG) Driver off On read
MSC diagnosis register.

124/264 DS12308 Rev 4

L9788 Pre-drivers - ExtFET (MOS_Gate1/2/3/4/5) - PRD[1:5]

Table 53. Pre-driver - ExtFET error handling (continued)

Detection Clear
Type of error Action Restart condition
condition MSC flag

The fault is latched in

Open load (OPL) Driver off On read
MSC diagnosis register.
Driver on/off When
the driver output The fault is latched in
Driver Status Error (STA) On read
level is not aligned MSC diagnosis register.
with the cmd on/off

9.5 OFF state diagnostic

The Predriver follows the same off diagnosis as low-side driver. But despite the fast mode of
all drivers in off diagnostic condition (Ipupd_MODE bit), for all pre_Driver, there is a
dedicated MSC bit (IDIAG_HIGH_PDRV) to select off diagnostic high or low pull up/down
current
Conditions:
5.5 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified;

Table 54. Pre-driver - ExtFET electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

Pre-driver

On state MOS_ MOS_Gate

Vgate_on I_source_00 5 - 6 V
Gate voltage 1/2/3/4/5
Off state
MOS_Gate
Vgate_off MOS_Gate I_sink_00 0 - 0.1 V
1/2/3/4/5
voltage
Leakage current
MOS_Gate
Ileak_off of MOS_Gate @ - -1 - 1 µA
1/2/3/4/5
driver in tri-state
Pre-driver source MOS_Gate1/2/3/4/5 short to MOS_Gate
I_source_00 14 20 26 mA
current 1 gnd 1/2/3/4/5
Pre-driver source MOS_Gate1/2/3/4/5 short to MOS_Gate
I_source_01 7 10 13 mA
current 2 gnd 1/2/3/4/5
Pre-driver source MOS_Gate1/2/3/4/5 short to MOS_Gate
I_source_10 2.8 4 5.2 mA
current 3 gnd 1/2/3/4/5
Pre-driver source MOS_Gate1/2/3/4/5 short to MOS_Gate
I_source_11 1.3 2 2.6 mA
current 4 gnd 1/2/3/4/5
I_source_O2 Pre-driver source MOS_Gate
MOS_Gate1/3/ short to gnd 0.175 0.25 0.325 mA
H current 5 1/3
Pre-driver sink MOS_Gate1/2/3/4/5 short to MOS_Gate
I_sink_00 -26 -20 -14 mA
current 1 5V 1/2/3/4/5
Pre-driver sink MOS_Gate1/2/3/4/5 short to MOS_Gate
I_sink_01 -13 -10 -7 mA
current 2 5V 1/2/3/4/5

DS12308 Rev 4 125/264

263
Pre-drivers - ExtFET (MOS_Gate1/2/3/4/5) - PRD[1:5] L9788

Table 54. Pre-driver - ExtFET electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Pre-driver sink MOS_Gate1/2/3/4/5 short to MOS_Gate

I_sink_10 -5.2 -4 -2.8 mA
current 3 5V 1/2/3/4/5
Pre-driver sink MOS_Gate1/2/3/4/5 short to MOS_Gate
I_sink_11 -2.6 -2 -1.4 mA
current 4 5V 1/2/3/4/5
Pre-driver sink MOS_Gate
I_sink_O2H MOS_Gate1/3 short to 5V -0.175 -0.25 -0.325 mA
current 5 1/3

ON/OFF state diagnostic

Diagnosis Vds MOS_Drai

Vth_DS_000 - 120 150 180 mV
threshold 1 n1/2/3/4/5
Diagnosis Vds MOS_Drai
Vth_DS_001 - 220 245 270 mV
threshold 2 n1/2/3/4/5
Diagnosis Vds MOS_Drai
Vth_DS_010 - 300 325 350 mV
threshold 3 n1/2/3/4/5
Diagnosis Vds MOS_Drai
Vth_DS_011 - 380 405 430 mV
threshold 4 n1/2/3/4/5
Diagnosis Vds MOS_Drai
Vth_DS_100 - 500 525 550 mV
threshold 5 n1/2/3/4/5
Diagnosis Vds MOS_Drai
Vth_DS_101 - 620 660 700 mV
threshold 6 n1/2/3/4/5
Diagnosis Vds MOS_Drai
Vth_DS_110 - 900 950 1000 mV
threshold 7 n1/2/3/4/5
Over current MOS_Drai
T_filter_ovc Tested by scan 5 - 7 µs
filtering time n1/2/3/4/5
VOUTO
Open load MOS_Drai
V_OL Driver tristate, diag enabled PEN+16 - 3 V
threshold voltage n1/2/3/4/5
0mV
Open load output MOS_Drai
VOUTOPEN Driver tristate, diag enabled 2.3 2.5 2.7 V
voltage n1/2/3/4/5
Output short- VOUTO
MOS_Drai
VLVT circuit to GND Driver tristate, diag enabled 1.9 - PEN- V
n1/2/3/4/5
Voltage threshold 180mV
In OFF condition,
Diagnostic pull MOS_DRAINx <VLVT, MOS_Drai
I_LS_PU1 2.5 3.6 4.7 mA
up current Ipupd_EN = ENB, n1/2/3/4/5
Ipupd_MODE =”1”
In OFF condition,
MOS_DRAINx < VLVT,
Diagnostic pull MOS_Drai
I_LS_PU2 Ipupd_EN = ENB, 40 70 100 µA
up current n1/2/3/4/5
Ipupd_MODE =”0”and
IDIAG_HIGH_PDRV =”0”

126/264 DS12308 Rev 4

L9788 Pre-drivers - ExtFET (MOS_Gate1/2/3/4/5) - PRD[1:5]

Table 54. Pre-driver - ExtFET electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

In OFF condition,
MOS_Drainx < VLVT,
Diagnostic pull MOS_Drai
I_LS_PU3 Ipupd_EN = ENB, 100 - 200 µA
up high current n1/2/3/4/5
Ipupd_MODE =”0” and
IDIAG_HIGH_PDRV =”1”
In OFF condition,
MOS_DRAINx
Diagnostic pull MOS_Drai
I_LS_PD1 > VOUTOPEN, 60 85 105 µA
down current n1/2/3/4/5
Ipupd_EN = ENB and
IDIAG_HIGH_PDRV =”0”
In OFF condition, 
Diagnostic pull OUT MOS_Drainx
MOS_Drai
I_LS_PD2 down high > VOUTOPEN, 350 - 550 µA
n1/2/3/4/5
current Ipupd_EN = ENB
IDIAG_HIGH_PDRV = ”1”
MOS_DRAIN Output disable diagnostic MOS_Drai
I_leakage -10 10 µA
leakage current OFF condition, n1/2/3/4/5
MOS_Drai
Tflt_diagoff1 DIAG Filter time Filter Mode=0 75 100 125 µs
n1/2/3/4/5
MOS_Drai
Tflt_diagoff2 DIAG Filter time Filter Mode=1 450 600 750 µs
n1/2/3/4/5
Blanking time on MOS_Drai
Tblank_00 PRD1_BLK[0:1]=00 5.1 6 6.7 µs
ON diag n1/2/3/4/5
Blanking time on MOS_Drai
Tblank_01 PRD1_BLK[0:1]=01 11.1 12 13.5 µs
ON diag n1/2/3/4/5
Blanking time on MOS_Drai
Tblank_10 PRD1_BLK[0:1]=10 17.1 18 20 µs
ON diag n1/2/3/4/5
Blanking time on MOS_Drai
Tblank_11 PRD1_BLK[0:1]=11 23.1 24 26.7 µs
ON diag n1/2/3/4/5
Command delay
for
MOS_Drai
cmd_dly_0 MSC_CONFIG_ Tested by scan 140 150 160 µs
n1/2/3/4/5
REG20[7]=PDR
V_O2H_DLY=1
Command delay
for
MOS_Drai
cmd_dly_1 MSC_CONFIG_ Tested by scan 280 300 320 µs
n1/2/3/4/5
REG20[7]=PDR
V_O2H_DLY=1

DS12308 Rev 4 127/264

263
Pre-drivers - IGNITER IGN[1:6] L9788

10 Pre-drivers - IGNITER IGN[1:6]

These 6 Ignition pre-drivers are designed to drive ignition load. They are driven by MSC
command. The push-pull stage is made up of a high-side current generator and a low-side
driver.
When an overcurrent fault is detected the driver switches off with higher slew rate (FAST
SR) to reduce the power dissipation.
There is a bit selection for disabling the LSD in case of external IGBT. It is suggested to
configure the MSC bit (IGN_LSD_DIS CONFIG_REG6 D7) disabling the LSD of igniter
before the msc_driver_enable command.

Figure 51. Ignition pre-drivers block schematic

5V VBAT

LOAD
HS current generator
MSC Command Driver

OFF state
STB detection
ON state
STB, STG, OL detection

IGNx

MSC LS_dis Command PGND

IGN Pre-Driver GND1

GADG0512161455PS

10.1 Ignition pre_drivers diagnosis

The driver has the following detection diagnosis:
 Short To Vbat protection by checking the IGNx pin voltage higher than Vth_STB_IGN,
when the driver is enabled high (high-side on) or low (low-side on);
 Open Load when the driver is enabled high (high-side on) (DIAGOL);
 Short to Ground when the driver is enabled high (high-side on) (DIAGLV).

128/264 DS12308 Rev 4

L9788 Pre-drivers - IGNITER IGN[1:6]

Table 55. Pre-driver - IGNITER diagnosis

Detected faults @ pre- Detected faults @ pre-
Controlled load Diagnosis & protection type
driver enabled HIGH driver enabled LOW

Internal IGBT/smart IGBT The controlled device is

(IGN_DIAG module internal. No diagnosis - -
(CONFIG_REG2 D5) = ‘0’) and protection required
_ IGNx short to GND
External IGBT Load IGNx voltage and current
_ IGNx open load _ IGNx short to VBAT
(IGN_DIAG = ‘1’) monitoring
_ IGNx short to VBAT

10.2 Short to GND

When IGNx pin voltage is lower than Vth_STG_IGN for a filter time at pre-driver is enabled
high, short to ground fault is detected. So the fault is latched until Read_Diag_CMD action.

Figure 52. IGN pre-drivers diagnosis timing diagram at short to GND

IGNx_CMD

Diag_fault
NO Fault SHORT-TO-GROUND fault NO Fault

V_Pin_IGNx SHORT-TO-GROUND fault happened

Vth_STG_IGN

t
Filter time for IGN

Driver status

Enabled HIGH Enabled LOW

t
Enabled LOW
IGNx_stg

Read_Diag_CMD

t
GADG0512161558PS

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Pre-drivers - IGNITER IGN[1:6] L9788

10.3 Short to BAT

When IGNx pin voltage is higher than Vth_STB_IGN for a filter time at pre-driver is enabled
high or enabled low, short to battery fault is detected and the driver is disabled. So the fault
is latched.
During Short-to-Bat fault present the driver is auto-restart with these modalities:
 The high-side restart during OVC is on read diagnostic or IGNx_CMD goes to low and
high again.
 The low-side restart during OVC is on read diagnostic.

Figure 53. IGN pre-drivers diagnosis timing diagram at short to VBAT

IGNx_CMD

Diag_fault
NO Fault Short to VBAT

V_Pin_IGNx
VB

Vth_stb_ign

Short to Battery fault happened

High impedence t
Filter time for IGN

Driver status

Enabled HIGH Disabled Enabled HIGH

t
Enabled LOW
IGNx_stb

Read_Diag_CMD

GADG0512161540PS

130/264 DS12308 Rev 4

L9788 Pre-drivers - IGNITER IGN[1:6]

10.4 Open load

When IGNx pre-driver is enabled HIGH, if IGNx current is lower than OL current detection
Ith_OL_IGN for a filter time, open load fault is detected and the driver is not disabled. Open
load function can be disabled by a MSC bit. Open Load fault is latched until
Read_Diag_cmd action. OPL threshold is selectable between 2 values, the default
(between 0.4 and 0.8mA) and a lower one.
OPL threshold reduction is available just in low current limitation condition, so when
OL_RED and IGN_CURRENT_CFG (CONFIG_REG2 D4) bits are both high.

10.5 Error in driver status

Refer to Section 7.1.3.

Figure 54. Low-side drivers ON diagnosis timing diagram at open load

IGNx_CMD

Diag_fault
NO Fault Open load NO Fault

I_IGNx Open load fault happened

Ith_OL_IGN

t
Filter time for IGN

Driver status

Enabled HIGH Enabled LOW

t
Enabled LOW
IGNx_ol

Read_Diag_CMD

t
GADG0512161627PS

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263
Pre-drivers - IGNITER IGN[1:6] L9788

Conditions:
5.5 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified;

Table 56. Pre-driver - IGNITER electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

High-side current generator parameters

VIGNX = 4 V
VDD5 = 5 V 
High-side output MSC Bit
IOH1_HS_IGN 4.7 - 15.3 mA IGN1/2/3/4/5/6
current 1 IGN_CURRENT
CFG = 1,
OL_RED = 0
VIGNX = 4 V
VDD5 = 5 V
High-side output MSC Bit
IOH1_HS_IGN_OL_RED 2 - 15 mA IGN1/2/3/4/5/6
current 1 IGN_CURRENT
CFG = 1,
OL_RED = 1
VIGNX = 4 V
VDD5 = 5 V
High-side output MSC Bit
IOH2_HS_IGN 14.7 - 30.3 mA IGN1/2/3/4/5/6
current 2 IGN_CURRENT
CFG = 0 (Default
Value)
Isource = 5 mA
MSC Bit
Output voltage 1 VDD5
VOH1_HS_IGN IGN_CURRENT - VDD5 V IGN1/2/3/4/5/6
@ high-side on -0.4
CONFIG = 1,
OL_RED = 0
Isource = 2 mA
MSC Bit
Output voltage 1 VDD5
VOH1_HS_IGN_OL_RED IGN_CURRENT - VDD5 V IGN1/2/3/4/5/6
@ high-side on -0.4
CONFIG = 1,
OL_RED = 1
Isource = 15mA
MSC Bit
Output voltage 2 VDD5
VOH2_HS_IGN IGN_CURRENT - VDD5 V IGN1/2/3/4/5/6
@ high-side on -0.6
CONFIG = 0
(Default Value)
High-side leakage
IOFF_LK_IGN current @ off IGNx = 2.5 V in off - - 10 µA IGN1/2/3/4/5/6
condition

Low-side MOSFET parameters

Drain–source I_load = 0.1A

RDS-on_LS_IGN 1.8 2.2 3.1 Ω IGN1/2/3/4/5/6
resistance @ T = -40 °C

Drain–source I_load = 0.1 A

RDS-on_LS_IGN 2.4 3.0 3.91 Ω IGN1/2/3/4/5/6
resistance @ T = 27 °C

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L9788 Pre-drivers - IGNITER IGN[1:6]

Table 56. Pre-driver - IGNITER electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Drain–source I_load = 0.1 A

RDS-on_LS_IGN 3.8 5.0 7.0 Ω IGN1/2/3/4/5/6
resistance @ T = 150 °C

Output voltage @ IOL = 20 μA

VOL_LS_IGN - - 0.1 V IGN1/2/3/4/5/6
LS low-side on sinked

Output voltage @ IOL= 100 mA

VOL_LS_IGN - - 0.7 V IGN1/2/3/4/5/6
LS low-side on sinked

Body diode
I_load = 0.3 mA
Irev_LS_IGN reverse current - - 1 V IGN1/2/3/4/5/6
sourced
voltage drop

General IGN block parameters

CLOAD =10 nF
TDON_IGN Turn-on delay time - - 10 µs IGN1/2/3/4/5/6
Isource = 10 mA

TDOFF_IGN Turn-off delay time CLOAD = 10 nF - - 10 µs IGN1/2/3/4/5/6

CLOAD = 10 nF
TR_IGN Output rise time - - 9 µs IGN1/2/3/4/5/6
Isource = 10 mA

TF_IGN Output fall time CLOAD = 10 nF 0.05 - 2 µs IGN1/2/3/4/5/6

Output leakage
IOUT_LK_IGN Vpin = 13.5 V - - 10 µA IGN1/2/3/4/5/6
current

Short circuit to
Vth_STB_IGN VBAT voltage IGNx = VBAT 5.3 - 6.5 V IGN1/2/3/4/5/6
threshold

Short circuit to
Vth_STG_IGN - 2.1 - 2.7 V IGN1/2/3/4/5/6
GND threshold

Leakage current
@ short circuit to
Ileak_STG_IGN IGNx = GND - - 10 µA IGN1/2/3/4/5/6
GND, IGN in tri-
state
Leakage current
@ short circuit to
Ileak_STB_IGN IGNx = VBAT - - 1 mA IGN1/2/3/4/5/6
VBAT,IGN in tri-
state
Leakage current
GND = VB_IN =
Ileak_STB_IGN @ short circuit to - - 10 µA IGN1/2/3/4/5/6
0V IGNx = 18 V
VBAT
Open load and
TFLT_SCGOL IGN short circuit to - 72 - 90 µs IGN1/2/3/4/5/6
GND filter time

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Pre-drivers - IGNITER IGN[1:6] L9788

Table 56. Pre-driver - IGNITER electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Short circuit to
TFLT_SCB IGN VBAT switch-off - 5.9 - 7.2 µs IGN1/2/3/4/5/6
delay

Open load current

Ith_OL_IGN - 0.18 - 1.22 mA IGN1/2/3/4/5/6
threshold

Open load current

Ith_OL_IGN_OL_RED OL_RED = 1 0.03 - 0.2 mA IGN1/2/3/4/5/6
threshold

134/264 DS12308 Rev 4

L9788 Inductive sensor interface

11 Inductive sensor interface

The interface handles signals coming from magnetic pick-up sensors or Hall Effect sensors.
The interface feeds the digital signal to microcontroller that extracts flying wheel rotational
position, angular speed and acceleration.

11.1 VRS interface

VRS interface runs either in normal mode to convert the input differential voltage or in
diagnostic mode to detect eventual short to ground, short to battery or open condition at
sensor pins. Figure 55 shows the main parts inside VRS block and, in red, the internal
connection in case of diagnostic mode active.

Figure 55. VRS interface block diagram

Nȍ FLW_IN_P

Nȍ
VRS_DIAG=1
VRS Vcm_DIAG FLW_OUT
SENSOR Filter Time
Vcm NORM
VRS_CONF_
Nȍ MODE_1

Nȍ FLW_IN_N I_DIAG

VRS_HYST_FB

DIAG

LIMITED / FULLY
ADAPTIVE
HYSTERESIS
MSC SELECTOR

MANUAL

VRS_FB

GADG0612160835PS

Operating mode is defined in VRS register through VRS_DIAG in CONFIG_REG8 bit: when
VRS_DIAG=0, VRS block is set in normal mode; when VRS_DIAG=1 the VRS diagnosis
mode is activated.
If L9788 is supplied and VRS is running, in case FLW_IN_P or FLW_IN_N voltage rises their
values are clamped at VclpH.
In case of activation of clamp both on FLW_IN_P and FLW_IN_N, it is guaranteed by design
that FLW_IN_P voltage is higher than FLW_IN_P.

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Inductive sensor interface L9788

11.2 VRS - Normal mode

The VRS normal mode is set with VR_DIAG=0
In Normal mode, the circuit is configured as the one reported in Figure 56. It allows
decoding the VRS signal while flying wheel is in rotation.
Due to high variability of the input signal (±200 V) The input is clamped in the range
[VclpH:VclpL] in order to allow the analog circuitry processing the signal itself. Moreover, the
sensor input pins have an input common mode, VCM.
The preconditioned input signal is then processed by a zero-crossing comparator, which
toggles at each transition of the input signal.

Figure 56. VRS block diagram - Normal operating mode

Nȍ FLW_IN_P

Nȍ

VRS FLW_OUT
Vcm_NORM Filter Time
SENSOR
VRS_CONF_
Nȍ MODE_1

Nȍ FLW_IN_N
VRS_HYST_FB

LIMITED / FULLY
ADAPTIVE
HYSTERESIS
SELECTOR
SPI
MANUAL

VRS_FB

GADG0612160922PS

To avoid spurious commutations of the zero crossing comparator, a hysteresis mechanism

is implemented. L9788 is able to sink a hysteresis current which generates a voltage drop
across the external resistors. The voltage levels related to the hysteresis function shown
hereafter are calculated considering an external series resistance of 10 kΩ on FLW_IN_P
and 10 kΩ on FLW_IN_N pins.
As reported in Figure 57, the Vdiff (FLW_IN_P - FLW_IN_N) input differential signal exhibits
some steps at each zero crossing:
 when the output of the zero crossing comparator is high, the hysteresis current is kept
OFF;
 when the output of the zero crossing comparator is low, the hysteresis current is
switched ON.
This approach applies the hysteresis current only on the transition L-H of the VRS_FB
signal.

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L9788 Inductive sensor interface

Figure 57. Hysteresis application

GADG0612160927PS

The output of the zero crossing comparator can be further processed by a filtering circuit or
directly routed to FLW_OUT.

11.2.1 VRS normal mode configurations

L9788 integrates two main configurable architectures: VRS_A and VRS_B. These
architectures are selected in VRS register, VRS_MODE_SEL bit in CONFIG_REG 2.
Once VRS_A (VRS_MODE_SEL =1) or VRS_B (VRS_MODE_SEL =0) has been
configured, hysteresis and filtering strategy are defined through VRS_MODE[1:0] bit in the
same CONFIG_REG 8 register:
VRS_MODE[1] defines filtering function (OFF/ON and if ON, its time value)
VRS_MODE[0] defines the hysteresis (manual or adaptive)
Table 57 summarizes the parameters of VRS_A and VRS_B architecture; the next
paragraphs detail the two configurations.

Table 57. VRS_A, VRS_B hysteresis and filter time definition

VRS_MODE VRS
Filter Hyst.
_SEL _MODE[1:0]

VRS_A configuration

1 00 OFF 0 µs Manual Ref to VRS_A - Manual Hysteresis

1 01 OFF 0 µs Full adaptive Ref. to VRS_A - Fully Adaptive Hysteresis
1 10 ON T(n-1)/32 Manual Ref to VRS_A - Manual Hysteresis
1 11 ON T(n-1)/32 Full adaptive Ref. to VRS_A - Fully Adaptive Hysteresis

VRS_B configuration

0 00 OFF 0 µs Manual Ref. to VRS_B - Manual Hysteresis

0 01 OFF 0 µs Limited adaptive Ref. to VRS_B -Limited Adaptive Hysteresis
0 10 ON 4 µs Manual Ref. to VRS_B - Manual Hysteresis
0 11 ON 4 µs Limited adaptive Ref. to VRS_B -Limited Adaptive Hysteresis

In case a change of VRS_MODE_SEL bit within the normal operating mode occurs (1->0 or
0->1) with hysteresis current active, this leads to the change of the hysteresis (to HI1 or HI3,

DS12308 Rev 4 137/264

263
Inductive sensor interface L9788

according to the new selection programmed) not synchronized with any VRS_FB zero
crossing.

11.2.2 VRS_A - Manual Hysteresis

To set the manual hysteresis on VRS_A configuration, bit VRS_MODE[0] has to be
configured at '0'. Hysteresis value is manually set through VRS_HYST[2:0] of CONFIG-
REG 8 according to Table 58. Such hysteresis is fixed until a new SPI programming occurs.
Default hysteresis current after exiting reset is HI3.
New MSC current value is updated during HYST CURRENT OFF phase that means the
output comparator is high.

Table 58. VRS_A hysteresis value

Hysteresis Correspondent value on
Min Typ Max Unit Unit
current [H] 20 kΩ ext. resistor

HI1 3 5 7 µA 100 mV
HI2 7.5 10 13.5 µA 200 mV
HI3 13 17 23 µA 347 mV
HI4 23 32 40 µA 644 mV
HI5 35 51 60 µA 1020 mV
No Hyst - - - - - -

138/264 DS12308 Rev 4

L9788 Inductive sensor interface

11.2.3 VRS_A - Fully Adaptive Hysteresis

To set the adaptive hysteresis on VRS_A configuration, bit VRS_MODE[0] has to be set to
'1'. In this configuration, VRS input differential signal is fed into a peak detector circuit and
then quantized on 5 different voltage levels, based on 4 PVi thresholds (see Table 59).
Default hysteresis current after exiting reset is HI3.

Table 59. Peak voltage value ranges

Peak voltage [PVi] Min Typ Max Unit

PV1 600 930 1300 mV

PV2 1200 1600 1950 mV
PV3 2000 2300 2650 mV
PV4 2600 3000 3300 mV

The quantized output is sent to a logic block (Hysteresis Selection Table) that chooses the
proper hysteresis value (HIi) depending on the input peak voltage (PVi), see Table 60.

Table 60. Insert title here

Input peak voltage range Selected hysteresis (HIi)

0 - PV1 HI1
PV1 – PV2 HI2
PV2 – PV3 HI3
PV3 – PV4 HI4
> PV4 HI5

Peak detector and Hysteresis Selection Table circuits are enabled by VRS_FB signal
according to HYS_FB_SEL in CONFIG-REG 8 bit value that establishes if the feedback
signal is before or after the filter time.
VRS input differential voltage is continuously acquired: its max value, reached during time-
frame VRS_FB signal is asserted (hysteresis current is off), is latched through a peak
detector; such a peak defines a specific value of hysteresis current, turned on as soon as
the VRS_FB falls to zero and switches OFF when next rising edge occurs.
Based on the hysteresis current, the signal is processed by a squaring circuit which
processes the output signal of the comparator, see Figure 58.

DS12308 Rev 4 139/264

263
Inductive sensor interface L9788

Figure 58. VRS_A fully adaptive hysteresis

Square circuit
FLW_IN_P VRS_CONF_MODE_1

DV FLW_OUT
int_vrs
Filter Time

FLW_IN_N

Hi

Hi Hysteresis
PVi VRS_HYST_FB
Selection
Peak Detector H5 Table
ADC H4
H3
H2
H1

PV1
PV2
PV3
PV4
0
PV

VRS_FB

GADG0612161130PS

11.2.4 VRS_A - Adaptive filter time

In VRS_A mode, it is possible to enable the filter time on the output of the zero crossing
comparator through the bit VRS_MODE[1] of CONFIG-REG 8.
Once enabled, the most suitable internal filter based on the input signal frequency is
determined.
According to VRS previous output period, filter time value is updated as follows:

Tperiod (n-1)
Tfilter (n) =
32
GADG0612161215PS

If the value of the previous period is lower than 128 µs, the filter time would be saturated at
4 µs fixed value. After reset Tfilter = 200 µs (TYP)
Through EN_FALLING_FILT CONFIG-REG8 bit in VRS register, it is possible to configure
two different strategies for the filtering algorithm.
VRS_OUT rising edge: the transition depends on the hysteresis crossing of differential
signal Vdiff; VRS output is set if Vdiff remains asserted and stable for a period longer than
Tfilter.
VRS OUT falling edge: the transition depends on the zero crossing of differential signal
Vdiff:
 EN_FALLING_FILT = 1: VRS_OUT is deasserted when the signal is low and remains
stable for at least Tfilter; see Figure 59
 EN_FALLING_FILT = 0: VRS_OUT is de-asserted at first zero crossing transition of
differential signal and next eventual commutations are ignored for Tfilter time. see
Figure 60.

140/264 DS12308 Rev 4

L9788 Inductive sensor interface

Figure 59. EN_FALLING_FILT = 1

Vdiff

FILTER TIME

VRScomp_filt

GADG0612161235PS

Figure 60. EN_FALLING_FILT = 0

Vdiff

MASK TIME

VRScomp_filt

GADG0612161240PS

11.2.5 VRS_B - Manual Hysteresis

To set the manual hysteresis on VRS_B configuration, bit VRS_MODE [0] has to be set to
'0'. Hysteresis value is manually set through VRS_HYST [2:0] of CONFIG-REG 8 according
to Table 58 Such hysteresis is fixed until a new SPI programming occurs.
Once a new value is defined, new hysteresis threshold is applied after the second VRS_FB
H-L transition and until the next rising edge of the VRS input differential voltage occurs.

11.2.6 VRS_B -Limited Adaptive Hysteresis

To set the limited adaptive hysteresis on VRS_B configuration, bit VRS_MODE [0] has to be
set to '1'. In this mode, user programs a hysteresis threshold through VRS_HYST [2:0] bit in
VRS register and the internal logic selects a hysteresis based on input signal peak value:
the maximum of these two values is actually applied.
Once a new value is defined, new hysteresis threshold is applied after the second VRS_FB
H-L transition and until the next rising edge of the VRS input differential voltage occurs.

11.2.7 VRS_B - Fixed Filter Time

In VRS_B configuration, it is possible to enable the filter time on the output of the zero
crossing comparator through the bit VRS_MODE[1] of VRS register. This configuration
allows defining the internal filter time at a fixed value of 4 µs, active on both rising and falling
edges of VRS output.

DS12308 Rev 4 141/264

263
Inductive sensor interface L9788

As per VRS_A architecture, EN_FALLING_FILT allows configuring the same two different
strategies for the filtering algorithm.

11.3 VRS diagnostic mode

The diagnostic mode is selected through VRS_DIAG = '1' in CONFIG-REG8. This mode
provides feedback to detect faulty conditions either on FLW_IN_P or FLW_IN_N.
To be noted that diagnostic results are not reliable while the flying wheel is rotating.
If a fault is detected in DIAG mode, VRS correct functionality is not guaranteed. Fault bit
VRS_DIAG of VRS register is consequently set.
Figure 61 shows the circuit used ikn Diagnostic mode. When VRS diagnostic mode is
activated, FLW_IN_P is fixed at Vcm_DIAG and IDIAG current generator is enabled, the
current path is that one in green in Figure 61.

Figure 61. VRS block diagram - Diagnostic operating mode - Current path

Nȍ FLW_IN_P

VRS_DIAG=1
Vcm_DIAG Nȍ

VRS FLW_OUT
SENSOR Filter Time

I_DIAG VRS_CONF_
Nȍ MODE_1

Nȍ FLW_IN_N
VRS_HYST_FB

DIAG

LIMITED / FULLY
ADAPTIVE
HYSTERESIS
MSC SELECTOR

MANUAL

VRS_FB

GADG0612161457PS

11.4 Application circuit

Sensor sketch and parameters are reported in Figure 62 and Table 61.

Figure 62. Sensor sketch

Ȧ
VRS IN +

Rs
Vdiff

Ls
IN -

GAPGPS00571

142/264 DS12308 Rev 4

L9788 Inductive sensor interface

Table 61. VRS sensor parameters

Symbol Parameter Min Typ Max Unit

Rs Sensor resistance 300 600 1000 Ω

Ls Sensor inductor - 250 - mH
Vdiff Sensor output voltage -200 - +200 V
Tout Output period 100 - 5000 µs

The interface handles signals coming from magnetic pick-up sensors, see Figure 63, or Hall
Effect sensors with two possible configurations, as per Figure 64 and Figure 65.
The interface feeds the digital signal to microcontroller that extracts flying wheel rotational
position, angular speed and acceleration.

Figure 63. Variable reluctance sensor (VRS)

ECU

L9788 FLW_IN_P VRS +

10 kŸ

Ȧ
100 pF
100 nF

470 pF VRS

Rs
470 pF

33 kŸ
33 kŸ

Ls

SMART VRS -
Sensor
FLW_IN_N 10 kŸ
VRS
100 pF

470 pF

FLW_OUT
To μC

GADG0912161108PS

DS12308 Rev 4 143/264

263
Inductive sensor interface L9788

Figure 64. Hall effect sensor configuration 1

VSENSEx
Alim_Hall_S
ECU VSENSEx

2.7 kŸ
Ȧ
L9788 FLW_IN_P VRS + Hall Effect
27 kŸ
Sensor

470 pF

1 nF
Rif _Hall_S
3v3
33 kŸ

SMART
FLW_IN_N
VRS Placed close
to L9788
470 pF
33 kŸ

FLW_OUT
To μP

GADG0912161112PS

Figure 65. Hall effect sensor configuration 2

VSENSEx
Alim _Hall_S
ECU VSENSEx
2.7 kŸ

Ȧ
L9788 FLW_IN_P VRS +
27 kŸ
1 nF
470 pF

Rif_Hall_S
3v3

Hall Effect
33 kŸ

SMART Sensor
FLW_IN_N
VRS Placed close
to L9788
470 pF
33 K©

FLW_OUT
To μP

GADG0912161120PS

144/264 DS12308 Rev 4

L9788 Inductive sensor interface

Conditions:
5.5 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified;

Table 62. Flying wheel interface function - Diagnosis test

Symbol Parameter Test condition Min Typ Max Unit Pin

Input high-to-low
FLW_IN_P
ViThL differential threshold - -50 0 50 mV
FLW_IN_N
voltage
Common mode Not to be tested. It is an FLW_IN_P
VCM 0 1.65 3 V
operating range application note. FLW_IN_N
Input high clamping |I_FLW_IN_P|=|I_FLW_IN_N|= 3.3 3.3 V FLW_IN_P
VclpH -
voltage 20 mA, device ON -0.3 +0.3 V FLW_IN_N
Input high clamping |I_FLW_IN_P|=|I_FLW_IN_N|= FLW_IN_P
VclpH 1 - 2.8 V
voltage 20 mA, device OFF FLW_IN_N
Input low clamping |I_FLW_IN_P|=|I_FLW_IN_N|= FLW_IN_P
VclpL -1.5 - -0.3 V
voltage 20 mA FLW_IN_N
Output open load FLW_IN_P = FLW_IN_N = FLW_IN_P
Vopenload 1.5 (3.3) /2 1.8 V
voltage Vopenload FLW_IN_N
Input bias current FLW_IN_P
Ibvrsp VRS_INP -> FLW_IN_P - - 2 µA
Vrsp FLW_IN_N
Input bias current FLW_IN_P
Ibvrsm FLW_IN_N = Vopenload - - 2 µA
Vrsm FLW_IN_N
VDD5 = 5 V or 3.3 V 
VOL Output Low Voltage - - 0.5 V FLW_OUT
Isink current = 2 mA
VDD5 = 5 V or 3.3 V  VDD5
VOH Output High Voltage - - V FLW_OUT
Isource current = 2 mA -0.5
Input leakage current
Ilk_outvrs - - - 1 µA FLW_OUT
to GND
Input leakage current
Ilk_outvrs - - - 8 µA FLW_OUT
to VDD5
Td_on_outvrs Delay on falling edge Test Ext cap = 300 pF - - 1 µs FLW_OUT
Td_off_outvrs Delay on rising edge Input signal=4ms - - 150 µs FLW_OUT
T_r_Out_vrs MRX Rise Time Test Ext cap = 300 pF - - 150 ns FLW_OUT
T_f_Out_vrs MRX Fall Time Test Ext cap = 300 pF - - 150 ns FLW_OUT
Voutdiag Output diag voltage FLW_IN_P = open; diag mode 0.9 (3.3)/3 1.3 V FLW_OUT
FLW_IN_P = open;
Ioutdiag Output diag Current 50 65 80 µA FLW_OUT
FLW_IN_N= GND; diag mode

Voutsh Output Short-circuit

FLW_IN_P = open;
range to VBAT Open 2.8 3 3.2 V FLW_OUT
Vbdiagth FLW_IN_N = Vramp; diag mode
Load threshold
Output Short-to GND FLW_IN_P = open;
Voutshgnddiagth 1.1 1.3 1.5 V FLW_OUT
range threshold FLW_IN_N = Vramp; diag mode

Note: When FLW_IN_P and FLW_IN_N are both in input high clamping condition, the clamp
voltage of FLW_IN_N is 30 mV (typical) higher than FLW_IN_P.

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12 CAN FD interface

Figure 66. CAN FD interface diagram

V5V

V3V3_DIG
VDD_CAN

TX
CAN_TX

V3V3_EOT

RX + CANH
- CANL
CAN_RX
VDD_CAN

DIG

V3V3_EOT

EN GND_CAN
RX_ECHO CAN_LOGIC
CAN_OSC
CAN_ON MSC_BIT

VDD_CAN
OV / UV

GADG0912161250PS

The pins related to this block are:

 CANH;
 CANL;
 CANTX;
 CANRX;
 GND_CAN;
 VB_CAN;
 VDD_CAN
VDD_CAN= 5V is the supply for the CAN transceiver block. The voltage on this pin is
monitored and if the voltage is below VDD_CAN_SUP_LOW for a tcansuplow filter time an
undervoltage fault on VDD_CAN is detected. The fault is latched in a dedicated MSC flag
CAN_SUP_LOW until an MSC Upstream Read14 is given. While the undervoltage fault is
detected on VDD_CAN the CAN transmitter stays disabled (not MSC read clear access is
necessary to restore the transmitter just the fault detection expiration).

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L9788 CAN FD interface

If VDD_CAN is above VDD_CAN_SUP_OV for a tcansuphigh filter time an overvoltage fault

on VDD_CAN is detected. The fault is latched in a dedicated MSC flag VDD_CAN_OV until
an MSC Upstream Read14 is given during the MSC flag VDD_CAN_OV stays set the CAN
transmitter is disabled
During a VDD_CAN overvoltage or undervoltage detected fault the biasing voltage is
switched from VDD_CAN to a pre-regulated internal voltage (2.5V) supplied by VB_STBY.
When the fault ends the biasing voltage switches again on VDD_CAN. The msc flag
VDD_CAN_OV or CAN_SUP_LOW remains latched until an MSC Upstream Read14 is
given.
The biasing voltage is switched from VDD_CAN to a pre-regulated internal voltage (2.5V)
supplied by VB_STBY also in CAN_BIAS_ON and CAN_BIAS_OFF.
VB_CAN is the signal that enables CAN cell; if this pin is connected to VB_STBY the CAN is
enabled while if it's connected to GND the CAN is disabled

12.1 Functional description

General requirements:
 Compliant with C&S CAN FD certification(ISO16845-2:2015);
 Communication Speed up to 2 Mbit/s. (up to 5Mbit/s in "programming" mode);
 Function range from -27 V to +40 V DC at CAN Pins;
 GND disconnection fail safe at module level;
 GND shift operation at system level;
 Microcontroller interface with CMOS compatible I/O Pins;
 Matched output slopes and propagation delay;
 Receive-only mode available.
In order to further reduce the current consumption in low-power mode, the integrated CAN
bus interface offers an ultra low current consumption state when the u-chip is off called
Sleep mode.

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12.2 CAN state diagram

Figure 67. CAN state diagram

UCHIP-ON
msc_bit_wakeup_en = '1'
and
WU DETECTION
and
msc_bit_auto_bias = '1'
(WAKE_UP_CAN_DET_AUTO is latched) msc_bit_auto_bias = '0'
or
Tsilence expired

msc_bit_wakeup_en = '1'
and
WU DETECTION CAN_STBY_ON
CAN_BIAS_ON and
msc_bit_auto_bias = '1' Trasmitter: Disabled
Trasmitter: Disabled (WAKE_UP_CAN_DET_AUTO is latched) Receiver: Enabled
Receiver: Enabled RXD:Wake-up/HIGH
RXD:Wake-up/HIGH BIAS OFF
BIAS ON
LOW POWER MODE
(MSC_BIT_CAN_EN =0)
{msc_bit_can_en = '1'
and
(msc_bit_can_tx_en = '0'
or
msc_bit_can_en = '0' inhibit = '1' (rst_matrix*10*12)
(configure by MSC or or msc_bit_can_en = '0'
clear by reset matrix*13) Dominant timeout = '1' (configure by MSC or
and or clear by reset matrix*13)
msc_bit_auto_bias = '1' CAN_perm_recessive = '1' and
or msc_bit_auto_bias = '0'
{msc_bit_can_en = '1' RXDC perm_rec = '1'
and or msc_bit_can_en = '0'
(msc_bit_can_tx_en = '0' VDD_CAN_OV = '1')} (configure by MSC or
or clear by reset matrix*13) {(msc_bit_wakeup_en = '1'
inhibit = '1' (rst_matrix*10*12) and and
or msc_bit_auto_bias = '0' WU DETECTION)
Dominant timeout = '1' Uchip off OR
or Uchip on}
CAN_perm_recessive = '1' and
or msc_bit_can_en = '0'
CAN_RX and
RXDC perm_rec = '1' msc_bit_can_auto_bias = '1'
or Trasmitter: Disabled
VDD_CAN_OV = '1')} Receiver: Enabled
RXD:HIGH/BITSTREAM msc_bit_can_en = '1' {(msc_bit_wakeup_en = '1'
msc_bit_can_rx_en 0/1(default 1) and and
msc_bit_can_tx_en = '1' WU DETECTION)
msc_bit_can_en = '0' OR
(configure by MSC or BIAS ON and
inhibit = '0' (rst matrix *10*12) Uchip on}
clear by reset matrix*13) and
and and msc_bit_can_en = '0'
Dominant timeout = '0' {(msc_bit_wakeup_en = '1'
msc_bit_auto_bias = '1' and and
and msc_bit_can_auto_bias = '0'
msc_bit_can_tx_en = '0' CAN_perm_recessive = '0' WU DETECTION)
msc_bit_can_tx_en = '1' or OR
and and
inhibit = '1' (rst matrix *10*12)RXDC perm_rec = '0' Uchip on}
inhibit = '0' (rst matrix*10*12) or and
and and msc_bit_can_en = '1'
Dominant timeout = '1'
Dominant timeout = '0' NORMAL MODE VDD_CAN_OV = '0' and
msc_bit_can_en = '1' and (MSC_BIT_CAN_EN =1) or
CAN_perm_recessive = '1' {msc_bit_can_tx_en = '0'
and CAN_perm_recessive = '0' or or
msc_bit_can_tx_en = '1' and RXDC perm_rec = '1' inhibit='1'(rst_matrix*10*12)
and RXDC perm_rec = '0' or or
inhibit = '0' (rst matrix*10*12) and {(msc_bit_wakeup_en = '1' Dominant timeout = '1'
VDD_CAN_OV = '1' and
and VDD_CAN_OV = '0' or
Dominant timeout = '0' WU DETECTION) CAN_perm_recessive = '1' {(msc_bit_wakeup_en = '1'
and OR or and
CAN_perm_recessive = '0' Uchip on} RXDC perm_rec = '1' WU DETECTION)
and or OR
and msc_bit_can_en = '1'
RXDC perm_rec = '0' CAN_TRX VDD_CAN_OV = '1'} Uchip on}
and and
and Trasmitter: Enabled {msc_bit_can_tx_en = '1'
VDD_CAN_OV = '0' msc_bit_can_en = '1'
Receiver: Enabled and and
RXD:HIGH/BITSTREAM inhibit='0'(rst_matrix*10*12) {msc_bit_can_tx_en = '0'
{(msc_bit_wakeup_en = '1' and or
msc_bit_can_rx_en 0/1(default 1) and Dominant timeout = '0'
WU DETECTION) inhibit='1'(rst_matrix*10*12)
and or
BIAS ON OR CAN_perm_recessive = '0'
Uchip on} Dominant timeout = '1'
and or
and RXDC perm_rec = '0' CAN_perm_recessive = '1'
msc_bit_can_en = '1' and or
and VDD_CAN_OV = '0'} RXDC perm_rec = '1'
{msc_bit_can_tx_en = '1' or
and VDD_CAN_OV = '1'}
inhibit='0'(rst_matrix*10*12)
and
UCHIP-OFF
Dominant timeout = '0'
and
CAN_perm_recessive = '0'
and
RXDC perm_rec = '0'
{(msc_bit_wakeup_en = '1' and
and VDD_CAN_OV = '0'}
WU DETECTION)
OR
Uchip on} CAN_STBY_OFF CAN_BIAS_OFF
and msc_bit_wakeup_en = '0'
msc_bit_can_en = '0' Trasmitter: Disabled
Trasmitter: Disabled
and Receiver: Disabled/Enabled
msc_bit_can_auto_bias = '1' (msc_bit_wakeup_en 0/1) Receiver: Enabled
RXD:no output RXD:no output
Tsilence expired
CAN register reset defaut values on POR VBSTBY BIAS OFF BIAS ON
MSC_BIT_CAN_TX_EN = 1
MSC_BIT_CAN_RX_EN = 1
MSC_BIT_CAN_EN = 1
MSC_CAN_TXD_DOM_EN = 1
MSC_CAN_PERM_REC_EN= 1
MSC_CAN_PERM_DOM_EN= 1
MSC_CAN_RXD_REC_EN=1 from any other state except CAN_STBY_ON
MSC_CAN_AUTO_BIAS = 1 Uchip off LOW POWER MODE
and
msc_can_auto_bias ='0'
CAN register masked with RSTN = 0
Trasmitter disabled
(MSC_BIT_CAN_TX_EN = 0)
Diagnostics disabled from any other state except CAN_STBY_ON Uchip off
(MSC_CAN_TXD_DOM_EN = 0 and
MSC_CAN_PERM_REC_EN= 0 msc_can_auto_bias ='1'
MSC_CAN_PERM_DOM_EN= 0
MSC_CAN_RXD_REC_EN=0)
GADG0912161302PS

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12.3 CAN normal mode

If CAN_EN bit MSC_CONFIG-REG17-1[2] is set and the U-chip is in ON state the CAN
transceiver is in normal mode (referring to state diagram, CAN_RX or CAN_TRX state). In
this state the transmitter and receiver can be configured by MSC (CAN_TX_EN,
CAN_RX_EN) as follows:
 TRX Standby: transmitter disabled and CAN_RX pin masked to 1(CAN_TX_EN = '0',
CAN_RX_EN = '0');
 TRX Listen: transmitter disabled, receiver enabled (CAN_TX_EN = '0', CAN_RX_EN =
'1');
 TRX transmit: transmitter enabled CAN_RX pin masked to 1 (CAN_TX_EN = '1',
CAN_RX_EN = '0');
 TRX Normal (default): transmitter enabled receiver enabled (CAN_TX_EN = '1',
CAN_RX_EN = '1')
In normal mode the CAN biasing is always active
Wake up by CAN disabled option is allowed only for the application that does not require the
transceiver (CANH/L not connected to any bus).

12.4 CAN low-power mode

When L9788 is ON it is possible to deactivate the CAN transceiver setting the MSC bit
CAN_EN (MSC_CONFIG-REG17_1[2]) to zero, sending the CAN in Low-power Mode. The
CAN transceiver remains deactivated until it will be activated again setting the CAN_EN bit.
When L9788 is OFF the CAN transceiver is always in Low-power Mode independently from
any other configuration bit except CAN_WAKEUP_EN, which if set to zero, sends it to Sleep
mode once the transceiver goes to CAN_STBY_OFF state. In Low-power mode the biasing
can be active or inactive depending on CAN_AUTO_BIAS bit value and from the CAN bus
activity (see state diagram), furthermore the transmitter is always disabled and the CAN_RX
pin is always masked to recessive. When biasing is disabled the receiver input termination
will be biased at zero volt.

12.5 CAN Sleep Mode

When the CAN transceiver goes in CAN_STBY_OFF with CAN_WAKEUP_EN = '0' it falls in
an ultra low current consumption state called Sleep mode. In this state for the L9788 is
impossible to detect Wake-up activity on CAN bus and consequently no power-up is done
for a CAN detection (pattern or no pattern).

12.6 CAN error handling

CAN Driver HS and LS are supplied by a dedicated pin (VDD_CAN) to avoid disturbances
of CAN activity on main supply lines. After internal power on reset of VB_STBY the CAN
transceiver is configured according to the configuration register bit default values. When the

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CAN transceiver is in normal mode, the transmitter is disabled and its state changes to
CAN_RX in case of at least one of the following events:
 Dominant TxDC time out and CAN_TXD_DOM_EN MSC bit = 1;
 CAN permanent recessive CAN_PERM_REC_EN MSC bit = 1;
 RxDC permanent recessive CAN_RXD_REC_EN MSC bit = 1;
 VDD_CAN overvoltage detection (MSC bit VDD_CAN_OV = 1);
 VDD_CAN undervoltage detection active;
 MSC bit CAN_TX_EN = 0;
 Reset matrix Conditions *10*12 (see Reset Matrix section).
The CAN receiver is not disabled in case of any failure condition.
The device provides the following 4 error handling features; the CAN error handling function
can be disabled by setting the dedicated corresponding MSC bit. The error handling must
be also enabled by setting the CAN_EN bit MSC_CONFIG-REG17-1[2].

12.6.1 Dominant CAN_TX time out

If CAN_TX is in dominant state (low) for t > tTXDC_DOM_TO the transmitter will be disabled,
CAN_TXD_DOM status bit will be latched and can be read and cleared by MSC. The
transmitter remains disabled until the status register is cleared or until the state returns
recessive according to the setting of the bit CAN_TX_DOM_ERR_CFG MSC CONFIG-
REG21 [0]. The detection of this error is enabled by the CAN_TXD_DOM_EN bit
MSC_CONFIG_REG21[3] and by the CAN_TX_EN bit MSC_CONFIG_REG17_1[3].

12.6.2 CAN permanent recessive

If CAN_TX changes to dominant (low) state but CAN bus does not follow for 4 times, the
transmitter will be disabled, CAN_PERM_REC status bit will be latched and can be read
and cleared by MSC. The transmitter remains disabled until the status register is cleared.
The detection of this error is enabled by the CAN_PERM_REC_EN bit
MSC_CONFIG_REG21[4] and by the CAN_TX_EN bit MSC_CONFIG_REG17_1[3].

12.6.3 CAN permanent dominant

If the bus state is dominant (low) for t > tdom a permanent dominant status will be detected.
CAN_PERM_DOM status bit is latched and can be read and cleared by MSC. The
transmitter will not be disabled. The detection of this error is enabled by the
CAN_PERM_DOM_EN bit MSC_CONFIG_REG21[5].

12.6.4 CAN_RX permanent recessive

If CAN_RX Pin is clamped to recessive (high) state, the controller is not able to recognize a
bus dominant state and could start messages at any time, which results in disturbing the
overall bus communication. Therefore, if CAN_RX does not follow CAN_TX for 4 times the
transmitter will be disabled. CAN_RXD_REC status bit will be latched and can be read and
cleared by MSC. The transmitter remains disabled until the status register is cleared. The
detection of this error is enabled by the CAN_RXD_REC_EN bit MSC_CONFIG_REG21[6]
and by the CAN_TX_EN bit MSC_CONFIG_REG17_1[3].

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12.6.5 Smart reset RSTN effects

In order to avoid spurious interference on CAN Bus and false CAN error detection, during
the power-up sequence, as long the Smart Reset RSTN pin signal stays low the following
CAN configuration registers are masked to zero:
 CAN_TX_EN (transmitter disabled);
 CAN_TXD_DOM_EN (Dominant TxDC Time Out disabled);
 CAN_PERM_REC_EN (CAN Permanent Recessive disabled);
 CAN_PERM_DOM_EN (CAN Permanent Dominant disabled);
 CAN_RXD_REC_EN (CAN RXDC Permanent Recessive disabled).

12.7 Wake up With U-Chip OFF

When the U-chip is off with CAN wake up option enabled (CAN_WAKEUP_EN = '1'), the
CAN transceiver can detect wake up activity on bus and then wake up the device. In this
situation the MSC bit WAKE_UP_CAN_DET is latched (MSC UPSTREAM READ 12,
Frame3). If the U-chip is off with CAN wake up option disabled (CAN_WAKEUP_EN = '0')
and automatic voltage biasing disabled (CAN_AUTO_BIAS = '0') the transceiver goes in
Sleep mode. Otherwise if the U-chip is off with CAN wake up option disabled
(CAN_WAKEUP_EN = '0') and automatic voltage biasing enabled (CAN_AUTO_BIAS = '1')
the transceiver goes in CAN_BIAS_OFF state and after a period greater than Tsilence
without activity on bus goes in Sleep mode.

12.8 Wake up with U-Chip ON

When the U-chip is on and the CAN transceiver is in low power mode (CAN_EN bit = '0')
and the wake up option is enabled (CAN_WAKEUP_EN = '1'), the CAN Transceiver can
detect wake up activity on bus. In this situation the MSC bit WAKE_UP_CAN_DET_AUTO is
latched (MSC UPSTREAM READ 13, Frame3) and a dominant pulse of tdom_pulse is sent on
pad CAN_RX. If the CAN_AUTO_BIAS bit MSC_CONFIG_REG21[7] is set and the CAN
transceiver is in the state CAN_STBY_ON the detection of a wake up activity will bring the
transceiver in the state CAN_BIAS_ON

12.8.1 Wake up options

For the wake up feature the device logic differentiates different Wake-up detection
conditions.

12.8.2 Normal pattern wake up

Normal pattern wake up can occur when CAN pattern wake up option is enabled
(CAN_PATTERN_EN = '1'), the wake up enable bit is set (CAN_WAKEUP_EN = '1') and the
CAN transceiver is in low-power mode. In order to have a Wake-up detection, the following
criteria must be fulfilled:
 The CAN interface wake up receiver must receive a series of two consecutive valid
dominant pulses, each of which must be longer than tfilter;
 The distance between 2 pulses must be longer than tfilter;
 The two pulses must occur within a time frame of twake.

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12.8.3 No pattern wake up

If the CAN pattern wake up option is disabled (CAN_PATTERN_EN = '0') and the wake up
enable bit is set (CAN_WAKEUP_EN = '1') and the transceiver is in Low-power mode, a
dominant state on CAN BUS for more than tfilter will cause a Wake-up detection.

Figure 68. CAN wake up options

Normal Pattern wake-up

>twake
>tfilter >tfilter tfilter

CANH-CANL

U-CHIP STATE ON OFF ON

No Pattern wake-up

tfilter

CANH-CANL

U-CHIP STATE ON OFF ON

GADG0912161440PS

12.9 Automatic voltage biasing

If the CAN transceiver is in Low-power mode (CAN_EN = 0 or U-CHIP OFF) and the
automatic voltage biasing is active (CAN_AUTO_BIAS = '1', MSC_CONFIG-REG21[7) if
there has been no activity on the bus for longer than tSILENCE, the bus lines are biased
towards 0 V via the receiver input resistors RCANH/RCANL (biasing disabled) and the MSC
flag CAN_SILENT is set to 1. If the wake up option is enabled (CAN_WAKEUP_EN = '1')
and a wake-up activity on the bus lines is detected (wake-up pattern or no pattern), the bus
lines are biased to VCANHrec respectively VCANLrec via the internal receiver input
resistors RCANH/RCANL also the MSC bit WAKE_UP_CAN_DET_AUTO is latched (MSC
UPSTREAM READ 12, Frame3). The biasing is activated not later than tBias.

12.10 CAN reset matrix

In the reset matrix table there is a row dedicated to CAN.
Reset matrix *12 source means that at least one of the following faults is active:
 VDD5_OV;
 OSC FAULT;
 TNL;
 RST_N.

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When the CAN transceiver is in normal mode and at least one of the above faults occurs the
transmitter is disabled.
Reset matrix *10 source means that at least one of the following faults is active and the
CAN_TDI bit is set:
 ERR_CNT>4;
 ERR_CNT>7;
 RST_PRL;
When the CAN transceiver is in normal mode and at least one of the above faults occurs the
transmitter is disabled.
Reset matrix *13 source means that at least one of the following faults is active:
1. VB_STBY_UV
2. VB_OV t>TBOV2
3. VB_UV
4. V3V3A_OV, V3V3A_UV, V3V3D_OV and V3V3D_UV
5. VDD5_UV
6. VDDIO_UV
When the CAN transceiver is in normal mode and at least one of the above faults occurs the
MSC bit CAN_EN is cleared sending the CAN transceiver in Low-power Mode.

12.11 CAN looping mode

If the proper configuration bit (CAN_LOOP_EN) in control register is set the TxDC input is
mapped directly to the RxDC Pin. This mode can be used in combination with the CAN
receive-only mode, to run diagnosis for the CAN protocol handler of the microcontroller.

Figure 69. CAN_TX input structure

Input structures: cascoding to
sustain battery level
V3V3
VHIGH V3V3

VLOW
GADG0912161539PS

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CAN FD interface L9788

Figure 70. CAN transceiver test circuit

CANH

RL \ 2
CAN-FD C2
TRANSCEIVER
CANTX VDIFF
C1 VCANH

RL \ 2
CANRX

CA NL
CRX
GND VCANL

GADG2605171108PS

Conditions:
5.5 V ≤ VB_IN ≤ 18 V, 4.5 V ≤ VDD_CAN ≤ 5.5 V, 5 V ≤ VB_STBY ≤ 18 V, Tj -40 to 175 °C
unless otherwise specified;

Table 63. CAN threshold related Low supply voltage flag

Symbol Parameter Test condition Min Typ Max Unit Pin

Threshold to detect CAN

VDD_CAN_SUP_LOW VDD_CAN decreasing 4.5 4.65 4.8 V -
Supply low
Threshold for CAN cell Not tested For
VB_CAN_TH(1) 0.8 - 2.2 V -
enable information only
Threshold to detect CAN
VDD_CAN_SUP_OV VDD_CAN increasing 6.1 6.85 7.5 V -
Supply over-voltage
1. Below this threshold all CAN functions are disabled. In case CAN functionality is requested by application VB_CAN has to
be shorted to VB_stby, otherwise it should be put to GND to disable CAN block.

Table 64. CAN communication operating range

Symbol Parameter Test condition Min Typ Max Unit Pin

Supply Voltage operating

VDD_CAN range for CAN - 4.5 - 5.5 V -
transceiver
Common mode Bus Measured with respect to the
VCANHL,CM voltage ground of the CAN -12 - 12 V -
(VCANH + VCANL) / 2 transceiver
Transceiver current
consumption during
ITRCV_REC(1) normal mode from VTXDC = VTXDCHIGH - - 10 mA -
VDD_CAN, Recessive
State

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L9788 CAN FD interface

Table 64. CAN communication operating range (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Transceiver current
consumption during
ITRCV_DOM(1) normal mode from VTXDC = 0 V - - 60 mA -
VDD_CAN Dominate
State
Transceiver current
RL = 50 Ω to 65 Ω;
consumption during
ITRCV_short VCANH =- 3 V or  - - 120 mA -
output short from
VCANL = 40 V
VDD_CAN
Transceiver current
consumption during low- RL = 50 Ω to 65 Ω;
ITRCVLPbias - - 350 µA -
power mode; biasing VTXDC = VTXDCHIGH;
active from VDD_CAN
Transceiver current
consumption during low- RL = 50 Ω to 65 Ω;
ITRCVLP - - 50 µA -
power mode; biasing VTXDC = VTXDCHIGH;
inactive from VDD_CAN
Transceiver current
ITR_VB consumption from - - - 5 µA -
VB_CAN
Supported bit-rates at which
all requirements are fulfilled
BR Supported Bit-rates 5 - - Mb/s -

Application info
1. To be confirmed after ATE measurements.

Table 65. CAN transmit data input: Pin TxDC

Symbol Parameter Test condition Min Typ Max Unit Pin

Ileak_cantx Input leakage current CAN_TX = VDDIO – 1 V - - 10 µA CAN_TX

Input voltage
VTXDCLOW - 0.9 - 1.4 V CAN_TX
dominant level
Input voltage
VTXDCHIGH - 1.45 - 2 V CAN_TX
recessive level
VTXDCHIGH-
VTXDCHYS - 0.1 - 0.4 V CAN_TX
VTXDCLOW
RTXDCPU TxDC pull up resistor - 20 50 100 kΩ CAN_TX
RL = 60 Ω (±1%);
C2 = 100 pF (±1%); 70%
TxDC - CANH,L VTXD – VDIFF = 0.5 V;
td,TXDC(dom-rec) Delay Time dominant TXDC rise time = 10 ns 0 - 140 ns -
- recessive (10% - 90%)
Guaranteed by bench
correlation

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Table 65. CAN transmit data input: Pin TxDC (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

RL = 60 Ω (±1%);
C2=100pF (±1%); 30%
TxDC - CANH,L VTXD – VDIFF = 0.9 V;
td,TXDC(rec-diff) Delay Time recessive TXDC fall time = 10ns 0 - 120 ns -
- dominant (90% - 10%)
Guaranteed by bench
correlation
TxDC dominant time-
tTXDC_DOM_TO - 0.8 2 5 ms -
out

Table 66. CAN transmit data output: Pin RxDC

Symbol Parameter Test condition Min Typ Max Unit Pin

Output voltage Active mode,

VRXDCLOW (0) 0.2 0.5 V CAN_RX
dominant level IRXDC = 2 mA
Output voltage Active mode, VDDIO- VDDIO
VRXDCHIGH VDDIO V CAN_RX
recessive level IRXDC = -2 mA 0.5 -0.2
CRX = 15 pF, 
30% – 70% VRXDC
tr, RXDC RxDC rise time 0 - 25 ns -
Guaranteed by bench
correlation
CRX = 15 pF, 
70% – 30% VRXDC
tf, RXDC RxDC fall time 0 - 25 ns -
Guaranteed by bench
correlation
CRX = 15 pF, 
CANH,L – RxDC VDIFF = 0.5V – 70%
td, RXDC Delay Time VRXDC 0 - 120 ns -
(dom-rec) dominant -
Guaranteed by bench
recessive
correlation
CANH,L – RxDC
CRX = 15 pF, 
td, RXDC Delay Time
VDIFF = 0.9 V – 30% 0 - 120 ns -
(rec - dom) recessive -
VRXDC
dominant

Table 67. CAN transmitter dominant output characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

Single Ended CANH

VTXDC = VTXDCLOW; 
VCANHdom voltage level in dominant 2.75 3.5 4.5 V -
RL = 50 Ω to 65 Ω;
state
Single Ended CANL
VTXDC = VTXDCLOW; 
VCANLdom voltage level in dominant 0.5 1.5 2.25 V -
RL = 50 Ω to 65 Ω;
state

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L9788 CAN FD interface

Table 67. CAN transmitter dominant output characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Differential output voltage

VTXDC = VTXDCLOW; 
VDIFF, dom in dominant state: 1.5 2.0 3 V -
RL = 50 Ω to 65 Ω;
VCANHdom-VCANLdom
Differential output voltage
in dominant state:
VTXDC = VTXDCLOW; 
VDIFF, dom_extR VCANHdom-VCANLdom 1.4 - 3.3 V -
RL = 45 Ω to 70 Ω;
at extended termination
resistor range
Differential output voltage
in dominant state: VTXDC = VTXDCLOW; 
VDIFF, dom_Arb 1.5 - 5 V -
VCANHdom-VCANLdom RL = 2240 Ω;
during arbitration
Measured over one 1 MHz
Driver Symmetry: period (1 µs)
VSYM = (VCANHdom + RL = 60 Ω (±1%) 
VSYM VCANLdom)/VDD_CAN 0.9 1 1.1 V -
fTXDC = 1MHz (square
VDD_CAN = 5V wave, 50% duty cycle); 
C1 = 4.7nF (±5%)
IOCANH, CANH output current in VTXDC = VTXDCLOW; 
-115 - mA -
dom (-3 V) dominant state VCANH = -3 V;
IOCANL, CANL output current in VTXDC = VTXDCLOW;
- - 115 mA -
dom (16 V) dominant state VCANL = 16 V;
VTXDC = VTXDCLOW;
IOCANH, CANH output current in
VCANH = 40 V;  0 - -5 mA -
dom (40 V) dominant state
Vs = 40 V
VTXDC = VTXDCLOW;
IOCANL, CANL output current in
VCANL = 40 V;  (0) - 115 mA -
dom (40 V) dominant state
Vs = 40 V

Table 68. CAN transmitter recessive output characteristics, normal mode

Symbol Parameter Test condition Min Typ Max Unit Pin

CANH voltage
level in recessive
VCANHrec VTXDC = VTXDCHIGH; No Load 2 2.5 3 V -
state (Normal
mode)
CANL voltage level
VCANLrec in recessive state VTXDC = VTXDCHiGH; No Load 2 2.5 3 V -
(Normal mode)
Differential output
voltage in
VDIFF, recOUT recessive state VTXDC = VTXDCHIGH; No Load -50 - 50 mV -
(Normal mode):
VCANHrec-VCANLrec

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CAN FD interface L9788

Table 69. CAN transmitter recessive output characteristics, low power mode, biasing active
Symbol Parameter Test condition Min Typ Max Unit Pin

CANH voltage level

VCANHrecLPbias 2 2.5 3 V -
in recessive state
CANL voltage level
VCANLrecLPbias 2 2.5 3 V -
in recessive state VTXDC = VTXDCHIGH; No Load
5.5 V ≤ VB_STBY ≤ 18 V
Differential output
voltage in recessive
VDIFF, recOUTLPbias -50 - 50 mV -
state 
VCANHrec-VCANLrec

Table 70. CAN transmitter recessive output characteristics, low-power mode, biasing inactive
Symbol Parameter Test condition Min Typ Max Unit Pin

CANH voltage level

VCANHrecLP VTXDC = VTXDCHiGH; No Load -0.1 0 0.1 V -
in recessive state
CANL voltage level
VCANLrecLP VTXDC = VTXDCHiGH; No Load -0.1 0 0.1 V -
in recessive state
Differential output
voltage in recessive
VDIFF, recOUTLP VTXDC = VTXDCHiGH; No Load -50 - 50 mV -
state VCANHrec -
VCANLrec

Table 71. CAN Receiver input characteristics during normal mode

Symbol Parameter Test condition Min Typ Max Unit Pin

Differential receiver threshold -12 V ≤ VCANH ≤ +12 V,

VTHdom (0.5) - 0.9 V -
voltage recessive to dominant state -12 V ≤ VCANL ≤ +12 V
Differential receiver threshold -12 V ≤ VCANH ≤ +12 V,
VTHrec 0.5 - (0.9) V -
voltage dominant to recessive state -12 V ≤ VCANL ≤ +12 V

Table 72. CAN Receiver input characteristics during low power mode, biasing active
Symbol Parameter Test condition Min Typ Max Unit Pin

Differential receiver
-12 V ≤ VCANH ≤ +12 V,
VTHdomLPbias threshold voltage recessive (0.5) - 0.9 V -
-12 V ≤ VCANL ≤ +12 V
to dominant state
Differential receiver
-12 V ≤ VCANH ≤ +12 V,
VTHrecLPbias threshold voltage dominant 0.5 - (0.9) V -
-12 V ≤ VCANL ≤ +12 V
to recessive state

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L9788 CAN FD interface

Table 73. CAN Receiver input characteristics during low power mode, biasing inactive
Symbol Parameter Test condition Min Typ Max Unit Pin

Differential receiver
-12 V ≤ VCANH ≤ +12 V,
VTHdomLP threshold voltage recessive (0.5) - 1.05 V -
-12 V ≤ VCANL ≤ +12 V
to dominant state
Differential receiver
-12 V ≤ VCANH ≤ +12 V,
VTHrecLP threshold voltage dominant 0.4 - (0.9) V -
-12 V ≤ VCANL ≤ +12 V
to recessive state

Table 74. CAN Receiver input resistance

Symbol Parameter Test condition Min Typ Max Unit Pin

Differential internal
Rdiff VTXDC = VTXDCHiGH; No Load 12 - 100 kΩ -
resistance
RCANH, Single Ended
VTXDC = VTXDCHiGH; No Load 6 - 50 kΩ -
CANL Internal resistance
Biasing active;
Internal Resistance
VTXDC=VTXDCHIGH; no load
mR matching -0.03 - 0.03 - -
R = 2 x (RCAN_H - RCAN_L) /
RCANH,CANL
(RCAN_H + RCAN_L)
Cin Internal capacitance Guaranteed by design - - 66 pF -
Differential internal
Cin, diff Guaranteed by design - - 33 pF -
capacitance

Table 75. CAN transceiver delay

Symbol Parameter Test Condition Min Typ Max Unit Pin

RL = 60 Ω (±1%); C2 = 100pF (±1%);

Loop delay TXDC to 30% VTXDC – 30% VRXDC;
tLOOP,hl - - 255 ns -
RXDC (High to Low) TXDC fall time = 10ns (90% - 10%);
CRX = 15 pF
RL = 60 Ω (±1%); C2 = 100pF (±1%);
Loop delay TXDC to 70% VTXD – 70% VRXD;
tLOOP,lh - - 255 ns -
RXDC (Low to High) TXDC fall time = 10ns (10% - 90%);
CRX = 15 pF
RL = 60 Ω (±1%); VDIFF: 0.5 V(falling) -
0.9 V(rising); C2 = 100pF (±1%);
CRX = 15 pF; TXD rise and fall time =
10 ns (10% - 90%, 90% - 10%);
Test signal to be applied on the TXD
TBit(RXD) Recessive bit symmetry input of the implementation is a square
745 1000 1255 ns -
≤ 1 Mb/s at RXDC wave signal with a positive duty cycle of
1/6 and a period of six times the
nominal recessive bit width.
Rectangular pulse signal TTXDC=
6000ns, high pulse 1000ns, low pulse
5000ns

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CAN FD interface L9788

Table 75. CAN transceiver delay (continued)

Symbol Parameter Test Condition Min Typ Max Unit Pin

Rectangular pulse signal TTXDC=

TBit(RXD) Recessive bit symmetry
3000ns, high pulse 500ns, low pulse 400 500 550 ns -
≤ 2Mb/s at RXDC
2500ns
Rectangular pulse signal
TBit(RXD) Recessive bit symmetry
TTXDC = 1200 ns, high pulse 200 ns, 120 200 220 ns -
≤ 5Mb/s at RXDC
low pulse 1000 ns
RL = 50 Ω to 65 Ω; 
VDIFF: 0.5 V(falling) - 0.9 V(rising); 
CL = 100 pF; CRXD = 15 pF;
TXD rise and fall time = 10 ns 
(10% - 90%, 90% - 10%);
Test signal to be applied on the TXD
TBit(BUS) Recessive bit symmetry
input of the implementation is a square 800 1000 1100 ns -
≤ 1Mb/s at CAN-Bus
wave signal with a positive duty cycle of
1/6 and a period of six times the
nominal recessive bit width
Rectangular pulse signal
TTXDC = 6000 ns, high pulse 1000 ns,
low pulse 5000 ns
Rectangular pulse signal
TBit(BUS) Recessive bit symmetry
TTXDC = 3000 ns, high pulse 500 ns, 435 500 530 ns -
≤ 2Mb/s at CAN-Bus
low pulse 2500 ns
Rectangular pulse signal
TBit(BUS) Recessive bit symmetry TTXDC = 1200 ns, high pulse 200 ns,
155 200 210 ns -
≤ 5Mb/s at CAN-Bus low pulse 1000 ns; Guaranteed by
bench correlation
Rectangular pulse signal
Receiver Timing
∆tREC ≤ TTXDC = 3000 ns, high pulse 500 ns,
Symmetry (TBit(RXD) - -65 - 40 ns -
2Mb/s low pulse 2500 ns; Guaranteed by
TBit(BUS))
bench correlation
Rectangular pulse signal
Receiver Timing
∆tREC ≤ TTXDC = 1200 ns, high pulse 200 ns,
Symmetry (TBit(RXD) - -45 - 15 ns -
5Mb/s low pulse 1000 ns; Guaranteed by
TBit(BUS))
bench correlation
CAN permanent
Tdom Guaranteed by scan 500 700 1000 µs -
dominant time-out
time between WUP(1)
on the CAN bus until
Wake-Up according to ISO11898-5 
RXD is active (i.e. the
tWUP-RXD RXD output enabled; Guaranteed by 0 - 1 ms -
CAN signal is
scan
represented at the RXD
output)
1. Time starts with the end of last dominant phase of the WUP.

160/264 DS12308 Rev 4

L9788 CAN FD interface

Table 76. Maximum leakage currents on CAN_H and CAN_L, unpowered

Symbol Parameter Test condition Min Typ Max Unit Pin

Unpowered device;
VCANH = 5V ; VCANL = 5 V;
ILeakage, Input leakage VDD_CAN, VB_STBY
-10 - 10 µA -
CANH current CANH connected via 0 Ω to GND
VDD_CAN, VB_STBY
connected via 47 kΩ to GND
Unpowered device;
VCANH = 5V ; VCANL = 5 V;
ILeakage, Input leakage VDD_CAN, VB_STBY
-10 - 10 µA -
CANL current CANL connected via 0 Ω to GND
VDD_CAN, VB_STBY
connected via 47 kΩ to GND

Table 77. Biasing control timings

Symbol Parameter Test condition Min Typ Max Unit Pin

tfilter CAN activity filter time Guaranteed by scan 0.5 1.8 µs

twake Wake-up time out Guaranteed by scan 0.35 1 5 ms
tSilence CAN timeout Guaranteed by scan 600 700 1200 ms
RL = 60 Ω (±1%); 
C2 = 100 pF (±1%);
C1 = 100 pF (±1%);
VTXDC = VTXDCLOW; 
tBIAS Bias Reaction Time - - 220 µs -
50% VDIFF; VSYM = 0.1(1);
Transition bias inactive to
bias active; Guaranteed by
scan
tcansuphigh CAN_SUP_LOW filter time Guaranteed by scan 8.5 10 11.5 µs -
tcansuplow VDD_CAN_OV filter time Guaranteed by scan 8.5 10 11.5 µs -
tdom_pulse Dominant interrupt pulse Guaranteed by scan 47.6 56 64.4 µs -
1. Measured from the start of a dominant-recessive-dominant sequence (each phase 6μs) until VSYM ≥ 0.1

Table 78. Standby current consumption (Battery line @RT)

Total quiescent current consumption(1) Max value Unit

EOT disabled and CAN block enabled, CAN wake up disabled 60 µA

EOT disabled and CAN block enabled, CAN wake up enabled 70 µA
EOT enabled and CAN block enabled, CAN wake up disabled 70 µA
EOT enabled and CAN block enabled, CAN wake up enabled 80 µA
1. L9788 Total quiescent current consumption at pins VB_STBY, VB_IN, VB_IN_SW, VB_SENSE, CP (through 100 nF
capacitor), VB_CAN, MRD, RLY1, LED2, STR2_DRN, PDR1_DRN connected to battery. The total current was measured
at battery line @RT.

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CAN FD interface L9788

Table 79. Standby current consumption (Battery line @HT)

Total quiescent current consumption(1) Max value Unit

EOT disabled and CAN block enabled, CAN wake up disabled 140 µA
1. L9788 Total quiescent current consumption at pins VB_STBY, VB_IN, VB_IN_SW, VB_SENSE, CP (through 100 nF
capacitor), VB_CAN, MRD, RLY1, LED2, STR2_DRN, PDR1_DRN connected to battery. The total current was measured
at battery line @HT.

Expected additional current due to bias ON is:

Table 80. can_auto_bias = 1 and can_wakeup_en = 1

- 27 °C, I(VB_STBY) 150 °C, I(VB_STBY)

TYP 548 µA 576 µA

MAX 650 µA 675 µA

Table 81. can_auto_bias = 1 and can_wakeup_en = 0

- 27 °C, I(VB_STBY) 150 °C, I(VB_STBY)

TYP 563 µA 591 µA

MAX 660 µA 690 µA

162/264 DS12308 Rev 4

L9788 LIN/K-LINE interface

13 LIN/K-LINE interface

13.1 Functional description

This interface is adapted to “LIN Specification Rev.2.1”, and it is also adapted to “K-LINE
Specification (ISO9141)”.
The Chip has over-voltage protection, loss of ground protection from -27 V to 40 V. -27 V
AMR is guaranteed at room & hot temperature. +40 V AMR is guaranteed in all temp
range.Short Circuit to Battery or Ground Protection is provided. If the bus line is short circuit
to battery, the over current protection is protected by current limitation function. Upon return
of connection, normal operation resumes without any intervention on the LIN bus line.
In case of power loss (VB_IN pin disconnected or power off) or ground loss (GND pin
disconnected) or LIN block in receive only mode (Transmition function disabled), the LIN
driver will not disturb the communication of the remaining transceivers connected to LIN or
KLINE bus. Upon return of connection, normal operation will resume without any
intervention on the LIN bus line.
LIN-TX is internally pulled up to internal 3.3 V.
All values in this section apply to the entire operating temperature and life of the U-chip.
The LIN block MAX baudrate is 20 Kbit/s.

Figure 71. Block diagram of LIN interface

LIN VB_IN
VBR
Dser_int V3V3A

1 kOhm 30 kOhm

LIN
-27 V LIN interface LIN_TX
LIN Spec rev 2.1, ISO9141
+27 V
short to VB protection
short to ground protection

PGND LIN_RX

GADG1212161148PS

13.2 LIN receive only mode

There is a MSC bit (LIN_TX_EN CONFIG-REG 11) to put the LINE block in receive only
mode (Transmition function disabled). Refer to reset matrix for the conditions to enter
receive only mode.

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LIN/K-LINE interface L9788

13.3 LIN thermal shut down

The LIN block has a dedicated thermal sensor to protect itself.
To protect LIN block from temperature overheat (high battery range of operation, soft short
conditions, etc.) a dedicated thermal sensor placed close to power mos is present in the
layout sensing FET temperature; one threshold is implemented (T_SD_H) with Hysteresis
(T_SD_hys). When the T_SD_H threshold is detected the Driver switches OFF. Once the
power stage has been switched-off for over-temperature detection, it will be able to switch
on again when temperature is decreased below thermal shut down threshold plus hysteresis
value to avoid high frequency on-off cycling.

13.4 LIN error handling

The Chip provides the following 3 error handling features which are not described in the
standard LIN Spec Rev2.1, but are realized in different stand alone LIN Interface /
microcontrollers to switch the application back to normal operation mode.
The error handling features can be disabled through the LIN_ERR_EN[2:0] (CONFIG-REG
11 D1~D3)bit.

13.4.1 LIN dominant TXD timeout

If TXDC is in dominant state (low) for t > t TXDC_DOM_TO=12ms(typ) the transmitter will
be disabled, status bit LIN_TXD_DOM (Upstream Bit Map Read15 frame 1) will be latched
and can be read and cleared by MSC. The transmitter remains disabled until the status
register is cleared or until the state returns recessive, according to MSC configuration bit
LIN_TX_DOM_ERR_CFG.

13.4.2 LIN permanent recessive

In case TXD changes to dominant (low level) state but RxD signal does not follow within
tLIN1: 40 us (typ), the transmitter is disabled. The status bit LIN_PERM_REC (Upstream Bit
Map Read15 frame 1) is latched and can be read and cleared by MSC. The transmitter
remains disabled until the status register is cleared.

13.4.3 LIN Permanent Dominant

In case the bus state is dominant (low level) for more than tLIN2: 12 ms (typ) a permanent
dominant status is detected. The status bit LIN_PERM_DOM (Upstream Bit Map Read15
frame 1) is latched and can be read and cleared by MSC. The transmitter is not switched off.

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L9788 LIN/K-LINE interface

Figure 72. LIN TimeOut function

1. LIN Permanent Recessive

4 After LIN_ERR status
bit is cleared, if LIN_TX
2 Even if LIN_TX is set to High, LIN_BUS be kept disable
is set to Low, the
continuation and LIN_ERR status bit is not cleared
dominant output of LIN
Bus will be corried out
LIN_TX normally

LIN bus disabled

LIN_RX

tLIN1
LIN_RX signal does not follow
within tLIN1 detect
LIN Error
status bit

Read Read Read

by SPI by SPI by SPI Cleared
by MSB
1 If LIN_RX is continuation of High fixed,
3 LIN_ERR status bit is cleared when LIN_TX is
LIN_ERR status bit is not cleared even if a
high and after a diagnosis is read by SPI
diagnosis is read by SPI

2. LIN Permanent Dominant

LIN_RX

LIN bus fixed to Dominant

LIN
tLIN2 LIN Permanent dominant staus Detect

Status bit
(LIN_ERR)

Read Read Read Cleared

by SPI by SPI by SPI by SPI
1 If LIN_RX is continuation of Low Fixed, 2 A status bit is cleared when LIN_RX is high
LIN_ERR status bit is not cleared even if a and after a diagnosis is read by SPI
diagnosis is read by SPI
GADG1212161201PS

Figure 73. LIN_TX input structure

Input structures: cascoding to

sustain battery level
V3V3
VHIGH V3V3

VLOW
GADG0912161539PS

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LIN/K-LINE interface L9788

Conditions:
7 V ≤ VB_IN ≤ 18 V, Tj -40 to 175 °C unless otherwise specified; VB_IN = 18 to 27 V,
Tj ≤ 50°C, all specs in limit. In the rest of supply range, parameters are degraded or reset.
If an ECU is not intended to transmit on the LIN bus (e.g. transmit input of a LIN transceiver
is recessive), the LIN driver will not drive the LIN bus to dominant state.If the LIN bus is in
recessive state, the LIN receiver output will provide a recessive state.

Table 82. Electrical characteristics of LIN interface

Symbol Parameter Test condition Min Typ Max Unit Pin

Input leakage
Ileak_lintx LIN_TX = VDDIO-1 V - - 10 µA LIN_Tx
current
HIGH_level Input
VIH_TX - 1.45 - 2 V LIN_Tx
voltage
LOW_level Input
VIL_TX - 0.9 - 1.4 V LIN_Tx
voltage
Input voltage
VHYS_TX - 0.1 - 0.4 V LIN_Tx
hysteresis

PULL_TX Pull-up resistance Lin_TX = 0 V 50 100 200 kΩ LIN_Tx

HIGH-level output VDDIO VDDIO

VOH_RX Isource = 2 mA - V LIN_Rx
voltage -0.6 -0.2
LOW-level output
VOL_RX Isink = 2 mA - 0.2 0.5 V LIN_Rx
voltage
LOW-level output Pull up =500 Ω, 0.2
VOL_LIN - - V LIN
voltage LIN_Tx = 0 V VB_IN
HIGH-level output Pull up =500 Ω, 0.8
VOH_LIN - VB_IN V LIN
voltage LIN_Tx = HIGH VB_IN
Dominant Source LIN_Tx = HIGH,
Ibus_dom -600 - 0 µA LIN
Current VB_IN = 12 V, LIN = 0 V
Resessive sink LIN_Tx=HIGH,VB_IN=8~1
Ibus_res 0 - 20 µA LIN
current 8V, LIN=8~18V,LIN≥VB_IN
VB_IN=8~18V,
Ibus_stby Standby current 0 - 20 µA LIN
LIN=8~18V,LIN≥VB_IN

IOVC Current limitation LIN=18V, LIN_Tx=0V 70 - 150 mA LIN

LIN bus to Ground

Rl-g_iso - 500K - - Ω LIN
isolation resistance
Ground loss VB_IN=12V, GND = Open,
ILK_NG1 -100 - 100 µA LIN
leakage current LIN=0~18V
VB_IN Loss VB_IN = Open,
ILK_NB1 -23 - 23 µA LIN
Leakage Current LIN = 0~18 V
TXDC dominant
t TXDC_DOM_TO - 9 12 15 ms LIN
time-out

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L9788 LIN/K-LINE interface

Table 82. Electrical characteristics of LIN interface (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

LIN permanent
tLIN1 (Time Out) - 30 40 50 µs LIN
recessive
LIN permanent
tLIN2 - 9 12 15 ms LIN
dominant
Input voltage for 0.4 LIN(Bus
ViD_LIN Application information - - V
dominant state VB_IN Receiver)
Input voltage for 0.4 0.45 0.5 LIN(Bus
Vth_DOM Application information V
dominant threshold VB_IN VB_IN VB_IN Receiver)
Input voltage for 0.6 LIN(Bus
ViR_LIN - - VB_IN V
recessive state VB_IN Receiver)
Input voltage for
0.5 0.55 0.6 LIN(Bus
Vth_REC recessive - V
VB_IN VB_IN VB_IN Receiver)
threshold
Vth_CNT = Input receiver
0.475 0.5 0.525 LIN(Bus
(Vth_REC + tolerance center - V
VB_IN VB_IN VB_IN Receiver)
Vth_DOM) / 2 voltage
Vth_HYS =
Input voltage 0.07 0.1 0.175 LIN(Bus
Vth_REC - - V
hysteresis voltage VB_IN VB_IN VB_IN Receiver)
Vth_DOM
Output delay time Cbus = 10 nF, LIN(Bus
tdly(LIN)HL - - 50 µs
HtoL Pull up = 500 Ω Receiver)
Output delay time Cbus = 10 nF, LIN(Bus
tdly(LIN)LH - - 50 µs
LtoH Pull up = 500 Ω Receiver)
Input delay time LIN(Bus
tDLY_HL CRXD=20pF - - 6 µs
HtoL Receiver)
Input delay time LIN(Bus
tDLY_LH CRXD=20pF - - 6 µs
LtoH Receiver)
LIN(Bus
tDLY Input delay time tDLY_HL- tDLY_LH -2 - 2 µs
Receiver)
Thresmax = 0.744VB_IN,
Thdommax = 0.581VB_IN,
LIN(Bus
D1 Duty Cycle VB_IN = 7-18 V, 0.396 - - -
Receiver)
tbit = 50 µs,
D1 = tbus_resmin/(2xtbit)
Thresmin = 0.422VB_IN,
Thdommin = 0.284VB_IN,
LIN(Bus
D2 Duty Cycle VB_IN = 7.6-18V, - - 0.581 -
Receiver)
tbit = 50 µs,
D2 = tbus_resmax/(2xtbit)
Thresmax = 0.778VB_IN,
Thdommax = 0.616VB_IN,
LIN(Bus
D3 Duty Cycle VB_IN = 7-18 V, 0.417 - - -
Receiver)
tbit = 96 µs,
d3 = tbus_resmin/(2xtbit)

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LIN/K-LINE interface L9788

Table 82. Electrical characteristics of LIN interface (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Thresmin = 0.389 VB_IN,

Thdommin = 0.251 VB_IN,
LIN(Bus
D4 Duty Cycle VB_IN = 7.6-18 V, - - 0.59
Receiver)
tbit=96µs,
D4 = tbus_resmax/(2xtbit)
Cbus = 2.2nF, Rbus = 1kΩ, V/ LIN(Bus
trise_LIN Slew Rate(LIN) 1 2 3
40-60%,VB_IN=13.5V µs Receiver)
Cbus = 2.2nF, Rbus = 1kΩ, V/ LIN(Bus
Tfall_LIN Slew Rate(LIN) 0.8 2 3
40-60%,VB_IN=13.5V µs Receiver)
Cbus = 7.2 nF + 2 nF,
Slew V/ LIN(Bus
trise_K_LINE Rbus = 510 Ω, 1.2 - 5
Rate(K_LINE) µs Receiver)
20-80%,VB_IN = 18 V
Cbus = 7.2 nF + 2 nF,
Slew V/ LIN(Bus
Tfall_K_LINE Rbus = 510 Ω, 1.2 - 11
Rate(K_LINE) µs Receiver)
20-80%,VB_IN = 18 V
Temperature shut
T_SD_HIGH - 185 - 200 °C LIN
down
Temperature shut
T_SD_LOW - 175 - 190 °C LIN
down recover
Temperature shut
T_SD_hys - 5 - 10 °C LIN
down hysteresis
Thermal shutdown
- Guaranteed by design 1.5 - 4 µs LIN
analog filter time
Digital deglitch
filter time on
- Guaranteed by scan - 10 - µs LIN
Temperature shut
down detection

Rslave(1) - - 20 30 60 kΩ LIN

Diode drop + pull-

VserDiode(1) Ibias = 10 µA 0.4 0.7 1.0 V LIN
up resistor drop
Ibias= 550 µA
VserDiode_drop Diode drop 0.4 0.7 1.0 V LIN
Guaranteed by design
LINIO input
CLINIO Guaranteed by design - - 25 pF LIN
capacitance
1. LIN Physical Layer Spec Revision 2.1 November 24, 2006; Page 119

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L9788 LIN/K-LINE interface

13.4.4 Timing diagram

Figure 74. LIN transmission timing chart

1.45 V
LIN_TX 1.4 V

0.8VB

LIN 0.2VB

tdly(LIN)HL tdly(LIN)LH

GADG1212161503PS

Figure 75. LIN reception timing chart

Vth_HYS(LIN)

VTH_Rec
LIN VTH_DOM

50% 50%
LIN_RX

tDLY_HL tDLY_LH

GADG1212161507PS

Figure 76. LIN duty cycle timing chart

tbus_dom(max) tbus_rec(min)

Threc(max)

Thdom(max)

LIN
Threc(min)

Thdom(min)

tbus_dom(min) tbus_rec(max)
GADG1212161510PS

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LIN/K-LINE interface L9788

Figure 77. LIN slew rate timing chart

tfall_60% tfall_40% trise_40% trise_60%

Vswing

60%
LIN
40%

|dv/dt|fall = 0.2Vswing / (Tfall_40% - tfall_60%)

|dv/dt|rise = 0.2Vswing / (Trise_60% - trise_40%)
GADG1212161516PS

Figure 78. Test circuit for measurement of slew rate

V3VA
VB

Rbus 100 kOhm

LIN LIN_TX
Cbus

LIN_RX

20 pF

GADG1212161520PS

170/264 DS12308 Rev 4

L9788 Built in self test

14 Built in self test

14.1 Power supply independency and voltage monitors

In order to guarantee independence between monitor functions of the L9788 and monitored
functions of the same L9788 two independent band-gap references are used; a simple field
of application of this concept is the under/over voltage detection of MCU power supply
generated by the same L9788.
The basic schematic of the band-gap used to generate the main function and of the band-
gap used to monitor it, including their own supply architecture, is shown in Figure 79.
Two band-gaps VBG1 and VBG2 are generated starting from protected battery line: VBG1
is used as reference voltage to generate internal analog and digital supply lines and to
generate external power supply voltages; VBG2 is used as reference for the uv/ov monitors
of these supplies.
The concept to guarantee independence between the two references is that both of them
have independent supply and ground architectures to ensure that a single point failure in
one of the two structures will not affect the other; independence is achieved by means of
physical isolation between the two band-gaps and their supply circuits (A and B areas),
isolation is done layouting the circuits in different floor plan areas and by usage of deep
trench isolation in between.

Figure 79. Band-gap supply architecture

VChargePump

VBatt

V3V3PRE_mon V3V3PRE

+ +
- -
VDD2V7 VDD2V7 VINT3V3 VINT3V3 V3V3PRE V3V3PRE_mon
monitor monitor monitor monitor
VDD2V7

VINT3V3
VBG2 VBG1
(monitor) (reference)

GND_DIG
GND_ANA_2 GND_ANA_1 ANALOG blocks DIGITAL blocks

GADG1212161531PS

A cross-referenced monitor is used to detect eventual failures in any of the band-gap supply
and enter a safe state: VBG1 is used as reference for the monitor of the supply of VBG2 and
VBG2 is used as monitor of the supply of VBG1.
The concept is needed to solve dependencies of band-gap voltage from the supply line: let
us suppose that V3V3PRE_mon in the above picture has a fault impacting VBG2 voltage
reference, since V3V3PRE_mon is also the supply for monitor circuits a failure in this region

DS12308 Rev 4 171/264

263
Built in self test L9788

will cause the loss of monitor functionality with an undetected latent fault; the insertion of a
monitor supplied from V3V3PRE and referenced to VBG1 allows the detection of this latent.
The same concept applies on the vice-versa.
The remaining common points of the internal architecture can be summarized as:
 protected battery line,
 charge pump supply,
 V3V3PRE_mon monitor input (netA),
 V3V3PRE monitor input (netB)
The above points can be tolerated because:
 Protected battery line is the main supply of the L9788, used to generate supply for
analog and digital core. All the circuits connected to this rail are capable of high voltage
operation, in case the connection is lost no logic supply can be generated and the
device will be stuck in reset condition.
 Charge pump is used to guarantee proper functionality during battery cranking only
and is useless in normal mode. All the circuits connected to this line are capable of high
voltage, in case the line is open it can be detected by dedicated monitor (not shown
here) during normal operation or at power-up of the device.
 In case netA is shorted to ground there is fault detection while short to supply line is
normal condition, short to VBG1 through V3V3PRE_mon monitor inputs is not possible
since the inputs are cascaded; in case a double fault is present (shorted cascade) it will
cause an increase in analog and digital supply lines (VINT3V3 and VDD2V7) detected
by their monitors using VBG2 reference and triggering safety switch-off path for safety
relevant outputs.
 In case netB is shorted to ground there is fault detection while short to supply line is
normal condition, short to VBG2 through V3V3PRE monitor inputs is not possible since
the inputs are cascaded; in case a double fault is present (shorted cascade) it will
cause a failure on the monitor circuit only, without affecting normal functionality until a
third fault occurs.

14.2 Analog comparators BIST

For all the safety relevant monitors a self test is implemented to verify that the comparator
can detect a variation of the monitored signal applied at its input. The basic implementation
scheme is shown in Figure 80: comparator inputs are choppered by a diagnostic clock and
the output of the comparator is xored with diagnostic clock itself: if the comparator is not
able to toggle due to fault condition (internal or external) its output will start toggling
following diagnostic clock and causing a self test failure.

172/264 DS12308 Rev 4

L9788 Built in self test

Figure 80. Analog bist implementation

V+ VB

Control

+ V3V_PRE (VBG1)

V3VA
- V3VD

+
- VBG2

OV_FLT

+
-
UV_FLT

BG_READY
BIST_EN

Primary Secondary

GADG1212161540PS

The analog bist is applied to the following analog comparators:

V3V3A_OV, V3V3A_UV, V3V3D_OV, V3V3D_UV (internal supply monitors) VDD5_OV,
VDD5_UV (VDD5 monitors)
The bist is run on MSC command BIST_EN. The result is read and clear by MSC.
 On driver section BIST is implemented for diagnostic of main outputs:
 OVC, OPL, STG comparators (injectors)
 STG comparator (igniter)
 The bist is run on MSC command. The result is read and cleared by MSC.

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Stand-by memory L9788

15 Stand-by memory

This memory is a general purpose memory registers array for microcontroller-data which is
supposed to be saved during standby when ECU is switched off. Intention is to reduce the
number of write cycles in microcontroller-flash.
In case of standby-power-supply failure the data is no longer valid. This condition can be
detected reading flag VB_STBY_UV MSC_READ13.FRAME2[0].
As long as the standby-power-supply is valid, no data is lost.
There are 15 memory-registers which can be used for application data. The 16th register is
an address-register which cannot be used for application data.
Before writing application data into one of the memory-registers, the address of the
memory-register must be written into the address-register with the STBY_NVM_ADD_REG
command.
After setting the address a STBY_NVM_ADD_REG command can write the corresponding
array byte.
Using the STBY_NVM_ADD_REG command and thus updating the address-register is not
necessary in case the previously written address is still correct, e.g. when application writes
consecutively to the same register.
The memory-register-addresses can have values from 0 to 14. Value 15 is not used for write
commands. This means STBY_NVM_ADD_REG commands will have no effect when
writing to address 15.
The application data is written with mentioned STBY_NVM_ADD_REG command which
writes one byte (8bit) of application data into the memory-register. To write more than one
register, STBY_NVM_ADD_REG and STBY_NVM_ADD_REG sequences are necessary.
As the other registers above, the upstream reading of the registers is not done register-wise
but in blocks of four registers. MEM_REG1 … 4, MEM_REG5 … 8, MEM_REG9 … 12 and
MEM_REG13 … 15 are grouped in the four upstream blocks of Read16.
The address-register MEM_ADR_REG16 is located at the end of the memory and is the
16th register. As mentioned, it cannot be used for application data. It is the fourth byte of the
upstream Read16 and can be read back with a read command for this block.
Before upstream-reading, the register-address must be set with the
STBY_NVM_ADD_REG command. If the previously written address is already the correct
one, the STBY_NVM_ADD_REG command is not necessary.
For upstream reading of the MEM_REGx and MEM_ADR_REG16 registers, the command
RD_COMMAND16 is used. The RD_COMMAND16 command is the same for all four
upstream blocks as the block to be read is defined via the address-register. The read-
command will not only read the addressed register, but will read the complete four-byte
upstream-block which contains the addressed register.
The STBY_NVM_ADD_REG command allows to write a MEM_VALID bit (D6) that can be
set to 1 by the microcontroller to signal that the memory has been written and validated
reading back data. If standby-power-supply is removed MEM_VALID bit is reset.

174/264 DS12308 Rev 4

L9788 DAC

16 DAC

Device integrates a 2-bit DAC, with 4 possible output voltages between 0V and VDD5_IN.
The selected level is determined by 2 bits DAC[0:1] into CONFIG_REG_7.
Conditions:
5.5 V ≤ VB_IN ≤ 18 V, 4.75 V ≤ VDD_IO ≤ 5.25 V, Tj -40 to 175 °C unless otherwise
specified.

Table 83. DAC electrical parameters

Symbol Parameter Test condition Min Typ Max Unit Pin

V00 Output voltage 00 - 0.7 1 V AD_TEST

V01 Output voltage 01 - 1.5 1.8 V AD_TEST
V10 Output voltage 10 - 2.2 2.8 V AD_TEST
V11 Output voltage 11 - 3.6 4.7 V AD_TEST
Transition from 00 to
trise Rising time - - 10 µs AD_TEST
11 10%-90% open
Transition from 11 to
tfall Falling time - - 10 µs AD_TEST
00 90%-10% open

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263
ADC L9788

17 ADC

A 10-bit ADC converter is integrated into the device in order to give information about silicon
temperature.
A 10-bit conversion can be read with READ_COMMAND12 MSC frame. Conversion
formula is T=MSCcode*290/1024 - 63 (°C).
Conditions:
5.5 V ≤ VB_IN ≤ 18 V, 4.75 V ≤ VDD_IO ≤ 5.25 V, Tj -40 to 175 °C unless otherwise
specified.

Table 84. ADC electrical parameters

Symbol Parameter Test condition Min Typ Max Unit Pin

Guaranteed by
ADC_bits ADC effective number of bits - 10 - - -
design
Guaranteed by
Trange Internal junction temperature range -50 - 200 °C -
design
Guaranteed by
Tacc Temperature accuracy -10 - 10 °C -
design

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L9788 Micro second channel (MSC) interface

18 Micro second channel (MSC) interface

18.1 Function description

The Micro Second Channel interface is an adapted high performance serial bus for power
switch device.
L9788 has one Micro Second Channel slave controller capable of receiving up to 35 MHz
downstream and transmitting up to 2.18 MBaud upstream.
MSC Clock is supported with synchronous continuous mode. Master clock and data are
implemented by LVDS. Slave data out signal is implemented by LVTTL.

Figure 81. MSC communication timing diagram

tCK
tCKhigh tCKlow
MSC_CK

tswitch t
tsetup thold
MSC_DI tENsetup

t
tENhold
MSC_EN

Active phase Passive phase Active phase

t
tSDOdelay
MSC_DO

t
GADG1212161611PS

Conditions:
5.5 V ≤ VB_IN ≤ 18 V, 4.75 V ≤ VDD_IO ≤ 5.25 V, Tj -40 to 175 °C unless otherwise
specified.

Table 85. MSC communication timing parameters

Symbol Parameter Test condition Min Typ Max Unit Pin

tCK Cycle time Tested by SCAN/ 25 - - ns -

tsetup Data setup time Tested by SCAN/ 5 - - ns -
thold Data hold time Tested by SCAN/ 5 - - ns -
Switching time switching time
for CL, EN and SI measured
tswitch Tested by SCAN/ - - 3 ns -
between 0.1*VVDD3 and
0.9*VVDD3
tCKlow CK low time Tested by SCAN/ 7.5 - - ns -
tCKhigh CK high time Tested by SCAN/ 7.5 - - ns -

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Micro second channel (MSC) interface L9788

Table 85. MSC communication timing parameters (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

EN setup time (i.e. time

tENsetup between falling edge of EN and Tested by SCAN/ 5 - - ns -
next falling edge of CK)
EN hold time (i.e. time between
tENhold falling edge of CK and next Tested by SCAN/ 5 - - ns -
rising edge of EN)

Data out cycle time F_DO_SEL 128

(CONFIG_REG2 [1:2]) = “11” 64
tSDO /tCK Tested by SCAN/ - - - -
F_DO_SEL = “10” F_DO_SEL 32
= “01” F_DO_SEL = “00” 16
Clock range at CK as long as
there is a clock at pins
Tested by SCAN/ - - 35 MHz -
MSC_CK_P,
MSC_CK_N. tCPP ≥ 2 * tCL
fCK
Clock range at CK as long as
there is a clock at pins
Tested by SCAN/ - - 40 MHz -
MSC_CK_P, 
MSC_CK_N. tCPP ≥ 4 * tCL
- tSDOdelay Tested by SCAN/ - - 160 ns -

The MSC is used to receive the input command and data from CPU and to transmit an
output data to CPU. Four signals are used according to the timing chart of Figure 81:
EN: Bus Enable
There is one input for chip select at pin [EN] This signal is LVTTL Interface from Master to
Slave. MSC uses inverted polarity for EN: a logic '1' is a 'passive level' and a logic '0' is a
'active level'. It is possible to drive multiple power devices with shared CL and DI lines and
individual EN signal.
CL: Synchronous Serial Clock
The clock pins are [CLP] and [CLN], the differential clock. [CLP]-[CLN] is referred to as CL.
The maximum downstream clock rate is CL= 35 MHz.There is an internal resistor between
pins [CLP] and [CLN].This signals are LVDS Interface from Master to Slave.
DI: Serial Input Data
Differential inputs for downstream data are pins [DIP] and [DIN]; the differential input signal
[DIP]-[DIN] is referred to as DI. There is an internal resistor between pins [DIPP] and [DIN].
These signals are LVDS Interface from Master to Slave
DO: Serial Output Data
There is one push-pull output for upstream data at pin [DO]. Upstream is done with a lower
clock rate fDO, selectable by the microcontroller; after a reset the upstream clock rate is fDO
= fCL/32.The upstream clock is synchronous with CL since it is derived from a clock
divider.Therefore the CL signal must be always running independently whether a
downstream transmission is running or not.This signal is LVTTL Interface from Slave to
Master.

178/264 DS12308 Rev 4

L9788 Micro second channel (MSC) interface

Figure 82. Communication diagram between µC and U-CHIP

μC U-chip
EN

CLP

CLN

DIP
Downstream Divider
DIN

Upstream
DO

GADG1312161115PS

Figure 83. MSC voltage levels diagram

MSC_CK_P
MSC_DI_N
1.6 V

1.2 V

0.8 V

t
MSC_CK_P
MSC_DI_N
1.6 V

1.2 V

0.8 V

MSC_CK = MSC_CK_P - MSC_CK_N

MSC_DI = MSC_DI_P - MSC_DI_N
MSC_CK
MSC_DI +450 mV
‘1’
+150 mV
100 mV

-100 mV t

‘0’

GADG1312161143PS

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Micro second channel (MSC) interface L9788

Conditions:
5.5 V ≤ VB_IN ≤ 18 V, 4.75 V ≤ VDD_IO ≤ 5.25 V, Tj -40 to 175 °C unless otherwise
specified.

Table 86. MSC electrical characteristics

Symbol Parameter Test condition Min Typ Max Unit Pin

Not to be tested. It is MSC_CK_P

VCK_P,VCK_N Input voltage range 0.8 - 1.6 V
an application note. MSC_CK_N
Differential input voltage
Not to be tested. It is MSC_CK_P
VCKdiff VCKdiff =|VCK_P – 150 - 450 mV
an application note. MSC_CK_N
VCK_N|
Input voltage offset
Not to be tested. It is MSC_CK_P
VCKoff VCKoff =0.5*(VCK_P + 1 - 1.4 V
an application note. MSC_CK_N
VCK_N)
EXTERNAL Resistor
Not to be tested. It is MSC_CK_P
Rck between CK_P and 100 - Ω
an application note. MSC_CK_N
CK_N
MSC_CK_P
Rpu_N Internal pull-up resistor - 100 200 400 kΩ
MSC_CK_N
Internal pulldown MSC_CK_P
Rpd_P - 100 200 400 kΩ
resistor MSC_CK_N
Differential input high
detection level
MSC_CK_P
VCK_high VCK_high= - - - 100 mV
MSC_CK_N
VCK_P_high –
VCK_N_high
Differential input low
detection level MSC_CK_P
VCK_low - -100 - - mV
VCK_low= VCK_P_low MSC_CK_N
– VCK_N_low
Not to be tested. It is MSC_DI_P
VDI+,VDI- Input voltage range 0.8 - 1.6 V
an application note. MSC_DI_N
Differential input voltage Not to be tested. It is MSC_DI_P
VDIdiff 150 - 450 mV
VDIdiff =|VDI_P-VDI_N| an application note. MSC_DI_N
Input voltage offset
Not to be tested. It is MSC_DI_P
VDIoff VDIoff =0.5*(VDI_P 1 - 1.4 V
an application note. MSC_DI_N
+VDI_N)
Resistor between DI_P Not to be tested. It is MSC_DI_P
Rcl - 100 - Ω
and DI_N an application note. MSC_DI_N
MSC_DI_P
Rpu_N Internal pull-up resistor - 100 200 400 kΩ
MSC_DI_N
Internal pulldown MSC_DI_P
Rpd_P - 100 200 400 kΩ
resistor MSC_DI_N
Differential input high
detection level MSC_DI_P
VDI_high - - - 100 mV
VDI_high= VDI_P_high- MSC_DI_N
VDI_N_high

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L9788 Micro second channel (MSC) interface

Table 86. MSC electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit Pin

Differential input low

detection level MSC_DI_P
VDI_low - -100 - - mV
VDI_low= VDI_P_low- MSC_DI_N
VDI_N_low
VDDIO=5V or 3.3V
VDO_L DO output low level - - 0.5 V MSC_DO
Isink current=2mA
VDDIO =5V or 3.3V VDDIO
VDO_H DO output high level - - V MSC_DO
Isink current=2mA -0.5
fDO Maximum frequency Tested by SCAN fCK/128 fCK/64 fCK/16 MHz MSC_DO
ENL Low input level - -0.3 - 1.1 V MSC_EN
VDD5
ENH High input level - 2.3 - V MSC_EN
+0.3
VHYST Hysteresis - 0.1 - V MSC_EN
IIN Input current - - 32 μA MSC_EN
RPU Pull up resistor - 50 - 250 kΩ MSC_EN

18.2 Downstream communication

The enable input is active with inverted polarity - i.e. ‘low level' during the active phases of
command or data frames. An active enable signal validates the DI input signal. Outside the
active phase (enable line is at high level) invalid data may occur at DI. The active phase of a
downstream frame starts with the falling edge of the enable signal and ends with the rising
edge of the enable signal. The enable signal changes its state with the rising edge of the
clock CL. DI changes its state on rising edge and it is latched by L9788 on the falling edge of
CL. Downstream frames are synchronous serial frames. They support enable signal and
command/data selection bit as part of the frame. Command/data selection bit allows
distinguishing frames as command and data frames in the receiver circuit. Command
frames and data frames may be sent in any sequence with a passive phase of at least 2 CL-
cycles after each frame.

18.2.1 Command frame

A command frame always starts with a high level bit (command selection bit). The number
of the command bit of the active phase of a command frame NCB is fixed to 16. If the
number of the command bit is not equal to NCB = 16 the frame will be ignored, the
command will not be executed and the error flag (TRANS_L) will be set. If the MSC
command frame has an invalid command the flag "CMD_ERROR" is set but no action on
outputs is taken. The command frame is ignored.
The length of the command frame's passive phase tCPP must be a minimum of 2 * tCL.

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263
Micro second channel (MSC) interface L9788

Figure 84. MSC Command Frame bit stream

Downstream Command Frame (16 bits) tCPP

Address field (7 bits) Data field (8 bits)

INVALID CMD A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 INVALID

LSB MSB LSB MSB
MSC_EN Active level

GADG1312161204PS

Table 87. MSC Interface command frame

bit Description

0 =’1’: command selection bit

1-7 Command. LSB first!
8-15 Data for the command. LSB first!

18.2.2 Data frame

A data frame always starts with a low level bit (data selection bit). The number of the data bit
of the active phase of a data frame NDB is fixed to 31 bits:
If the number of the data bit is not equal to NDB = 31 the frame will be ignored and the error
flag (TRANS_L) will be set, but no action on outputs is taken.
The length of the data frame's passive phase tCPP must be a minimum of 2 * tCL.

Figure 85. MSC Data Frame bit stream

Downstream Data Frame (32 bits) tCPP

Data field (31 bits)

CMD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D30 INVALID

LSB MSB
Active level

GADG2112161207PS

Content of DATA frame (transmitted LSB first)

182/264 DS12308 Rev 4

L9788 Micro second channel (MSC) interface

Table 88. MSC Interface Data frame

bit Description

0 =’0’:DATA selection bit

1-31 D0-D30 CONTROL REGISTER LSB first!

Table 89. Control register

Control Register

D0 D1 D2 D3 D4 D5 D6 D7

LSD-INJ1 LSD-INJ2 LSD-INJ3 LSD-INJ4 LSD-O2H1 - LSD-O2H2 -

D8 D9 D10 D11 D12 D13 D14 D15

LSD-SOL1 LSD-SOL2 LSD-LED1 LSD-LED2 LSD-RLY1 LSD-RLY2 LSD-RLY3 LSD-RLY4

D16 D17 D18 D19 D20 D21 D22 D23

LSD-HSD- LSD-HSD- LSD-HSD-

LSD-RLY5 FET-PRD1 FET-PRD2 FET-PRD3 FET-PRD4
STR1 STR2 STR3

D24 D25 D26 D27 D28 D29 D30 -

FET-PRD5 IGN1 IGN2 IGN3 IGN4 IGN5 IGN6 -

Note: If RLY4, STR2, STR3 are not configured as starter their status is controlled by the data in
control register.
If they are configured as starter their status is controlled by MSC dedicated command.

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Micro second channel (MSC) interface L9788

18.3 Upstream communication

The serial data output [DO] is the synchronous serial data signal of the upstream channel.
The polarity for [DO] is ‚normal polarity'- i.e. a low level bit at [DO] is stored in the µC as a
logic ‚0', and a high level bit at [DO] is stored in the µC as a logic ‚1'. The serial data output
is single-ended.
The frequency is derived from fCL by an internal divider to typ. fDO = fCL/32. It can be
adjusted via MSC to fDO = fCL/16... fCL/128. The time for a bit is TSDO = 1/fDO.
Each upstream frame consists of 16 bit:
 1 start bit, always '0'
 4-bit-upstream address field (A[0..3] with LSB first)
 8 bit data upstream data field (D[0..7] with LSB first)
 1 upstream parity bit (with even parity for the complete data frame)
 2 fDO stop bit, always '1'.
There are 16 commands to perform read accesses.
All the read command READ-N Upstream Block are composed of 4 continued frames sent
to µC.
Within the execution of these read commands an upstream data frame is sent after the 2
stop bits of the prior upstream data frame and one additional interframe bit waiting time. If a
new read command is received while the up-stream communication is active, the 16 bit up-
stream on-going is completed and the new read command is canceled. At the end of the
upstream frame the latched flags contained in the register are cleared automatically, if the
frame is interrupted by new read command, flags will not be cleared. The time from the read
command to the first upstream frame of the answer is less than 100 µs.
Outside the upstream frame the DO output is high impedance

Figure 86. MSC upstream

INTERFRAME
PARITY BIT
Total up stream frame field (16 bits) Next up stream frame (16 bits)
Stop
Up stream Frame (14 bits) bits

Address Data field (8 bits)

Start Start
bit A A A A D D D D D D D D PB S S bit A A A A D D
LS MSB LS MS MSB
Active level

GADG1312161239PS

184/264 DS12308 Rev 4

L9788 Micro second channel (MSC) interface

Figure 87. MSC upstream commands example

Read command 1: 1-101010-101010101
Read command 2: 1-101010-010101010
Read command 3: 1-010101-011001100

C0-C5 D0-D8 => read frames data

Interframe

16 16 Frames + end

Down stream Read

Up stream

First Last
frame frame

End Frame1 = 0-0101-10101010-Pb-

End Frame2 = 0-0101-01010101-Pb-
End Frame3 = 0-1010-01100110-Pb-
End Frame4 = 0-1010-11010101-Pb-
End Frame5 = 0-0010-01110111-Pb-
End Frame6 = 0-0010-10101110-Pb-

Inverted read C0-C3 bits Read D0-D8 bits

GADG1312161244PS

18.4 Micro Second Channel activity watchdog

MSC data frames are monitored to be sent in intervals shorter than tMSC_mon. If L9788
receives no valid data frame for longer than tMSC_mon, it will switch off all the drivers,
removing driver enable command, and the error flag (TRANS_F) is set to 1 and internal
signal "OUT_DIS" will be set to "0". Note: OUT_DIS = driver_en (Read11 frame 1);
tMSC_mon is the time needed to send OUT_DIS, it is different from time needed to turn off
drivers (which can be different depending on driver type, the maximum time to turn off all
drivers is about 300 µs).
To enable again the outputs, the µC has to read the TRANS_F and then send the command
Enable_Driver, and then outputs are reactivated with the first correct data frame. If the fault
flag is not cleared the Enable_Driver command is ignored.
By default the Micro Second Channel activity watch dog is enabled and the monitoring time
will start after writing of the internal signal OUT_DIS bit by Enable_Driver command. Each
time L9788 receives a valid data frame the tMSC_on timer is reset. This means that micro
controller can drive the outputs only when the monitoring module is active.
It is also possible to enable /disable the Micro Second Channel activity watch dog through
MSC_ACT_EN bit (CONFIG_REG2 D0), 0= disable and 1 = enable (reset value).

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Micro second channel (MSC) interface L9788

Figure 88. MSC activity watchdog time diagram

Control reg. write CMD READ Control reg. write

Driver enable Control reg. write Driver enable

Down stream CMD CMD

Up stream

1 = enable
Out_Dis_bit 0 = disable
internal signal

timeout
tMSC_mon
Timer Counter

TRANS_F

GADG1312161256PS

Table 90. MSC Interface Micro Second Channel activity watchdog

Parameter min typ max unit

tMSC_mon 100 142 185 µs

186/264 DS12308 Rev 4

 18.5 Downstream frame Bit Map

L9788
MSC Interface DOWN STREAM FRAME Bit Map

Table 91. MSC Interface DOWN STREAM FRAME Bit Map

ADDRESS DATA

C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

RD_COMMAND1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
RD_COMMAND2 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
RD_COMMAND3 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1
RD_COMMAND4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
RD_COMMAND5 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1
RD_COMMAND6 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0
DS12308 Rev 4

RD_COMMAND7 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1
RD_COMMAND8 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0
RD_COMMAND9 1 0 1 0 1 0 1 1 1 1 0 1 1 1 0
RD_COMMAND10 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1
RD_COMMAND11 0 1 0 1 0 1 0 1 1 1 0 1 1 1 0

Micro second channel (MSC) interface

RD_COMMAND12 0 1 0 1 0 1 0 0 0 0 1 0 0 0 1
RD_COMMAND13 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1
RD_COMMAND14 1 0 1 0 1 0 1 1 0 0 0 1 0 0 0
RD_COMMAND15 0 1 0 1 0 1 0 0 1 1 1 0 1 1 1
RD_COMMAND16 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0
PHOLD_ LED1_PD LED2_PD BOOST_ WAKE_UP_TIMER_S
CONFIG-REG 1 0 0 1 1 1 1 1 PHOLD_TIME[0:1]
EN _EN _EN EN TART_STOP[0:1]
IGN_CUR
MSC_AC VRS_MO IGN_DIA IPUPD_E IPUPD_M
CONFIG-REG 2 0 1 1 1 1 0 1 F_DO_SEL[0:1] RENT_CF
T_EN DE_SEL G N ODE
G
187/264
 Table 91. MSC Interface DOWN STREAM FRAME Bit Map (continued)
188/264

Micro second channel (MSC) interface

ADDRESS DATA

C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

RLY4_DL LSD/HSD LSD/HSD LSD/HSD

CONFIG-REG 3 1 1 1 1 0 0 1 Y_OFF_E _DRV1- _DRV2- _DRV3- SRT2_EN STR3_EN T_SEO_DELAY[0:1]
N CFG CFG CFG
CONFIG-REG 4 1 1 0 0 0 0 1 PRD1_IDRV[0:1] PRD2_IDRV[0:1] PRD3_IDRV[0:1] PRD4_IDRV[0:1]
CONFIG-REG 5 0 0 0 0 1 1 1 PRD5_IDRV[0:1] PRD1_VDS[0:2] PRD2_VDS[0:2]
EOT_MO IGN_LSD
CONFIG-REG 6 1 1 0 0 1 1 1 PRD3_VDS[0:2] PRD4_VDS[0:2]
DE _DIS
TRK_EN[ TRK_EN[ TRK_EN[
CONFIG-REG 7 0 0 1 1 0 0 1 PRD5_VDS[0:2] DAC[0:1]
1] 2] 3]
VRS EN_FALLI HYS_FB_
CONFIG-REG 8 1 0 1 1 0 1 1 VRS _MODE[0:1] VRS _HYS2[0:2]
_DIAG NG_FILT SEL
DS12308 Rev 4

CONFIG-REG 9-0 0 1 0 0 1 0 1 0 1 WDA_RESPTIME[0:5]

WDA_WI WDA_INI
CONFIG-REG 9-1 0 1 0 0 1 0 1 1 0
N_SEL T
CONFIG-REG 10 0 0 0 1 1 0 1 WDA_RESP[0:7]
LIN_TX_
LIN/KLIN LIN_ERR LIN_ERR LIN_ERR LIN_TX_E DIS_FOR VDD5_OF O2H2_O
CONFIG-REG 11 0 1 1 0 1 1 1
E SEL _EN[0] _EN[1] _EN[2] N _WDA_E F_SEL C_FLT
RR
VB_IN_O VDD5_O WAKE_U WAKE_U
TNL_RST O2H1_O FILTER_ WK_IN_R
CONFIG-REG 12 1 0 0 1 0 0 1 V_RST_E V_RST_E P_CAN_R P_EOT_R
_EN C_FLT MODE ST
N N ST ST
IPUPD_E IPUPD_E IPUPD_E
WDA_PW N_HLS1 IDIAG_HI
N_HLS2 N_HLS3 IDIAG_HI IDIAG_HI
CONFIG-REG 13 1 1 0 1 1 0 1 R_CNT_ GH_PDR
IPUPD_E IPUPD_E IPUPD_E GH_INJ GH_SOL
OFF_DIS V
N_STR1 N_STR2 N_STR3
CONFIG-REG 14 1 1 1 0 0 1 1 RLY1_UC RLY2_UC RLY3_UC RLY4_UC RLY5_UC STR1_UC STR2_UC STR3_UC

L9788
CONFIG-REG15-0
1 0 0 0 0 1 1 0 0 Wake up timer_SET_0[0:5]
(WUPT_0)
 Table 91. MSC Interface DOWN STREAM FRAME Bit Map (continued)

L9788
ADDRESS DATA

C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

CONFIG-REG15-1
1 0 0 0 0 1 0 0 1 Wake up timer_SET_1[6:11]
(WUPT_1)
CONFIG-REG15-2
1 0 0 0 0 1 0 1 0 Wake up timer_SET_2[12:17]
(WUPT_2)
CONFIG-REG15-2
1 0 0 0 0 1 1 1 1 Wake up timer_SET_3[18:23]
(WUPT_3)
CONFIG-REG16-0 0 0 1 0 0 1 1 0 1 PRD1_BLK[0:1] PRD2_BLK[0:1] PRD3_BLK[0:1]
O2H_PD O2H_PD
CONFIG-REG16-1 0 0 1 0 0 1 1 1 0 PRD4_BLK[0:1] PRD5_BLK[0:1]
RV_1 RV_3
O2H1_O O2H2_O
CONFIG-REG17-0 0 0 1 0 0 1 0 0 0 O2H1_SR O2H2_SR
C_TH C_TH
DS12308 Rev 4

CAN_WA CAN_PAT
CAN_TX_ CAN_RX CAN_2_5
CONFIG-REG17-1 0 0 1 0 0 1 0 1 1 CAN_EN KEUP_E TERN_E
EN _EN _MB
N N
MEM_VA
STBY_NVM_ADD_REG 0 1 0 0 1 1 0 0 1 STBY_NVM_ADD[0:3]
LID

Micro second channel (MSC) interface

STBY_NVM_DATA_REG 1 0 1 1 0 0 0 STBY_NVM_DATA[0:7]
WAKE_U KEY_OC LIN_TX_
FIN_WAK CAN_LO PDRV_O2
CONFIG-REG20 1 1 1 1 1 1 0 BIST_EN P_TIMER _RERTY_ CAN_TDI DOM_ER
E OP_EN H_DLY
_EN_SEL MAX_EN R_CFG
CAN_TX_ CAN_TX CAN_PE CAN_PE CAN_RX
BUCK_SL CAN_AU
CONFIG-REG21 0 0 0 0 0 0 1 DOM_ER OL_RED D_DOM RM_REC RM_DOM D_REC_E
OW_SR TO_BIAS
R_CFG _EN _EN _EN N
LOCK 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1
UNLOCK 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0
WDA_EN 1 0 0 1 1 1 1 0 1 1 0 0 1 1 0
WDA_DIS 1 0 0 1 1 1 1 1 0 0 1 1 0 0 1
189/264

SW-RESET 1 0 1 1 1 0 1 0 1 1 0 1 1 0 1
 Table 91. MSC Interface DOWN STREAM FRAME Bit Map (continued)
190/264

Micro second channel (MSC) interface

ADDRESS DATA

C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

EN-DRIVERS 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1
DISABLE-DRIVERS 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0
MRD_ON 0 1 1 0 0 0 1 1 1 0 0 0 1 1 1
MRD_OFF 0 1 1 0 0 0 1 0 0 1 1 1 0 0 0
MRD_UC 0 1 1 0 0 0 1 1 1 0 1 1 0 1 1
STR2_ON 0 1 0 0 1 0 0 0 0 1 0 1 0 1 0
STR2_OFF 0 1 0 0 1 0 0 1 1 0 1 0 1 0 1
STR3_ON 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0
STR3_OFF 0 1 0 0 1 0 0 1 1 1 1 0 0 1 1
DS12308 Rev 4

RLY4_ON 0 1 0 0 1 0 0 0 0 1 1 0 0 1 1
RLY4_OFF 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0

Legenda:

Locked bit Bit generated as pulse Address Default value Bit in satellite logic, not affected by reset matrix clear conditions
Locked bit: Bit generated as pulse Bit in satellite logic, not affected by reset matrix clear conditions.

L9788
L9788 Micro second channel (MSC) interface

18.5.1 CONFIG-REG 1

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

LED2_ WAKE_UP_TIM
CONFIG- PHOLD_E PHOLD_TIME[0: LED1_ BOOS
0 0 1 1 1 1 1 PD_E ER_START_ST
REG 1 N 1] PD_EN T_EN
N OP[0:1]
RW DEFAULT 0 0 0 0 0 1 1 0
D0:D5
v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
RESET SOURCE
D6:D7
the read bits are from satellite logic on VB_STBY and are not affected by
reset matrix
ACTIVATION D0:D7 bits active as level
not locked
CONTROL ACCESS
bits

[6:7] WAKE_UP_TIMER_START_STOP [0:1]

Start/stop Wake_up_timer counter
10: (stop) wake up timer stops (default)
01: (start) → 10 (stop) wake up timer counter value hold
10: (stop) → 01 (start) wake up timer starts from h'000001
01: (start) wake up timer counter is running
Application note: after a start/stop command 500us must be waited to have the command
be effective in the EOT clock domain.
[5] BOOST_EN
Boost enable.
1: enabled (default)
0: disabled
[4] LED2_PD_EN
Enable the pull down current (open load diagnosis not available) for LED2 driver
0: pull down current disabled (LED mode enabled) (default)
1: enable
[3] LED1_PD_EN
Enable the pull down current (open load diagnosis not available) for LED1 driver
0: pull down current disabled (LED mode enabled) (default)
1: enable
[2:1] PHOLD_TIME[1:0]

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263
Micro second channel (MSC) interface L9788

Set the power hold timeout.

00: timeout disabled (default)
01: 500 ms
10: 5 minutes
11: 20 minutes
[0] PHOLD_EN
Enable the power hold function.
0: disabled (default)
1: enabled

18.5.2 CONFIG-REG 2

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

IGN_CU
CONFIG- MSC_ACT F_DO_SE VRS_MODE IGN_ IPUPD IPUPD_
0 1 1 1 1 0 1 RRENT
REG 2 _EN L[0:1] _SEL DIAG _EN MODE
_CFG
RW DEFAULT 1 1 0 0 0 0 0 1
D0:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
ACTIVATION D0:D7 bits active as level
CONTROL ACCESS not locked bits

[7] IPUPD_MODE
Enable the fast charge current I_LS_PU1 required by driver fast off diagnosis.
0: fast charge current disabled
1: fast charge current enabled (default)
[6] IPUPD_EN
Enable the driver off diagnosis and the currents I_LS_PU2, I_LS_PD1 required by it.
0: off diagnosis disabled (default)
1: off diagnosis enabled
[5] IGN_DIAG.
0: IGN diagnosis off (default)
1: IGN diagnosis on
[4] IGN_CURRENT_CFG.
0: I1_HS_IGN current selected 15-30 mA (default)
1: I2_HS_IGN current selected 5-15 mA

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L9788 Micro second channel (MSC) interface

[3] VRS_MODE_SEL: VRS mode

0: limited adaptive (default)
1: full adaptive
[2:1] F_DO_SEL [1:0] Upstream clock ratio selection.
00: fDO= fCL/ 16
01: fDO= fCL/ 32(default)
10: fDO= fCL/ 64
11: fDO= fCL/ 128
[0] MSC_ACT_EN: MSC activity monitoring enable
0: MSC activity monitoring function is disabled
1: MSC activity monitoring function is enabled (default)

18.5.3 CONFIG-REG 3

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

RLY4_ LSD/H LSD/H LSD/H

CONFIG- DLY_ SD_D SD_D SD_D SRT2_ STR3_ T_SEO_DELAY[0:
1 1 1 1 0 0 1
REG 3 OFF_ RV1- RV2- RV3- EN EN 1]
EN CFG CFG CFG
RW DEFAULT 1 1 1 1 1 1 0 0
D0:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv,
sw_reset, after_run_reset, RSTN_IN
ACTIVATION D0:D7 bits active as level
CONTROL ACCESS locked bits

[7:6] SEO_DELAY_DELAY[1:0]
Delay from KEY_OFF for SEO function activation.
00: 100 ms (default)
01: 200 ms
10: 400 ms
11: 800 ms
[5] STR3_EN
0: disable
1: starter functions (DELAY OFF) enable for driver STR[3] (default)
[4] STR2_EN
0: disable

DS12308 Rev 4 193/264

263
Micro second channel (MSC) interface L9788

1: starter functions (DELAY OFF) enable for driver STR[2] (default)

[3] LSD/HSD_DRV3-CFG
1: LOW-SIDE configuration for STR3 driver (default)
0: HIGH-SIDE configuration for STR3 driver
[2] LSD/HSD_DRV2-CFG
1: LOW-SIDE configuration for STR2 driver (default)
0: HIGH-SIDE configuration for STR2 driver
[1] LSD/HSD_DRV1-CFG
1: LOW-SIDE configuration for STR1 driver (default)
0: HIGH-SIDE configuration for STR1 driver
[0] RLY4_DLY_OFF_EN
Enable delay off for RLY4 driver.
0: disabled
1: enabled (default)

18.5.4 CONFIG-REG 4

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

CONFIG-
1 1 0 0 0 0 1 PRD1_IDRV[0:1] PRD2_IDRV[0:1] PRD3_IDRV[0:1] PRD4_IDRV[0:1]
REG 4
RW DEFAULT 0 0 0 0 0 0 0 0
D0:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
ACTIVATION D0:D7 bits active as level
CONTROL ACCESS not locked bits

[7:6] PRD4_IDRV[1:0]
MOSFET pre-driver current driving strength
00: IDRV_00 20mA (default)
01: IDRV_01 10mA
10: IDRV_10 4mA
11: IDRV_11 2mA
[5:4] PRD3_IDRV[1:0]
MOSFET pre-driver current driving strength
00: IDRV_00 20mA (default)
01: IDRV_01 10mA

194/264 DS12308 Rev 4

L9788 Micro second channel (MSC) interface

10: IDRV_10 4mA

11: IDRV_11 2mA
[3:2] PRD2_IDRV[1:0]
MOSFET pre-driver current driving strength
00: IDRV_00 20mA (default)
01: IDRV_01 10mA
10: IDRV_10 4mA
11: IDRV_11 2mA
[1:0] PRD1_IDRV[1:0]
MOSFET pre-driver current driving strength
00: IDRV_00 20mA (default)
01: IDRV_01 10mA
10: IDRV_10 4mA
11: IDRV_11 2mA

18.5.5 CONFIG-REG 5

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

CONFIG- PRD5_IDRV[0:
0 0 0 0 1 1 1 PRD1_VDS[0:2] PRD2_VDS[0:2]
REG 5 1]
RW DEFAULT 0 0 0 0 0 0 0 0
D0:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
ACTIVATION D0:D7 bits active as level
CONTROL ACCESS not locked bits

[7:5] PRD2_VDS[2:0]
MOSFET pre-driver VDS threshold
000: VTH_DS_000 150mV (default)
001: VTH_DS_001 245mV
010: VTH_DS_010 325mV
011: VTH_DS_011 405mV
100: VTH_DS_100 525mV
101: VTH_DS_101 660mV
110: VTH_DS_110 950mV
[4:2] PRD1_VDS[2:0]

DS12308 Rev 4 195/264

263
Micro second channel (MSC) interface L9788

MOSFET pre-driver VDS threshold

000: VTH_DS_000 150mV (default)
001: VTH_DS_001 245mV
010: VTH_DS_010 325mV
011: VTH_DS_011 405mV
100: VTH_DS_100 525mV
101: VTH_DS_101 660mV
110: VTH_DS_110 950mV
[1:0] PRD5_IDRV[1:0]
MOSFET pre-driver current driving strength
00: IDRV_00 20mA (default)
01: IDRV_01 10mA
10: IDRV_10 4mA
11: IDRV_11 2mA

18.5.6 CONFIG-REG 6

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

CONFIG
1 1 0 0 1 1 1 PRD3_VDS[0:2] PRD4_VDS[0:2] EOT_MODE IGN_LSD_DIS
-REG 6
RW DEFAULT 0 0 0 0 0 0 1 1
D0:D5, D7
v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
RESET SOURCE
D6
the read bit is from satellite logic on VB_STBY and is not affected by reset
matrix
ACTIVATION D0:D7 bits active as level
CONTROL ACCESS D0:D7 not locked bits

[7] IGN_LSD_DIS
Disable for LSD stage in igniter driver to be used with IGBT load
0: LSD enable
1: LSD disabled (default)
[6] EOT_MODE
Bit going to Wake Up Timer Logic
Selection for EOT function

196/264 DS12308 Rev 4

L9788 Micro second channel (MSC) interface

0: counter without wake up function EOT function 1

1: counter with wake up function EOT function 2 (default)
Application note: EOT_MODE bit can be written only when WAKE_UP_TIMER_EN_SEL=0
(CONFIG_REG20 D2, MSC Start/Stop) and WAKE_UP_TIMER_START_STOP[0:1]=10
(CONFIG_REG1 D7-D6, Stop condition) when WAKE_UP_TIMER_START_STOP[0:1] is
effective in EOT clock domain
[5:3] PRD4_VDS[2:0]
MOSFET pre-driver VDS threshold
000: VTH_DS_000 150mV (default)
001: VTH_DS_001 245mV
010: VTH_DS_010 325mV
011: VTH_DS_011 405mV
100: VTH_DS_100 525mV
101: VTH_DS_101 660mV
110: VTH_DS_110 950mV
[2:0] PRD3_VDS[2:0]
MOSFET pre-driver VDS threshold
000: VTH_DS_000 150mV (default)
001: VTH_DS_001 245mV
010: VTH_DS_010 325mV
011: VTH_DS_011 405mV
100: VTH_DS_100 525mV
101: VTH_DS_101 660mV
110: VTH_DS_110 950mV

18.5.7 CONFIG-REG 7

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

CONFIG-
0 0 1 1 0 0 1 PRD5_VDS[0:2] TRK_EN[1] TRK_EN[2] TRK_EN[3] DAC[0:1]
REG 7
RW DEFAULT 0 0 0 1 1 1 1 1
D0:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
ACTIVATION D0:D7 bits active as level
CONTROL ACCESS not locked bits

[7:6] DAC

DS12308 Rev 4 197/264

263
Micro second channel (MSC) interface L9788

A/D test output voltage selection

00: 0.25*Vref
01: 0.50*Vref
10: 0.75*Vref
11: 1.0*Vref (default)
[5] TRK_EN[3]
Enable for tracking regulator 3
0: disabled
1: enabled (default)
[4] TRK_EN[2]
Enable for tracking regulator 2
0: disabled
1: enabled (default)
[3] TRK_EN[1]
Enable for tracking regulator 1
0: disabled
1: enabled (default)
[2:0] PRD5_VDS[2:0]
MOSFET pre-driver VDS threshold
000: VTH_DS_000 150mV (default)
001: VTH_DS_001 245mV
010: VTH_DS_010 325mV
011: VTH_DS_011 405mV
100: VTH_DS_100 525mV
101: VTH_DS_101 660mV
110: VTH_DS_110 950mV

198/264 DS12308 Rev 4

L9788 Micro second channel (MSC) interface

18.5.8 CONFIG-REG 8

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

VRS
CONFIG- VRS VRS
1 0 1 1 0 1 1 _DIA EN_FALLING_FILT HYS_FB_SEL
REG 8 _MODE[0:1] _HYS2[0:2]
G
RW DEFAULT 0 0 1 0 0 0 0 0
D0:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
ACTIVATION D0:D7 bits active as level
CONTROL ACCESS not locked bits

[7] HYS_FB_SEL:
0: VRS hyst. Feedback connected before adaptive filter (default)
1: VRS hyst. Feedback connected after adaptive filter
[6] EN_FALLING_FILT:
0: Falling edge filter disabled (default)
1: Falling edge filter enabled
[5:3] VRS_HYST[2:0]
000: Hys current = 17 µA (Hys VRS = 347 mV with 10 kΩ ext resistors) (default)
001: Hys current = 5 µA (Hys VRS=100mV with 10 kΩ ext resistors)
010: Hys current = 10 µA (Hys VRS=200mV with 10 kΩ ext resistors)
011: Hys current = 17 µA (Hys VRS=347mV with 10 kΩ ext resistors)
100: Hys current = 32 µA (Hys VRS=644mV with 10 kΩ ext resistors)
101: Hys current = 51 µA (Hys VRS=967mV with 10 kΩ ext resistors)
110: Hys current = 17 µA (Hys VRS=347mV with 10 kΩ ext resistors)
111: Hys current = 0 µA (used only for test purpose)
[2:1] VRS_MODE[1:0]
Internal auto-adaptive hysteresis OFF allows to configure hysteresis by MSC. Internal auto-
adaptive hysteresis ON selects higher hysteresis between the one configured by MSC and
the one internally computed by peak voltage.
Internal auto-adaptive filter time ON works properly only in full adaptive mode, in limited
adaptive mode filter time ON is fixed to 4 us. Internal auto-adaptive filter time OFF allows to
bypass the filter in both modalities.
00: Internal auto-adaptive hysteresis OFF, internal auto-adaptive filter time OFF
01: Internal auto-adaptive hysteresis ON, internal auto-adaptive filter time OFF
10: Internal auto-adaptive hysteresis OFF, internal auto-adaptive filter time ON (default)

DS12308 Rev 4 199/264

263
Micro second channel (MSC) interface L9788

11: Internal auto-adaptive hysteresis ON, internal auto-adaptive filter time ON

[0] VRS_DIAG: VRS diagnosis enable, only for full adaptive mode
0: diagnosis function is disabled (default)
1: diagnosis function is enabled

18.5.9 CONFIG-REG 9

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

CONFIG-
0 1 0 0 1 0 1 0 1 WDA_RESPTIME[0:5]
REG 9_0
RW DEFAULT 1 1 1 1 1 1
D2:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_ov, vdd5_uv, vddio_uv,
err_cnt>7, sw_reset, after_run_reset, RSTN_IN
ACTIVATION D2:D7 bits active as level

CONTROL ACCESS D2:D7 not locked bits

[7:2] WDA_RESPTIME[5:0]
Response-time = WDA_RESPTIME[5:0]) *1.6 ms
The error counter is incremented by one on a controller write access to this register

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

CONFIG
WDA_WIN
-REG 0 1 0 0 1 0 1 1 0 WDA_INIT
_SEL
9_1
RW DEFAULT 1 0
D2:D3
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_ov, vdd5_uv, vddio_uv,
err_cnt>7, sw_reset, after_run_reset, RSTN_IN
ACTIVATION D2:D3 bits active as level
CONTROL ACCESS D2:D3 locked bits

[3] WDA_INIT
Monitoring module reset
0: disabled (default)
1: enabled
[2] WDA_WIN_SEL
Select the time base for window watchdog generation

200/264 DS12308 Rev 4

L9788 Micro second channel (MSC) interface

0: 39 kHz
1: 64 kHz (default)

18.5.10 CONFIG-REG 10

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

CONFIG-
0 0 0 1 1 0 1 WDA_RESP[0:7]
REG 10
RW DEFAULT 0 0 0 0 0 0 0 0
D0:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_ov, vdd5_uv, vddio_uv,
err_cnt>7, sw_reset, after_run_reset, RSTN_IN
ACTIVATION D0:D7 bits active as level
CONTROL ACCESS D0:D7 not locked bits

WDA_RESP[0:7]
Q&A WD response according to Table 21.

18.5.11 CONFIG-REG 11

C C C C C C
C3 D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 4 5 6

LIN_TX_D
LIN_E LIN_E LIN_E O2H2_
CONFIG LIN/KLIN LIN_T IS_FOR_ VDD5_O
0 1 1 0 1 1 1 RR_E RR_E RR_E OC_FL
-REG 11 E SEL X_EN WDA_ER FF_SEL
N[0] N[1] N[2] T
R
RW DEFAULT 0 0 0 0 0 1 0 0
D0:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
ACTIVATION D0:D7 bits active as level
CONTROL ACCESS D0:D7 not locked bits

[7] O2H2_OC_FLT
Select the OVC filter time for O2H2.
0: select I_LS_ocv_flt (default)
1: select I_LS_ocv_flt x 2
[6] VDD5_OFF_SEL
VDD5 disabled by VB_IN UV:
0 VDD5 depends on VB_IN (default)

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Micro second channel (MSC) interface L9788

1: VDD5 does not depend on VB_IN

[5] LIN_TX_DIS_FOR_WDA_ERR
Disable the LIN transmitting when Watchdog ERR_CNT>4
0: LIN transmitting stays enabled when Watchdog ERR_CNT>4
1: LIN transmitting disabled when Watchdog ERR_CNT>4 (default)
[4] LIN_TX_EN
Enable the LIN transmission function
0: disabled (default)
1: enabled
[3] LIN_ERR_EN[2]
LIN error handling permanent dominant
0; LIN error handling disabled (default)
1; LIN error handling enabled
[2] LIN_ERR_EN[1]
LIN error handling permanent recessive
0; LIN error handling disabled (default)
1; LIN error handling enabled
[1] LIN_ERR_EN[0]
LIN error handling permanent TX timeout
0; LIN error handling disabled (default)
1; LIN error handling enabled
[0] LIN/KLIN SEL
Select between LIN/K-LINE sel
0: LIN Mode (default)
1: K-LINE Mode

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18.5.12 CONFIG-REG 12

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

VB_IN VDD5_ O2H1 WAKE_ WAKE_U

CONFIG- TNL_R FILTER WK_IN_
1 0 0 1 0 0 1 _OV_R OV_RS _OC_ UP_CAN P_EOT_
REG 12 ST_EN _MODE RST
ST_EN T_EN FLT _RST RST
RW DEFAULT 1 1 1 0 0 0 0 0
D0:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv,
sw_reset, after_run_reset, RSTN_IN
ACTIVATION D0:D7 bits active as level
CONTROL ACCESS not locked bits

[7] WK_IN_RST
Activation of WK_IN_RST, active on level
1: clearing of WK_IN_DET
0: no functionality (default)
[6] WAKE_UP_EOT_RST
Activation of WAKE_UP_EOT_RST, active on level
1: clearing of WAKE_UP_EOT_DET
0: no functionality (default)
[5] WAKE_UP_CAN_RST
Activation of WAKE_UP_CAN_RST, active on level
1: clearing of WAKE_UP_CAN_DET
0: no functionality (default)
[4] FILTER_MODE
Select the filter time (Tflt_diagoff) of all the drivers.
0: selected Tflt_diagoff1 (100us) (default)
1: selected Tflt_diagoff2 (600us)
[3] O2H1_OC_FLT
Select the OVC filter time for O2H1.
0: select I_LS_ocv_flt (default)
1: select I_LS_ocv_flt x 2
[2] VDD5_OV_RST_EN
Enable the contribution of VDD5_OV in the reset matrix
0: disabled

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1: enabled (default)
[1] VB_IN_OV_RST_EN
Enable the contribution of VB_IN_OV on BUCK /VDD5/ VTRK regulator in the reset matrix
0: disabled
1: enabled (default)
[0] TNL_RST_EN
enable the RSTN activation for TNL time on the positive edge of KEY_IN
1: enable (default)
0: disable

18.5.13 CONFIG-REG 13

C C C C C C
C4 D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 5 6

WDA_PW IPUPD_ IPUPD_ IPUPD_ IDIAG_ IDIAG_ IDIAG_

CONFIG-
1 1 0 1 1 0 1 R_CNT_ EN_STR EN_STR EN_STR HIGH_ HIGH_S HIGH_P
REG 13
OFF_DIS 1 2 3 INJ OL DRV
RW DEFAULT 0 0 0 0 0 1 1 1
D1:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
ACTIVATION D1:D7 bits active as level
D1 locked bit
CONTROL ACCESS
D2:D7 not locked bits

[7] IDIAG_HIGH_PDRV
Increase the currents required for pre-drivers off diagnosis.
0: I_LS_PU2 (40 µA (min) I_LS_PD1(60 µsA (min))
1: I_LS_PU3 (100 µA (min) I_LS_PD2(350 µsA (min)) (default)
[6] IDIAG_HIGH_SOL
Increase the currents required for Solenoids off diagnosis.
0: I_LS_PU2 (40 µA (min) I_LS_PD1(60 µsA (min))
1: I_LS_PU3 (100 µA (min) I_LS_PD2(350 µsA (min)) (default)
[5] IDIAG_HIGH_INJ
Increase the currents required for Solenoids off diagnosis.
0: I_LS_PU2 (40 µA (min) I_LS_PD1(60 µsA (min))
1: I_LS_PU3 (100 µA (min) I_LS_PD2(350 µsA (min)) (default)
[4] IPUPD_EN_STR3

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Enable the driver off diagnosis and the currents required by it.
0: off diagnosis disabled (default)
1: off diagnosis enabled
[3] IPUPD_EN_STR2
Enable the driver off diagnosis and the currents required by it.
0: off diagnosis disabled (default)
1: off diagnosis enabled
[2] IPUPD_EN_STR1
Enable the driver off diagnosis and the currents required by it.
0: off diagnosis disabled (default)
1: off diagnosis enabled
[1] WDA_PWR_CNT_OFF_DIS
Disable the power down due to watchdog pwr_cnt overflow.
0: enabled (default)
1: disabled
[0] Not used

18.5.14 CONFIG-REG 14

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

CONFI
RLY1_ RLY2_ RLY3_ RLY4_ RLY5_ STR1_ STR2_ STR3_
G-REG 1 1 1 0 0 1 1
UC UC UC UC UC UC UC UC
14
RW DEFAULT 0 0 0 0 0 0 0 0
D0:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
ACTIVATION D0:D7 bits active as pulse
CONTROL ACCESS D0:D7 not locked bits

[7] STR3_UC
0→1: micro command for fast diagnostic activation for relay driver STR3
0: no functionality (default)
1: no functionality
[6] STR2_UC
0→1: micro command for fast diagnostic activation for relay driver STR2
0: no functionality (default)

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1: no functionality
[5] STR1_UC
0→1: micro command for fast diagnostic activation for relay driver STR1
0: no functionality (default)
1: no functionality
[4] RLY5_UC
0→1: micro command for fast diagnostic activation for relay driver RLY5
0: no functionality (default)
1: no functionality
[3] RLY4_UC
0→1: micro command for fast diagnostic activation for relay driver RLY4
0: no functionality (default)
1: no functionality
[2] RLY3_UC
0→1: micro command for fast diagnostic activation for relay driver RLY3
0: no functionality (default)
1: no functionality
[1] RLY2_UC
0→1: micro command for fast diagnostic activation for relay driver RLY2
0: no functionality (default)
1: no functionality
[0] RLY1_UC
0→1: micro command for fast diagnostic activation for relay driver RLY1
0: no functionality (default)
1: no functionality

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18.5.15 CONFIG-REG 15

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

CONFIG-
REG15-0 1 0 0 0 0 1 1 0 0 Wake up timer_SET_0[0:5]
(WUPT_0)
RW DEFAULT 0 0 0 0 0 0
CONFIG-
REG15-1 1 0 0 0 0 1 0 0 1 Wake up timer_SET_1[6:11]
(WUPT_1)
RW DEFAULT 0 0 0 0 0 0
CONFIG-
REG15-2 1 0 0 0 0 1 0 1 0 Wake up timer_SET_2[12:17]
(WUPT_2)
RW DEFAULT 0 0 0 0 0 0
CONFIG-
REG15-3 1 0 0 0 0 1 1 1 1 Wake up timer_SET_3[23:18]
(WUPT_3)
RW DEFAULT 0 0 0 0 0 0
D2:D7
RESET SOURCE The read bits are from satellite logic on VB_STBY and are not affected by
reset matrix
ACTIVATION D2:D7 bits active as level
CONTROL ACCESS D2:D7 not locked bits

Application note: the minimum time distance between two consecutive accesses to the
Wake up timer SET registers is 2.5 µs.
Wake up timer_SET_x Bits go to, and are stored, in Wake Up Timer Logic.
Wake up timer_SET_x regs can be written only when WAKE_UP_TIMER_EN_SEL=0
(CONFIG_REG20 D2, MSC Start/Stop) and WAKE_UP_TIMER_START_STOP[0:1]=10
(CONFIG_REG1 D6-D7, Stop condition).

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18.5.16 CONFIG-REG 16

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

CONFIG-
0 0 1 0 0 1 1 0 1 PRD1_BLK[0:1] PRD2_BLK[0:1] PRD3_BLK[0:1]
REG 16-0
RW DEFAULT 1 0 1 0 1 0
CONFIG- O2H_P O2H_P
0 0 1 0 0 1 1 1 0 PRD4_BLK[0:1] PRD5_BLK[0:1]
REG 16-1 DRV_1 DRV_3
RW DEFAULT 1 0 1 0 0 0
D2:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
ACTIVATION D2:D7 bits active as level
CONTROL ACCESS D2:D7 not locked bits

[7] O2H_PDRV_3
VDS comparator selection for ON diagnosis
0: PDRV3 takes VDS3 comparator and PDRV4 works as independent driver
1: PDRV3 takes VDS4 comparator and PDRV4 driver cannot be used
[6] O2H_PDRV_1
VDS comparator selection for ON diagnosis
0: PDRV1 takes VDS1 comparator and PDRV2 works as independent driver
1: PDRV1 takes VDS2 comparator and PDRV2 driver cannot be used
PRDx_BLK[1:0]
Blanking time on VDS detection in ON state for Predriver
00: 6 µs
01: 12 µs (default)
10: 18 µs
11: 24 µs

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18.5.17 CONFIG-REG 17

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

CONFIG-
REG 0 0 1 0 0 1 0 0 0 O2H1_SR O2H1_OC_TH O2H2_SR O2H2_OC_TH
17_0
RW DEFAULT 0 0 1 0 0 1
D2:D7
RESET SOURCE v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
ACTIVATION D2:D7 bits active as level
CONTROL ACCESS D2:D7 not locked bits

[7] O2H2_OC_TH
Select OVC threshold
0: threasold1 I_ovc1_o2h 4.5A typ
1: threasold2 I_ovc2_o2h 10A typ (default)
[6] O2H2_SR
Select SR threshold
0: typ 0,5 V/us (default)
1: typ 4 V/us
[4] O2H1_OC_TH
Select OVC threshold
0: threasold1 I_ovc1_o2h 4.5A typ
1: threasold2 I_ovc2_o2h 10A typ (default)
[3] O2H1_SR
Select SR threshold
0: typ 0,5 V/µs (default)
1: typ 4 V/µs

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

CAN_WA CAN_PA
CONFIG- CAN CAN_TX_ CAN_RX CAN_2_5
0 0 1 0 0 1 0 1 1 KEUP_E TTERN_E
REG 17_1 _EN EN _EN _MB
N N
RW DEFAULT 1 1 1 1 1 0

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C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

D2:D7
RESET SOURCE The read bits are from satellite logic on VB_STBY and are not affected by
reset matrix
ACTIVATION D2:D7 bits active as level
D2:D6 not locked bits
CONTROL ACCESS
D7 locked bit

[7] CAN_2_5_MB
CAN mode selection:
0: CAN with 2Mbaud (default)
1: CAN FD with 5Mbaud with reduced EMC performance.
[6]CAN_RX_EN:
CAN Receiver enable:
0: disable
1: enable (default)
[5] CAN_PATTERN_EN
Normal pattern wake up enable:
0: disable
1: enable (default)
[4] CAN_WAKEUP_EN
Enable wake up by CAN:
0: disable
1: enable (default)
[3] CAN_TX_EN
CAN Transmitter enable:
0: disable
1: enable (default)
[2] CAN_EN
CAN enable
0: disable
1: enable (default)
All Bits go to and are stored in CAN Logic

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L9788 Micro second channel (MSC) interface

18.5.18 CONFIG-REG STBY_NVM

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

STBY_NVM
0 1 0 0 1 1 0 0 1 STBY_NVM_ADD[0:3] MEM_VALID
_ADD_REG
RW DEFAULT 0 0 0 0 0
D2:D6
RESET SOURCE The read bits are from satellite logic on VB_STBY and are not affected by
reset matrix
ACTIVATION D2:D6 bits active as level
CONTROL ACCESS D2:D6 not locked bits

[6] MEM_VALID
STBY NVM memory valid bit:
0: not valid (default)
1: valid
[5:2] STBY_NVM_ADD
STBY NVM write address
0000: address of the byte to write (default)
All Bits go to and are stored in Wake Up Timer Logic

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

STBY_NVM_
1 0 1 1 0 0 0 STBY_NVM_DATA[0:7]
DATA
RW DEFAULT 0 0 0 0 0 0 0 0
D0:D7
RESET SOURCE The read bits are from satellite logic on VB_STBY and are not affected by
reset matrix
ACTIVATION D0:D7 bits active as level
CONTROL ACCESS D0:D7 not locked bits

[7:0] STBY_NVM_ADD
Byte to write in STBY NVM
All Bits go to and are stored in Wake Up Timer Logic

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18.5.19 CONFIG-REG 20

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

WAKE_ KEY_OC LIN_TX_

FIN_
CONFIG- BIST_ UP_TIM _RETRY CAN_LO CAN_T DOM_E PDRV_O
1 1 1 1 1 1 0 WAK
REG 20 EN ER_EN _MAX_E OP_EN DI RR_CFG 2H_DLY
E
_SEL N

RW DEFAULT 0 0 0 0 0 0 0 0

D0:D1; D4:D7
v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
RESET SOURCE
D2:D3
the read bits are from satellite logic on VB_STBY and are not affected by reset
matrix
D0 bit active as pulse
ACTIVATION
D1:D7 bits active as level
D0:D3 not locked bits
CONTROL ACCESS
D4:D7 locked bits

[7] PDRV_O2H_DLY
Selection of delay time for switching from low to high current in predriver on/off transitions in
o2h configuration.
0: 150µs selected (default)
1: 300µs selected
[6] LIN_TX_DOM_ERR_CFG
LIN Tx enable after dominant error timeout:
0: re-enable as soon as Tx become recessive (default)
1: wait for error flag read
[5] CAN_TDI
CAN transmission depends on WDA:
0: WDA does not affect CAN (default)
1: disable transmission if WDA_INT active
[4] CAN_LOOP_EN
CAN looping mode enable:
0: disable (default)
1: enable
[3] KEY_OC_RETRY_MAX_EN
Enable a maximum number of retry after OVC, when wake up by key:

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0: disable (default)
1: enable
Bits going to Wake Up Timer Logic
[2] WAKE_UP_TIMER_EN_SEL
Select the source of activation for the wake_up_timer
0: from MSC start/stop commands (default)
1: from KEY_IN 1->0
Bits going to Wake Up Timer Logic
[1] FIN_WAKE
0: satellite logics execute auto clear 1 second after power up (default)
1: micro confirmed power up, no auto clear after 1 second
[0] BIST_EN
Bist enable for regulators
0: disable (default)
1: enable

18.5.20 CONFIG-REG 21

C C C C C C C
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6

CAN_ CAN_
CAN_TX BUCK CAN_T CAN_PE CAN_A
CONFIG PERM RXD_
0 0 0 0 0 0 1 _DOM_E OL_RED _SLO XD_DO RM_RE UTO_BI
-REG 21 _DOM REC_
RR_CFG W_SR M _EN C_EN AS
_EN EN
RW DEFAULT 0 0 0 1 1 1 1 1
D0:D2
v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset,
after_run_reset, RSTN_IN
ACTIVATION
D3:D7
the read bits are from satellite logic on VB_STBY and are not affected by reset
matrix
CONTROL ACCESS D0:D7 bits active as level
D0 locked bit
RESET SOURCE
D1:D7 not locked bits

[7] CAN_AUTO_BIAS
0: auto biasing disabled
1: auto biasing enabled (default)
[6] CAN_RXD_REC_EN
0: error handling disable

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1: error handling enable (default)

[5] CAN_PERM_DOM_EN
0: error handling disable
1: error handling enable (default)
[4] CAN_PERM_REC_EN
0: error handling disable
1: error handling enable (default)
[3] CAN_TXD_DOM _EN
0: error handling disable
1: error handling enable (default)
All Bits going to CAN Logic
[2] BUCK_SLOW_SR
0: fast slew rate selected (default)
1: slow slew rate selected
[1] OL_RED
Select open load current:
0:0.8 mA max (default)
1: 0.2 mA max
[0] CAN_TX_DOM_ERR_CFG
CAN Tx enable after dominant error timeout:
0: re-enable as soon as Tx become recessive (default)
1: wait for error flag read

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18.5.21 Commands
RD_COMMAND1.. RD_COMMAND16
These commands allow the reading of information that will be output on Upstream.

Table 92. Commands

ADDRESS DATA
Name
C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

RD_COMMAND1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
RD_COMMAND2 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
RD_COMMAND3 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1
RD_COMMAND4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
RD_COMMAND5 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1
RD_COMMAND6 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0
RD_COMMAND7 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1
RD_COMMAND8 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0
RD_COMMAND9 1 0 1 0 1 0 1 1 1 1 0 1 1 1 0
RD_COMMAND10 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1
RD_COMMAND11 0 1 0 1 0 1 0 1 1 1 0 1 1 1 0
RD_COMMAND12 0 1 0 1 0 1 0 0 0 0 1 0 0 0 1
RD_COMMAND13 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1
RD_COMMAND14 1 0 1 0 1 0 1 1 0 0 0 1 0 0 0
RD_COMMAND15 0 1 0 1 0 1 0 0 1 1 1 0 1 1 1
RD_COMMAND16 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0

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Lock Command
Registers that have this function are locked as default.
Registers are unlocked by the UNLOCK command and locked again by the LOCK
command. Before the LOCK command the registers stay unlocked.

W C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

LOCK 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1

Unlock Command
Enables the write right to registers under lock.

W C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

UNLOCK 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0

Question and Answer Watch Dog Enable command

WD is enabled as default.

W C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

WDA_EN 1 0 0 1 1 1 1 0 1 1 0 0 1 1 0

Question and Answer Watch Dog Disable command

W C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

WDA_DIS 1 0 0 1 1 1 1 1 0 0 1 1 0 0 1

SW-Reset command
This command generates internal reset initiated by the CPU's software that clears all the
configuration and diagnostic registers and switches off all the drivers.

W C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

SW-RESET 1 0 1 1 1 0 1 0 1 1 0 1 1 0 1

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EN_Drivers command
The command Enable Drivers sets the bit Drivers_EN to "1" (UPS1 Frame 10 bit D1).
With Drivers_EN =1 all drivers controlled through control register can be activated using the
Data Frame.
After a reset or command Disable Drivers_EN = "0" and all drivers are disabled.

W C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

EN-DRIVERS 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1

Disable Driver

W C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

DISABLE-DRIVERS 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0

Main relay Driver ON

W C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

MRD_ON 0 1 1 0 0 0 1 1 1 0 0 0 1 1 1

Main relay Driver OFF

W C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

MRD_OFF 0 1 1 0 0 0 1 0 0 1 1 1 0 0 0

MRD_OFF_UC command

The Main Relay Driver is switched off for the time required to perform the off diagnosis and
then switched on again. The command can be activated if firstly is unlocked.

W C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 D5 D6 D7

MRD_UC 0 1 1 0 0 0 1 1 1 0 1 1 0 1 1

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STR2 driver ON/OFF

It has effect only if delay-off function for this driver is active (Config3[4] = 1).

STR2_ON 0 1 0 0 1 0 0 0 0 1 0 1 0 1 0
STR2_OFF 0 1 0 0 1 0 0 1 1 0 1 0 1 0 1

STR3 driver ON/OFF

It has effect only if delay-off function for this driver is active (Config3[5] = 1).

STR3_ON 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0
STR3_OFF 0 1 0 0 1 0 0 1 1 1 1 0 0 1 1

RLY4 driver ON/OFF

It has effect only if delay-off function for this driver is active (Config3[0] = 1).

RLY4_ON 0 1 0 0 1 0 0 0 0 1 1 0 0 1 1
RLY4_OFF 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0

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18.6 Upstream frame

See downstream paragraph for configuration register bits description. Bits highlighted in
orange are clear on read. Bits highlighted in green come from satellite logics, they need
VB_STBY in order to be correctly read.

18.6.1 Upstream Bit Map Read1 (CONFIG-REG 1-4)

Table 93. MSC Interface Upstream Bit Map Read1

ADDRESS DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

FRAME1 0 0 0 0 CONFIG-REG 1
FRAME2 0 0 1 0 CONFIG-REG 2
FRAME3 0 0 0 1 CONFIG-REG 3
FRAME4 0 0 1 1 CONFIG-REG 4
source logic on VB_IN (main logic)
access read

Frame[1]
[7:6] WAKE_UP_TIMER_START_STOP:
Read start "10" or stop "01" status, (never read "00" or "11").
These bits are valid only if WUT is driven by MSC.

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18.6.2 Upstream Bit Map Read2 (CONFIG-REG 5-8)

Table 94. MSC Interface Upstream Bit Map Read2

ADDRESS DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

CONFIG-REG 5
FRAME1 0 0 0 0

CONFIG-REG 6
FRAME2 0 0 1 0
EOT_MODE(1)
CONFIG-REG 7
FRAME3 0 0 0 1

CONFIG-REG 8
FRAME4 0 0 1 1

FRAME[1][3][4] FRAME[2]D[0:5] FRAME[2]D[7]

logic on VB_IN (main logic)
source
FRAME[2]D[6]
logic on VB_STBY(Wake Up Timer logic)
access read
1. Bit in satellite logic.

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L9788 Micro second channel (MSC) interface

18.6.3 Upstream Bit Map Read3 (CONFIG-REG 11-13, 16-0)

Table 95. MSC Interface Upstream Bit Map Read3
ADDRESS DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7
CONFIG-REG 11
FRAME1 0 0 0 0

CONFIG-REG 12
FRAME2 0 0 1 0

CONFIG-REG 13
FRAME3 0 0 0 1

STR_DELAY_OFF_STATUS CONFIG-REG 16-0

FRAME4 0 0 1 1
STR2 STR3
source logic on VB_IN (main logic)
access read

FRAME[4]:
[1] 1:STR3 delay-off function active
0: STR3 delay-off function inactive
[0] 1: STR2 delay-off function active
0: STR2 delay-off function inactive

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263
Micro second channel (MSC) interface L9788

18.6.4 Upstream Bit Map Read4 (CONFIG-REG 16-1 + Wake up timer_SET)

Table 96. MSC Interface Upstream Bit Map Read4
ADDRESS DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7
RLY4_DELAY_OFF_STATUS MRD_STATUS CONFIG-REG 16_1
FRAME1 0 0 0 0
RLY4 MRD
Wake up timer_SET [23:0]
FRAME2 0 0 1 0 Wake up timer_SET_0[0:7](1)
FRAME3 0 0 0 1 Wake up timer_SET_1[8:15](1)
FRAME4 0 0 1 1 Wake up timer_SET_2[16:23](1)
FRAME[1][0:7]
logic on VB_IN (main logic)
source
FRAME[2:4]D[0:7]
logic on VB_STBY (Wake Up Timer logic)
access read
1. Bit in satellite logic.

FRAME[1]:
[1] 1: Main Relay Driver On
0: Main Relay Driver Off
[0] 1: RLY4 delay-off function active
0: RLY4 delay-off function inactive
FRAME[2:4]: Wake Up Timer setting
Bits coming from WUT Logic

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L9788 Micro second channel (MSC) interface

18.6.5 Upstream Bit Map Read5 (CONFIG-REG 17-0, WAKE_UP_TIMER

VALUE)

Table 97. MSC Interface Upstream Bit Map Read5

ADDRESS DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

TNL CONFIG-REG 17_0

FRAME1 0 0 0 0
TNL_RESET(1)
TIMER CONT VALUE[23:0]
FRAME2 0 0 1 0 Wake up timer _CNT_0[0:7](2)
FRAME3 0 0 0 1 Wake up timer _CNT_1[8:15](2)
FRAME4 0 0 1 1 Wake up timer _CNT_2[16:23](2)
FRAME[1]D[0:7]
logic on VB_IN (main logic)
source
FRAME[2:3]D[0:7]
logic on VB_STBY (Wake Up Timer logic)
FRAME[1]D[1]
clear-on-read
access
FRAME[1]D[0] FRAME[1]D[2:7] FRAME[2:4]D[0:7]
read
1. Clear on Read.
2. Bit in satellite logic.

FRAME[1]:
[1] 1: After run reset (TNL) happened
0: After run reset (TNL) not happened, clear on read
FRAME[2:4]: Wake Up Timer counting

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Micro second channel (MSC) interface L9788

18.6.6 Upstream Bit Map Read6 (DRIVER DIAGNOSIS)

Table 98. MSC Interface Upstream Bit Map Read6

ADDRESS DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

DIAG INJ1 DIAG INJ2

FRAME1 0 0 0 0
STA STG OPL OVC STA STG OPL OVC
DIAG INJ3 DIAG INJ4
FRAME2 0 0 1 0
STA STG OPL OVC STA STG OPL OVC
DIAG O2H1
FRAME3 0 0 0 1
STA STG OPL OVC
DIAG O2H2
FRAME4 0 0 1 1
STA STG OPL OVC
source logic on VB_IN (main logic)
access clear-on-read

Clear on Read

FRAME[1:4]: Driver diagnosis for driver

STA: driver diagnosis: error in driver status
The driver status is detected by reading the STG comparator in on and off, it should be
aligned with command (msc command and enabling).
0: aligned, no error
1: not aligned, error
STG/STB: driver diagnosis: short to ground/battery
0: no fault (default)
1: for low-side and igniter drivers: short to ground fault
for high-side driver: short to battery fault
OPL: driver diagnosis: open load
0: no fault (default)
1: open load fault
OVC: driver diagnosis: over current
0: no fault (default)
1: over current faul

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L9788 Micro second channel (MSC) interface

18.6.7 Upstream Bit Map Read7 (DRIVER DIAGNOSIS)

Table 99. MSC Interface Upstream Bit Map Read7

ADDRESS READ3 DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

DIAG LED1 DIAG LED2

FRAME1 0 0 0 0
STA STG OPL OVC STA STG OPL OVC
MRD DIAG DIAG RLY1
FRAME2 0 0 1 0
STA STG OPL OVC STA STG OPL OVC
DIAG RLY2 DIAG RLY3
FRAME3 0 0 0 1
STA STG OPL OVC STA STG OPL OVC
DIAG RLY4 DIAG RLY5
FRAME4 0 0 1 1
STA STG OPL OVC STA STG OPL OVC
source logic on VB_IN (main logic)
access clear-on-read

Clear on Read

18.6.8 Upstream Bit Map Read8 (DRIVER DIAGNOSIS)

Table 100. MSC Interface Upstream Bit Map Read8

ADDRESS READ4 DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

DIAG STR1 DIAG STR2

FRAME1 0 0 0 0
STA STG/STB OPL OVC STA STG/STB OPL OVC
DIAG STR3 DIAG PRD1
FRAME2 0 0 1 0
STA STG/STB OPL OVC STA STG OPL OVC
DIAG PRD2 DIAG PRD3
FRAME3 0 0 0 1
STA STG OPL OVC STA STG OPL OVC
DIAG PRD4 DIAG PRD5
FRAME4 0 0 1 1
STA STG OPL OVC STA STG OPL OVC
source logic on VB_IN (main logic)
access clear-on-read

Clear on Read

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Micro second channel (MSC) interface L9788

18.6.9 Upstream Bit Map Read9 (DRIVER DIAGNOSIS)

Table 101. MSC Interface Upstream Bit Map Read9

ADDRESS READ4 DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

DIAG IGN1 DIAG IGN2

FRAME1 0 0 0 0
STA STG OPL OVC STA STG OPL OVC
DIAG IGN3 DIAG IGN4
FRAME2 0 0 1 0
STA STG OPL OVC STA STG OPL OVC
DIAG IGN5 DIAG IGN6
FRAME3 0 0 0 1
STA STG OPL OVC STA STG OPL OVC
DIAG SOL1 DIAG SOL2
FRAME4 0 0 1 1
STA STG OPL OVC STA STG OPL OVC
source logic on VB_IN (main logic)
access clear-on-read

Clear on Read

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L9788 Micro second channel (MSC) interface

18.6.10 Upstream Bit Map Fast Read10 (SAFETY WDA)

Table 102. MSC Interface Upstream Bit Map Read10

ADDRESS DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

WDA REQULO
FRAME1 0 0 0 0
REQU[0:3] ERR_CNT[0:2] WDA_INT
WDA REQUHI
FRAME2 0 0 1 0 RESP_TO NO_RE W_RE RESP_ RESP_E
CHRT RESP_CNT[0 :1]
O_EARLY SP SP Z0 RR
WDA PWR_RST_CNT
FRAME3 0 0 0 1
RST_CNT[0 :2] PWR_CNT[0:2] WDA_RST
WDA RESPTIME

FRAME4 0 0 1 1 WDA_
RESPTIME[0:5] WIN_S WDA_INIT
EL
source logic on VB_IN (main logic)
FRAME[1]D[0:7] FRAME[2]D[0] FRAME[2]D[2] FRAME[2]D[4:7]
FRAME[3]D[0:7] FRAME[4]D[0:7]
access read
FRAME[2]D[1] FRAME[2]D[3]
clear-on-read

Clear on Read

FRAME[1]: WATCHDOG REQULO

[7] WDA_INT
1: ERR_CNT[2:0]>4
Default: 1
[6:4] ERR_CNT[2:0]
Value of ERR_CNT[2:0]
Default: 0x6
[3:0] REQU[3:0]
4-bit question
FRAME[2]: WATCHDOG REQUHI
[7:6] RESP_CNT[1:0]
Counter for receiving the 4 response bytes
Default: 0xC

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Micro second channel (MSC) interface L9788

[5] RESP_ERR
1: 1 byte of 32-bit response is incorrect: one of the response bytes in the current sequencer
run is wrong, reading WDA status register after the 4th byte write implies that this flag will
always be read as 0.
reset to zero at each sequencer-run
[4] RESP_Z0
1: Controller set response time to 0ms
a correct response within the time window nevertheless increments the error counter by one
0: Response-time is greater than 0ms
[3] CHRT
1: Controller has changed response time
reset to zero after a read access and after the next sequencer run
[2] W_RESP
1: if one of the RESP_BYTEx was incorrect during the previous sequencer run;
0: otherwise
[1] NO_RESP
1: in case of no response at all timer is restarted automatically
reset to zero after a read access
[0] RESP_TOO_EARLY
1: in case the 4 response bytes arrive before time window starts during the previous
sequencer run;
Reset to zero at each sequencer run
FRAME[3]: WATCHDOG PWR_RST_CNT
[7] WDA_RST
See reset matrix
[5:3] PWR_CNT[2:0]
Current value of PWR_CNT register
[2:0] RST_CNT[2:0]
Current value of RST_CNT register
FRAME[4]: WATCHDOG RESPTIME
[7:6] CONFIG-REG9_1
[5:0] RESPTIME[5:0]
CONFIG-REG9_0

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L9788 Micro second channel (MSC) interface

18.6.11 Upstream Bit Map Read11 (SAFETY+BIST+VRS+LIN+ASIC_REV)

Table 103. MSC Interface Upstream Bit Map Read11

ADDRESS DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

SAFETY/VRS

FRAME1 0 0 0 0 CLK_
FREQ OSC_S OL_
TRANS_L TRANS_F CMD_ERR MON_ VRS_DIAG
_ERR TUCK RED
FAULT
BIST
FRAME2 0 0 1 0
V3V3 VDD5 IGN1 IGN2 IGN3 IGN4 IGN5 IGN6
BIST/LIN
LIN/
FRAME3 0 0 0 1 DRIVER KLINE
BIST_END INJ1 INJ2 INJ3 INJ4 LOCK
_EN STAT
US
ASIC REVISION[0:7]
FRAME4 0 0 1 1
1 1 0 0 0 1 0 0
source logic on VB_IN (main logic)
FRAME[1]D[6] FRAME[3][5:7] FRAME[4]D0:7]
read
access
FRAME[1]D[0:5] FRAME[1]D[7] FRAME[2]D[0:7] FRAME[3]D[0:4]
clear-on-read

Clear on Read

FRAME[1]: SAFETY/VRS
[0] TRANS_L
Wrong command frame or data frame down stream length (longer than 16 bits)
0: no fault (default)
1: down stream frame length incorrect
[1] TRANS_F
No valid the data frame for longer than tMSC_mon
0: no fault (default)
1: no data stream within tMSC_mon time out
[2] CMD_ERR
This bit is address error(C0-C5) of previous command Frame
0: no fault (default)
1: command error

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[3] FREQ_ERR
Main OSC and checker OSC running with more than +/- 20% freq difference
0: no fault (default)
1: clocks out of frequency or stucked
[4] CLK_MON_FAULT
Main OSC and checker OSC running with more than +/- 30% freq difference
0: no fault (default)
1: clocks out of frequency or stucked (drivers disabled)
[5] OSC_STUCK
Main OSC or checker OSC stuck
0: no fault (default)
1: clocks stucked (drivers disabled)
[6] OL_RED
CONFIG_REG21 BIT 1
[7] VRS_DIAG
VRS diagnosis result
0: no fault detected (default)
1: generic fault detected
FRAME[2]: BIST
[0] BIST_V3V3
Bist result for V3V3 regulator
0: bist pass (default)
1: bist fail
[1] BIST_VDD5
Bist result for VDD5 regulator
0: bist pass (default)
1: bist fail
[2:7] BIST_IGN
Bist result for Igniter drivers
0: bist pass (default)
1: bist fail
FRAME[3]: BIST/LIN
[0] BIST_END
End of Bist operation
0: bist not end

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L9788 Micro second channel (MSC) interface

1: bist end
[1:4] BIST_INJ
Bist result for INJECTOR drivers
0: bist pass (default)
1: bist fail
[5] DRIVER_EN
Drivers enabled or disabled by MSC command
0: drivers disabled (default)
1: drivers enabled
[6] LIN_KLINE_STATUS
LIN / K-LINE Mode (CONFIG-REG11 [0])
0: LIN mode (default)
1: KLINE mode
[7] MSC LOCK
MSC command and bit lock
0: unlocked
1: locked (default)
FRAME [4]: ASIC REVISION FOR BC
[0:7] ASIC_REVISION

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Micro second channel (MSC) interface L9788

18.6.12 Upstream Bit Map Read12 (PHOLD+POWER_UP+ADC)

Table 104. MSC Interface Upstream Bit Map Read12

ADDRESS DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

PHOLD

FRAME1 0 0 0 0 PHOLD PHOLD PHOLD PHOLD PHOLD PHOLD

PHOLD PHOLD
_TIME TIMER TIMER TIMER TIMER TIMER
TIMER[5] TIMER[6]
STATUS [0] [1] [2] [3] [4]
PHOLD

FRAME2 0 0 1 0 PHOLD PHOLD PHOLD PHOLD PHOLD PHOLD PHOLD PHOLD

TIMER TIMER TIMER TIMER TIMER TIMER TIMER TIMER
[7] [8] [9] [10] [11] [12] [13] [14]
EOT_ST
POWER UP ADC
ATUS
FRAME3 0 0 0 1 WAKE_ WAKE_
KEY_IN WK_IN FAULT_
UP_EO UP_CAN EOT(1) ADC[0] ADC[1]
_DET _DET WARN
T_DET _DET
ADC
FRAME4 0 0 1 1
ADC[2] ADC[3] ADC[4] ADC[5] ADC[6] ADC[7] ADC[8] ADC[9]
FRAME[1]D[0:7] FRAME[2]D[0:7] FRAME[3]D[0:4] FRAME[3]D[6:7]
FRAME[4]D[0:7]
source logic on VB_IN (main logic)
FRAME[3]D[5]
logic on VB_STBY (Wake Up Timer logic)
access read
1. Bit in satellite logic.

FRAME[1:2]: POWER_HOLD TIMER

It is the counter used to reach the timeout selected by PHOLD_TIME[0:1] configuration bits.
The run time is derived from the PHOLD_TIMER[14:0] according to the formula:
run time = PHOLD_TIMER[14:0] * 279 ms
FRAME[3]: POWER_UP
[0] KEY_IN_DET
Latch status of activation of KEY_IN signal
0: low level detected on KEY_IN signal
1: high level on KEY_IN signal
[1] WK_IN_DET
Latch status of activation of WK_IN signal.
0: no positive edge detected on WK_IN signal

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L9788 Micro second channel (MSC) interface

1: positive edge on WK_IN signal

[2] WAKE_UP_EOT_DET
Latch status of activation of Wake_Up_Timer counter
0: Wake_Up_Timer end counting not detected
1: Wake_Up_Timer end counting detected
[3] WAKE_UP_CAN_DET
Latch status of activation of CAN signal
0: no wake up activity detected on CAN
1: wake up activity detected on CAN
[4] FAULT_WARN
0: no fault warning active
1: at least one of fault warning contributors (oscillator fault, v3v3pre_mon_ov,
v3v3pre_mon_uv, v3v3pre_ov, v3v3pre_uv, v3v3ana_ov, v3v3ana_uv, v3v3dig_ov,
v3v3dig_uv, gnd_dig_loss) is active.
[5] EOT_STATUS:
1: EOT active (WAKE_UP_TIMER_START_STOP[0:1] = 01, start)
0: EOT inactive (WAKE_UP_TIMER_START_STOP[0:1] = 10, stop)
[6:7] ADC[0:1]
FRAME[4]
[0:7] ADC[2:9]
Temperature= (ADC[9:0] * 293 / 1024) - 63 [°C]

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Micro second channel (MSC) interface L9788

18.6.13 Upstream Bit Map Read13 (SUPPLY UV/OV)

Table 105. MSC Interface Upstream Bit Map Read13

ADDRESS DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

SUPPLY OVERVOLTAGE/UNDERVOLTAGE
FRAME
0 0 0 0 V3V3A_ V3V3A_ V3V3D_ V3V3D_ VB_IN_ VB_IN_ VB_IN_
1
UV OV UV OV UV OV 1 OV 2
SUPPLY OVERVOLTAGE/UNDERVOLTAGE
FRAME GND_
0 0 1 0 VB_STB VDDIO_ VDD5_ VDD5_ VPRE_ VPRE_
2 DIG_
Y_UV(1) UV UV OV UV OV
LOSS
SUPPLY OVERVOLTAGE/UNDERVOLTAGE

FRAME WAKE_
0 0 0 1 UP_CAN TRIM_ TRK_ TRK_ TRK_ TRK_ TRK_ TRK_
3
_DET_ VALID STB[1] STB[2] STB[3] OVC[1] OVC[2] OVC [3]
AUTO
SUPPLY OVERVOLTAGE/UNDERVOLTAGE
FRAME INT_ INT_ INT INT_ INT_ INT_
0 0 1 1 EXT_ EXT_
4 TRK_ TRK_ _TRK_ TRK_OV TRK_O TRK_
TRK_UV TRK_OV
UV[1] UV[2] UV[3] [1] V[2] OV[3]
FRAME[1]D[0:7] FRAME[2]D[1:7] FRAME[3]D[0:7] FRAME[4]D[0:7]
logic on VB_IN (main logic)
source
FRAME[2]D[0]
logic on VB_STBY (Wake Up Timer logic)
FRAME[3]D[1]
read
access
FRAME[1]D[0:7] FRAME[2]D[0:7] FRAME[3]D[0] FRAME[3]D[2:7] FRAME[4]D[0:7]
clear-on-read
1. Bit in satellite logic.

Clear on Read

FRAME[1:4]: SUPPLY OVERVOLTAGE/UNDERVOLTAGE

0: no fault (default)
1: overvoltage/undervoltage detected on the corresponding pin
VB_STBY_UV is functional only if VB_STBY is present, if VB_STBY is totally disconnected
no diagnosis related to VB_STBY will be available (bit latched in wut logic).
GND_DIG_LOSS comparator for digital ground level
0: the digital ground supply is connected to ground.
1: the digital ground supply is disconnected from ground.
TRIM_VALID

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L9788 Micro second channel (MSC) interface

0: trimming content not written or not valid (parity check fail) (default)
(in this case the trimming content is anyway used)
1: trimming content written and valid
WAKE_UP_CAN_DET_AUTO
0: No Wakeup pattern detected in sleep mode with UCHIP-ON and CAN_AUTO_BIAS =
1(CONFIG-REG 21 D7) (default)
1: Wakeup pattern detected

18.6.14 Upstream Bit Map Read14 (THERMAL WARNING AND CAN)

Table 106. MSC Interface Upstream Bit Map Read14

ADDRESS DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

OVERTEMPERATURE
FRAME1 0 0 0 0
OVT[1] OVT[2] OVT[3] OVT[4] OVT[5] OVT[6] OVT[7] OVT[8]
OVERTEMPERATURE
FRAME2 0 0 1 0
OVT[9] OVT[10] OVT[11] OVT[12] OVT[13] OVT[14] OVT[15] OVT[16]
OVERTEMPERATURE CONFIG-REG 17_1

FRAME3 0 0 0 1 VDD_ CAN_ CAN_

CAN_EN CAN_TX
OVT[17] OVT[18] OVT[19] CAN_OV (1) RX_EN WAKEU
(1) _EN(1) (1) P_EN(1)

CONFIG-REG 17_1 CAN DIAG

FRAME4 0 0 1 1 CAN_ CAN_ CAN_ CAN_ CAN_ CAN_ CAN_ CAN_

PATTER 2_5_MB TXD_ PERM_ PERM_ RXD_ SILENT SUP_L
N_EN(1) (1)
DOM (1) REC
(1)
DOM(1) REC(1) (1)
OW(1)
FRAME[1]D[0:7] FRAME[2]D[0:7] FRAME[3]D[0:2]
logic on VB_IN (main logic)
source
FRAME[3]D[4:7] FRAME[4]D[0:7]
logic on VB_STBY (Can logic)
FRAME[3]D[4:7] FRAME[4]D[0:1]
read
access
FRAME[1]D[0:7] FRAME[2]D[0:7] FRAME[3]D[0:3] FRAME[4]D[2:7]
clear on read
1. Bit in satellite logic.

Clear on Read

FRAME[1:3]: OVERTEMPERATURE
0: no fault (default)
1: overtemperature detected on the corresponding block
FRAME[3:4]:

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Micro second channel (MSC) interface L9788

[3]: VDD_CAN_OV
0: no fault
1: VDD_CAN _OV overvoltage detected
CONFIG_REG 17-1
FRAME[4]: CAN DIAG, see CAN section for detailed description.

18.6.15 Upstream Bit Map Read15 (MEM_STBY_CONFIG+CONFIG_REG20+UCs)

Table 107. MSC Interface Upstream Bit Map Read15

ADDRESS DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

LIN_ERROR STBY_NVM_ADD_REG

FRAME1 0 0 0 0 LIN_ LIN_ LIN_

MEM_
PERM_ PERM_ TXD_ STBY_NVM_ADD[0:3](1)
VALID(1)
REC DOM DOM
CONFIG_REG_21
CAN_ CAN_ CAN_ CAN_
FRAME2 0 0 1 0 BUCK_ CAN_ KEY_ WAKE_
TXD_ PERM_ PERM_ RXD_
SLOW_ AUTO_ IN_PIN IN_PIN_
DOM REC_ DOM_ REC_EN(
SR BIAS(1) _FLT FLT
_EN(1) EN(1) EN(1) 1)

CONFIG-REG 20
WAKE_
CAN_TX_ KEY_O LIN_TX
FRAME3 0 0 0 1 UP_TI PDRV_
DOM_ FIN_W C_RER CAN_LO _DOM_
MER_E CAN_TDI O2H_
ERR_ AKE TY_MA OP_EN ERR_C
N_SEL DLY
CFG(1) (1) X_EN(1) FG

CONFIG-REG 14 (UCOMMANDS STATUS)

FRAME4 0 0 1 1 RLY2_ RLY3_ RLY4_U STR2_ STR3_
RLY1_UC RLY5_UC STR1_UC
UC UC C UC UC
FRAME[1]D[0:2] FRAME[2]D[0] FRAME[2]D[6:7] FRAME[3]D[1] FRAME[3][4:7]
source FRAME[4]D[0:7]
logic on VB_IN (main logic)
FRAME[1]D[3:7] FRAME[2]D[0:7] FRAME[3]D[0:7] FRAME[4]D[0:7]
read
access
FRAME[1]D[0:2]
clear-on-read
1. Bit in satellite logic.

Clear on Read

FRAME [1]
[7] MEM_VALID (see 4.19)
1: memory has been written and validated by micro by reading back data.

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L9788 Micro second channel (MSC) interface

0: memory was not validated or standby-power-supply is removed

[6:3] STBY_NVM_ADD
[2] 1: LIN TxD dominant timeout error occurs
0: no LIN TxD dominant timeout error occurs
Clear on read
[1] 1: LIN permanent dominant error occurs
0: no LIN permanent dominant error occurs
Clear on read
[0] 1: LIN permanent recessive error occurs
0: no LIN permanent recessive error occurs
Clear on read
FRAME[2]
[7] 1: The WK_IN pin (filtering on low to high transition) is at high state.
0: The WK_IN pin (filtering on high to low transition) is at low state.
[6] 1: The KEY_IN pin (filtering on low to high transition) is at high state.
0: The KEY_IN pin (filtering on high to low transition) is at low state.
FRAME[3]
FRAME[4]
[7:0] µcommands:
1 if driver µcommand is still active and driver is off, 0 otherwise
0 if driver µcommand is still active and driver is on, 1 otherwise
See driver section for detailed description of µcommands.

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263
Micro second channel (MSC) interface L9788

18.6.16 Upstream Bit Map Read16 (MEM_STBY_DATA)

Table 108. MSC Interface Upstream Bit Map Read16

ADDRESS DATA

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

MEM_STBY_DATA(Byte0)(1)
FRAME1 0 0 0 0

MEM_STBY_DATA(Byte1)(1)
FRAME2 0 0 1 0

MEM_STBY_DATA(Byte2)(1)
FRAME3 0 0 0 1

MEM_STBY_DATA(Byte3)(1)
FRAME4 0 0 1 1

source logic on VB_STBY (Wake Up Timer logic)(1)

access read
1. Bit in satellite logic.

FRAME[1:4]: BYTES READ FROM MEM+STBY

238/264 DS12308 Rev 4

L9788 Package information

19 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

19.1 LQFP100 (14x14x1.4 mm exp. pad down) package information

Figure 89. LQFP100 (14x14x1.4 mm exp. pad down) package outline

BOTTOM VIEW

TOP VIEW

7518915_3.0_OS GADG2411160733PS

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Package information L9788

Table 109. LQFP100 (14x14x1.4 mm exp. pad down) package mechanical data
Dimensions in mm
Symbol Notes:
Min. Typ. Max.
Ө 0° 3.5° 6° -
Ө1 0° - - -
Ө2 10° 12° 14° -
Ө3 10° 12° 14° -
A - 1.40 1.60 15
A1 0.05 - 0.15 12
A2 1.35 1.40 1.45 15
b 0.17 0.22 0.27 9, 11
b1 0.17 0.20 0.23 11
c 0.09 - 0.20 11
c1 0.09 - 0.16 11
D 16.00 BSC 4
D1 16.00 BSC 5, 2
D2 VARIATIONS 13
D3 VARIATIONS 14
e 0.50 BSC -
E 16.00 BSC 4
E1 14.00 BSC 5, 2
E2 VARIATIONS 13
E3 VARIATIONS 14
L 0.45 0.60 0.75 -
L1 1.00 REF -
N 100 16
R1 0.08 - - -
R2 0.08 - 0.20 -
S 0.20 - - -
Tolerance of form and position
aaa 0.20
bbb 0.20
1, 7
ccc 0.08
ddd 0.08

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size up to 0.15
mm.
3. Datum A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.

240/264 DS12308 Rev 4

L9788 Package information

5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.

6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. Dimensions D2 and E2 show the maximum exposed metal area on the package
surface where the exposed pad is located (if present). It includes all metal protrusions
from exposed pad itself.
14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of
exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by
internal edge of inner groove.
15. The optional exposed pad is generally coincident with the top or bottom side of the
package and not allowed to protrude beyond that surface.
16. “N” is the number of terminal positions for the specified body size.

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Package information L9788

19.2 LQFP100 (14x14x1.4 mm exp. pad down) marking information

Figure 90. LQFP100 (14x14x1.4 mm exp. pad down) marking information
PACKAGE FACE : TOP LEGEND

Unmarkable Surface
B
A
Marking Composition Field
C a - 105946 - EJECTOR
D b - 105947 - NO MARK PKG AREA
A - 107166 - Second_lvl_intct
E F G H I
b
B - 107167 - 2D MATRIX CODE
J C - 107165 - MARKING AREA
D - 107164 - MARKING AREA
K L E - 107163 - Assy Plant
(PP)

F - 107162 - Assy Year

a (Y)
G - 107161 - Assy Week
(WW)
H - 107160 - Diffusion
Traceability Plant
(WX)

I - 107159 - Test & Finishing

Plant
(TF)
J - 107157 - BE Sequence
(LLL)
K - 107156 - COUNTRY OF ORIGIN
(MAX CHAR ALLOWED = 3)

L - 107158 - SS SUBLOT ASSY

Parts marked as ‘ES’ are not yet qualified and therefore not approved for use in production.
ST is not responsible for any consequences resulting from such use. In no event will ST be
liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted prior to any decision to use these engineering samples to run
a qualification activity.

242/264 DS12308 Rev 4

L9788 Device behavior

Appendix A Device behavior

A.1 Summary of all drivers block

Table 110. Summary of all drivers block
Min OVC Vclamp
Drivers Rdson (Ω) STB STG OPL OVC
value (A) Typ (V)

INJ 3 0.6 55 √ √ √ √
SOL 3 0.47 55 √ √ √ √
O2H 3/7.8 0.2 50 √ √ √ √
RLY 1 1.5 50 √ √ √ √
HS 1 1.5 -3.5 √ √ √ √
HSLS
LS 1 1.5 45 √ √ √ √
LED 0.07 20 45 √ √ √ √
MRD 1 - 50 √ √ √ √
IGN 0.1 7 - √ √ √
PreMOS - - - √ √ √ √

A.2 Slew rate and on/off delay time

Figure 91. Slew rate and on/off delay time

MSC_EN
Ton_OUTx

VB VB
OUTx
80% 80%

30%
20%

SR_ON Toff_OUTx SR_OFF

(V/T) (V/T)

GADG1512160940PS

Ton_OUTX is the on delay time of OUTX;

Toff_OUTX is the off delay time of OUTX;
SR_ON is the on slew rate of OUTX;
SR_OFF is the off slew rate of OUTX.

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Device behavior L9788

A.3 Power up/down scenarios

Figure 92. Power up and power down with deglitch concept (not permanent battery)

Key_Tfilter Key_Tfilter

KEY_IN KEY_IN

WK_IN_DET WK_IN

WAKE_UP_EOT_DET WAKE_UP_EOT_DET
WAKE_UP_CAN_DET WAKE_UP_CAN_DET

PHOLD PHOLD

MRD out MRD out

VUV_VB_IN
VUV_VB_CP_OFF
VB_IN VB_IN

Power On Reset Power On Reset

Tuv_filter_vpre
VPRE Vuv_vpre VPRE Vuv_vpre

Tuv_filter_vpre Tuv_filter_vdd5
VDD5 Vuv_vdd5 VDD5 Vuv_vdd5

VTRK Tuv_filter_vdd5 VTRK

Td_uv_rst
RSTN RSTN

SCENARIO 1 - POWER UP by KEY detection t SCENARIO 2 -POWER DOWN during KEY detection t
(with deglitch concept) (with deglitch concept)
not permanent battery not permanent battery
Note*: Power On Reset is activated at the end of power down sequence
without waiting for VUV_VB_CP_OFF
GADG1512160955PS

Figure 93. Power up and power down with boost (permanent battery)

Key_Tfilter
Key_Tfilter

KEY_IN KEY_IN

WK_IN_DET WK_IN

WAKE_UP_EOT_DET WAKE_UP_EOT_DET
WAKE_UP_CAN_DET WAKE_UP_CAN_DET

PHOLD PHOLD

MRD out MRD out

VB_IN VB_IN

Power On Reset Power On Reset

Tuv_filter_vpre
Vuv_vpre Vuv_vpre
VPRE VPRE
Tuv_filter_vdd5
Tuv_filter_vpre Vuv_vdd5 Vuv_vdd5
VDD5 VDD5

Tuv_filter_vdd5
VTRK VTRK
Td_uv_rst
RSTN RSTN

SCENARIO 3A - POWER UP by KEY detection t SCENARIO 3B - POWER DOWN during KEY detection t
permanent battery permanent battery
GADG1512160957PS

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L9788 Device behavior

Figure 94. Power up permanent battery without boost and cranking

VIH
KEY_IN VIL1 KEY_IN

WK_IN_DET WK_IN_DET

WAKE_UP_EOT_DET WAKE_UP_EOT_DET
WAKE_UP_CAN_DET WAKE_UP_CAN_DET

PHOLD PHOLD

OFF ON
MRD out MRD out

VB_IN_TH VBsense VB_IN_TH VBsense

Vuv_vb_in Vuv_vb_in
VB_IN Voff_vb_in VB_IN Voff_vb_in
Voff_vb_in Voff_vb_in

regulator disable regulator enable regulator disable regulator enable

Power On Reset Power On Reset

VPRE VPRE

Tuv_filter_vpre Tuv_filter_vpre
VDD5 VDD5

Tuv_filter_vdd5 Tuv_filter_vdd5
VTRK VTRK

Td_uv_rst Td_uv_rst
RSTN RSTN

SCENARIO 5A - CRANKING UNTIL POWER ON RESET t SCENARIO 5B - CRANKING UNTIL POWER ON RESET t
without boost without boost
KEY level under key_off threshold KEY level under key_on threshold
GADG1512161005PS

Figure 95. Power up permanent battery with boost and cranking

KEY_IN
KEY_IN

WK_IN_DET
WK_IN_DET

WAKE_UP_EOT_DET
WAKE_UP_EOT_DET
WAKE_UP_CAN_DET
WAKE_UP_CAN_DET

PHOLD
PHOLD

MRD out
MRD out
VB_IN_TH Vuv_vb_in Vuv_vb_in VBsense VB_IN_TH VBsense
VB_IN Vuv_vb_in
Voff_vb_in VB_IN Voff_vb_in

Power On Reset regulator disable regulator enable

Power On Reset

VPRE Vuv_vpre Tuv_filter_vpre

VPRE

Vuv_vdd5 Tuv_filter_vdd5
VDD5
VDD5

VTRK
VTRK
Td_uv_rst
RSTN Tuv_filter_vdd5 RSTN

SCENARIO 4 - CRANKING t SCENARIO 6 - CRANKING t

without boost with boost
GADG1512161121PS

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Device behavior L9788

Figure 96. Power up with WK_IN and power down with WK_IN in not permanent battery condition

KEY_IN_DET KEY_IN_DET

WK_IN WK_IN don’t’ care

WK_IN_DET wk_Tfilter WK_IN_DET WK_IN_RST(MSC)

WAKE_UP_EOT_DET WAKE_UP_EOT_DET
WAKE_UP_CAN_DET WAKE_UP_CAN_DET

PHOLD PHOLD

MRD out MRD out

VUV_VB_IN
VB_IN VUV_VB_CP_OFF VB_IN

Power On Reset Power On Reset

Tuv_filter_vpre
Vuv_vpre Vuv_vpre
VPRE VPRE
Tuv_filter_vdd5
Tuv_filter_vpre Vuv_vdd5 Vuv_vdd5
VDD5 VDD5

Tuv_filter_vdd5
VTRK VTRK
Td_uv_rst

RSTN RSTN

SCENARIO 7 - POWER UP by WK_IN detection t SCENARIO 8 - POWER DOWN during WK_IN detection t
not permanent battery not permanent battery
Note*: Power On Reset is activated at the end of power down sequence
without waiting for VUV_VB_CP_OFF
GADG1512161218PS

Figure 97. Power up with WK_IN and power down with WK_IN in permanent battery condition

KEY_IN_DET KEY_IN_DET

WK_IN WK_IN Don’t’ care

WK_IN_DET wk_Tfilter WK_IN_DET WK_IN_RST (MSC)

WAKE_UP_EOT_DET WAKE_UP_EOT_DET
WAKE_UP_CAN_DET WAKE_UP_CAN_DET

PHOLD PHOLD

OFF OFF
MRD out MRD out

VB_IN VB_IN

Power On Reset Power On Reset

Tuv_filter_vpre
Vuv_vpre VPRE Vuv_vpre
VPRE

Tuv_filter_vdd5
Tuv_filter_vpre Vuv_vdd5 Vuv_vdd5
VDD5 VDD5

Tuv_filter_vdd5
VTRK VTRK

Td_uv_rst
RSTN RSTN

SCENARIO 22 - POWER UP by WK_IN detection t SCENARIO 23 - POWER DOWN during WK_IN detection t
Permanent battery Permanent battery

GADG1512161223PS

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L9788 Device behavior

Figure 98. Power up with WAKE_UP_EOT/CAN and power down with WAKE_UP_EOT/CAN
(Scenario 9 and 10)

KEY_IN_DET KEY_IN_DET

WK_IN_DET WK_IN_DET
WAKE_UP_EOT_RST(MSC)
WAKE_UP_EOT_DET WAKE_UP_EOT_DET
WAKE_UP_CAN_RST(MSC)
WAKE_UP_CAN_DET WAKE_UP_CAN_DET

PHOLD PHOLD

MRD out MRD out

VUV_VB_IN
VB_IN VUV_VB_CP_OFF VB_IN

Power On Reset Power On Reset

Tuv_filter_vpre
Vuv_vpre Vuv_vpre
VPRE VPRE

Tuv_filter_vpre Tuv_filter_vdd5
Vuv_vdd5 Vuv_vdd5
VDD5 VDD5

Tuv_filter_vdd5
VTRK VTRK
Td_uv_rst
RSTN RSTN

SCENARIO 9 - POWER UP by detection of t SCENARIO 10 - POWER DOWN during detection of t

WAKE_UP_TIMER(EOT) or WAKE_UP_CAN(pattern) WAKE_UP_TIMER(EOT) or WAKE_UP_CAN(pattern)
not permanent battery not permanent battery
Note*: Power On Reset is activated at the end of power down sequence
without waiting for VUV_VB_CP_OFF
GADG1512161227PS

Figure 99. Power up with WAKE_UP_EOT/CAN and power down with WAKE_UP_EOT/CAN
(Scenario 24 and 25)

KEY_IN_DET KEY_IN_DET

WK_IN_DET WK_IN_DET

WAKE_UP_EOT_DET
WAKE_UP_EOT_RST(MSC)
WAKE_UP_EOT_DET
WAKE_UP_CAN_DET WAKE_UP_CAN_DET WAKE_UP_CAN_RST(MSC)

PHOLD PHOLD

OFF OFF
MRD out MRD out

VB_IN VB_IN

Power On Reset Power On Reset

Tuv_filter_vpre
VPRE Vuv_vpre VPRE Vuv_vpre

Tuv_filter_vpre Tuv_filter_vdd5
VDD5 Vuv_vdd5 VDD5 Vuv_vdd5

VTRK Tuv_filter_vdd5 VTRK

Td_uv_rst
RSTN RSTN

SCENARIO 24 -POWER UP by detection of t SCENARIO 25 -POWER DOWN during detection of t

WAKE_UP_TIMER(EOT) or WAKE_UP_CAN(pattern) WAKE_UP_TIMER(EOT) or WAKE_UP_CAN(pattern)
permanent battery permanent battery
GADG1512161230PS

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Device behavior L9788

Figure 100. Main relay driver timeout

WK_IN_DET
WAKE_UP_EOT_DET
WAKE_UP_CAN_DET

MRD_EN_TIMEOUT (500ms typ)

PHOLD

OFF ON OFF
MRD out

VB_IN

V3V3A/D
Power On Reset

VPRE

VDD5

VTRK

RSTN

t
SCENARIO 26 – Main Relay Driver Timeout
GADG1512161238PS

Figure 101. Power HOLD

KEY_IN_DET

WK_IN_DET

WAKE_UP_EOT_DET
WAKE_UP_CAN_DET

PHOLD MSC_PHOLD_EN=0
or
PHOLD_TIMEOUT
MRD out
VUV_VB_IN
VUV_VB_CP_OFF
VB_IN

Power On Reset
Tuv_filter_vpre
Vuv_vpre Vuv_vpre
VPRE
Tuv_filter_vpre Tuv_filter_vdd5
Vuv_vdd5 Vuv_vdd5
VDD5
Tuv_filter_vdd5
VTRK
Td_uv_rst

RSTN

SCENARIO 11 - POWER HOLD t

not permanent battery
Note*: Power On Reset is activated at the end of power down sequence
without waiting for VUV_VB_CP_OFF
GADG1512161244PS

According to reset matrix power down is also produced by Watchdog PWR_CNT counter
overflow during KEY_IN low. In these cases the power down sequence is actuated without
considering VDD5 undervoltage.

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L9788 Device behavior

A.4 Main relay scenario

Figure 102. Overcurrent OVC removed before VB present with KEY_IN high and Overcurrent OVC
removed before VB present with KEY_IN stays high

Key_Tfilter Key_Tfilter

KEY_IN KEY_IN

WK_IN_DET WK_IN

WAKE_UP_EOT_DET WAKE_UP_EOT_DET
WAKE_UP_CAN_DET WAKE_UP_CAN_DET

PHOLD PHOLD

MRD out MRD out

OVC OVC
FAULT FAULT

I_LS_ovc_flt I_LS_ovc_flt T_res

Internal OVC flag Internal OVC flag
OVC flag keeps MRD off until OVC flag keeps MRD off
VUV_VB_CP_OFF VUV_VB_CP_OFF
KEY_OFF and KEY_ON again during restart time
VB_IN VUV_VB_IN VB_IN VUV_VB_IN

Power On Reset Power On Reset

VPRE VPRE

SCENARIO 12 - MRD -Overcurrent t SCENARIO 13 - MRD -Overcurrent t

OVC removed before VB present with KEY_IN high OVC removed before VB present with KEY_IN stays high

GADG1512161248PS

Figure 103. Overcurrent OVC permanent after VB present with KEY_IN high

Key_Tfilter

KEY_IN

WK_IN_DET

WAKE_UP_EOT_DET
WAKE_UP_CAN_DET

PHOLD

MRD out

FAULT OVC

Internal OVC flag I_LS_ovc_flt

T_res T_res
I_LS_ovc_flt
VB_IN VUV_VB_CP_OFF VUV_VB_CP_OFF
VUV_VB_IN VUV_VB_IN

Power On Reset

VPRE

SCENARIO 14 - MRD - Overcurrent t

OVC permanent after VB present with KEY_IN high
GADG1512161501PS

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Device behavior L9788

Figure 104. Overcurrent OVC permanent after VB present with KEY_IN high - unlimited retry

Key_Tfilter

KEY_IN

WK_IN_DET

WAKE_UP_EOT_DET
WAKE_UP_CAN_DET

PHOLD

MRD out

FAULT OVC OVC OVC

Internal OVC flag I_LS_ovc_flt

T_res T_res
I_LS_ovc_flt
VB_IN VUV_VB_CP_OFF
VUV_VB_IN

Power On Reset

VPRE

SCENARIO 27 - MRD - Overcurrent t

OVC permanent after VB present with KEY_IN high - unlimited retry
GADG1512161515PS

Figure 105. Overcurrent OVC removed before Tres activation with KEY_IN high and Overcurrent
OVC permanent in PHOLD

Key_Tfilter Key_Tfilter

KEY_IN KEY_IN

WK_IN_DET WK_IN_DET

WAKE_UP_EOT_DET WAKE_UP_EOT_DET
WAKE_UP_CAN_DET WAKE_UP_CAN_DET

PHOLD PHOLD

MRD out MRD out

OVC OVC
FAULT FAULT

I_LS_ovc_flt I_LS_ovc_flt
Internal OVC flag Internal OVC flag

VUV_VB_CP_OFF VUV_VB_CP_OFF VUV_VB_CP_OFF

VB_IN VUV_VB_IN VUV_VB_IN VB_IN VUV_VB_IN

Power On Reset Power On Reset

VPRE VPRE

SCENARIO 15 - MRD - Overcurrent t SCENARIO 16 - MRD - Overcurrent t

OVC removed before Power On Reset with KEY_IN high OVC permanent in PHOLD

GADG1512161518PS

250/264 DS12308 Rev 4

L9788 Device behavior

Figure 106. Overcurrent not permanent battery OVC not permanent before VB present with
WK_IN/WAKE_UP_EOT/CAN detection (scenario 17)

KEY_IN

WK_IN_DET
WAKE_UP_EOT_DET
WAKE_UP_CAN_DET
MRD_EN_TIMEOUT (500ms typ)

PHOLD

MRD out

OVC OVC OVC NO FAULT

FAULT

Internal OVC flag T_res T_res T_res

I_LS_ovc_flt I_LS_ovc_flt I_LS_ovc_flt VUV_VB_CP_OFF
VB_IN VUV_VB_IN

Power On Reset

VPRE

SCENARIO 17 - MRD - Overcurrent not permanent battery t

OVC not permanent before VB present with WK_IN / WAKE_UP_EOT / CAN detection

GADG1512161527PS

Figure 107. Overcurrent not permanent battery OVC not permanent before VB present with
WK_IN/WAKE_UP_EOT/CAN detection (scenario 18)

KEY_IN

WK_IN_DET
WAKE_UP_EOT_DET
WAKE_UP_CAN_DET
MRD_EN_TIMEOUT (500ms typ)

PHOLD

MRD out

OVC OVC OVC OVC

FAULT

Internal OVC flag T_res T_res T_res

I_LS_ovc_flt I_LS_ovc_flt I_LS_ovc_flt
VB_IN

Power On Reset

VPRE

SCENARIO 18 - MRD - Overcurrent not permanent battery t

OVC permanent before VB present with WK_IN / WAKE_UP_EOT detection

GADG1612160813PS

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Device behavior L9788

Figure 108. Overcurrent not permanent battery OVC not permanent after VB present with
WK_IN/WAKE_UP_EOT/CAN detection - no retry

KEY_IN_DET

WK_IN_DET
WAKE_UP_EOT_DET
WAKE_UP_CAN_DET

PHOLD

on off
MRD out

OVC
FAULT

I_LS_ovc_flt
Internal OVC flag

VUV_VB_CP_OFF
VB_IN VUV_VB_IN

Power On Reset

VPRE

SCENARIO 31 - MRD - Overcurrent not permanent battery t

OVC permanent after VB present with WK_IN / WAKE_UP_EOT / CAN high – no retry

GADG1612160817PS

Figure 109. Overcurrent in permanent battery restart conditions during KEY or WK_IN or
WK_UP_EOT/CAN detection

power on by KEY detection

KEY_IN
power on by WK_IN detection
WK_IN_DET

WAKE_UP_EOT_DET power on by WAKE_UP_EOT / CAN

WAKE_UP_CAN_DET detection

PHOLD

MSC READ

MSC CMD (ON/OFF)

on off restart on off restart on off restart

MRD out

OVC OVC OVC

FAULT

I_LS_ovc_flt I_LS_ovc_flt I_LS_ovc_flt

Internal OVC flag

VB_IN

V3V3A/D
Power On Reset

VPRE

SCENARIO 19 - MRD overcurrent in permanent battery t

restart conditions during KEY or WK_IN or WAKE_UP_EOT / CAN detection
GADG1612160823PS

Note: In permanent battery when power on by KEY the MSC CMD can only restart driver after
OVC. The MSC CMD OFF has no effect.

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L9788 Device behavior

Figure 110. Overcurrent in permanent battery PHOLD

KEY_IN

WK_IN_DET

WAKE_UP_EOT_DET
WAKE_UP_CAN_DET

PHOLD enabled
PHOLD

MSC READ

MSC CMD (ON/OFF)

MRD out on off restart

OVC
FAULT
I_LS_ovc_flt
Internal OVT flag

VB_IN

Power On Reset

VPRE

SCENARIO 20 - MRD overcurrent in permanent battery t

PHOLD
GADG1612160836PS

Figure 111. Overtemperature in permanent battery restart conditions during KEY or WK_IN or
WAKE_UP_EOT/CAN detection

power on by KEY detection

KEY_IN
power on by WK_IN detection
WK_IN_DET

WAKE_UP_EOT_DET power on by WAKE_UP_EOT / CAN

WAKE_UP_CAN_DET detection

PHOLD

MSC READ

MSC CMD (ON/OFF)

on off restart on off restart on off restart

MRD out

OVT OVT OVT

FAULT

ovt_flt ovt_flt ovt_flt

Internal OVT flag

VB_IN

Power On Reset

VPRE

SCENARIO 21 - MRD overtemperature in permanent battery t

restart conditions during KEY or WK_IN or WAKE_UP_EOT / CAN detection
GADG1612160850PS

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Device behavior L9788

Figure 112. Overtemperature in permanent battery PHOLD

KEY_IN

WK_IN_DET

WAKE_UP_EOT_DET
WAKE_UP_CAN_DET

PHOLD enabled
PHOLD

MSC READ

MSC CMD (ON/OFF) off

MRD out on off restart

ovt_flt
OVT
FAULT
ovt_flt
Internal OVT flag

VB_IN

Power On Reset

VPRE

SCENARIO 29 - MRD overtemperature in permanent battery t

PHOLD
GADG1612160937PS

Figure 113. Overtemperature (permanent fault) in not permanent battery Power on by KEY
detection

KEY_IN_DET

WK_IN_DET

WAKE_UP_EOT_DET
WAKE_UP_CAN_DET

PHOLD

MSC READ

MSC CMD (ON/OFF)

MRD out on off on off on off on off on off

OVT OVT OVT OVT OVT

FAULT
ovt_flt
Internal OVT flag

V UV_VB_CP_OFF
VB_IN V UV_VB_IN

Power On Reset

VDD

SCENARIO 26 - MRD overtemperature (permanent fault) in not permanent battery t

Power on by KEY detection
GADG1612160948PS

254/264 DS12308 Rev 4

L9788 Device behavior

Figure 114. Overtemperature (not permanent fault) in not permanent battery Power on by KEY
detection

KEY_IN_DET

WK_IN_DET

WAKE_UP_EOT_DET
WAKE_UP_CAN_DET

PHOLD

MSC READ

MSC CMD (ON/OFF)

MRD out on off on off on off on off on

OVT OVT OVT OVT

FAULT
ovt_flt
Internal OVT flag

V UV_VB_CP_OFF
VB_IN V UV_VB_IN

Power On Reset

VDD

SCENARIO 27 - MRD overtemperature (not permanent fault) in not permanent battery t

Power on by KEY detection
GADG1612160954PS

Figure 115. Overtemperature in not permanent battery Power on by WK_IN or

WAKE_UP_EOT/CAN detection

KEY_IN_DET

WK_IN_DET
WAKE_UP_EOT_DET
WAKE_UP_CAN_DET

PHOLD

MSC READ

MSC CMD (ON/OFF)

MRD out On Off

OVT OVT
FAULT
ovt_flt
Internal OVT flag

VB_IN

Power On Reset

VPRE

SCENARIO 28 - MRD overtemperature in not permanent battery t

Power on by WK_IN or WAKE_UP_EOT/CAN detection
GADG1612161123PS

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Device behavior L9788

Figure 116. Overtemperature in not permanent battery Power on by PHOLD

KEY_IN_DET
WK_IN_DET
WAKE_UP_EOT_DET
WAKE_UP_CAN_DET

PHOLD

MSC READ

MSC CMD (ON/OFF)

MRD out On Off

OVT OVT
FAULT
ovt_flt
Internal OVT flag

VB_IN

Power On Reset

VPRE

SCENARIO 30 - MRD overtemperature in not permanent battery t

Power on by PHOLD
GADG1612161129PS

256/264 DS12308 Rev 4

 Appendix B Application diagrams

L9788
Figure 117. Driver/predriver section application diagram
IGN3
IGN2 IGN4
Q1 IGN5
Q2 IGN6
Q3 R1
R2 Q4
C1 R3
C2 C3 R4
Q5
C4 R5
R6
IGN1 R7 R8 C5
R9
Q6 GND R10
R11 GND GND
GND

32

33

43

44

62

61
GND DRN1
C6
D1Q7

IGN1

IGN2

IGN3

IGN4

IGN5

IGN6
R12
G1
DRN2
60
PDR1_DRN D2 S1
GND 59
PDR1_GATE DRN3
56 G2
PDR2_DRN D1
55 Q8A
PDR2_GATE DRN4
57 GND
PDR3_DRN G1 S2
58 D2 Q8B
PDR3_GATE
45 53 DRN5
MSC_EN MSC_EN PDR4_DRN G2
46 54 D1 S1
MSC_CK_P R13 MSC_CK_P PDR4_GATE Q9A
DS12308 Rev 4

52 GND
PDR5_DRN
47 51 G1 S2
MSC_CK_N MSC_CK_N PDR5_GATE Q9B
48
MSC_DI_P R14 MSC_DI_P GND
S1
49
MSC_DI_N MSC_DI_N GND STR1_DRN
28
MSC_DO MSC_DO STR1_SRC
R15 STR2_DRN
VDDIO 15 GND STR2_SRC
STR1_DRN
24 16 STR3_DRN
WDA WDA STR1_SRC STR3_SRC
18
STR2_DRN
26 17
SEO_OUT SEO_OUT STR2_SRC
19
STR3_DRN
20
STR3_SRC
L9788
36 INJ1
INJ1
29 39 INJ2
INJ_ENA INJ_ENA INJ2
30 12 INJ3
EN_N EN_N INJ3
31 14 INJ4
EN_P EN_P INJ4
90 O2H1
O2H1A
97 89 O2H1B
GND GND O2H1B
83 86 O2H2
O2H2_CURRENT Curr_sense_O2H2 O2H2A
93 85
O2H1_CURRENT Curr_sense_O2H1 O2H2B
65 SOL1
R16 R17 SOL1
63 SOL2
SOL2
34 RLY1

Application diagrams
RLY1
35 RLY2
RLY2
40 RLY3
GND GND RLY3
41 RLY4
RLY4
42 RLY5
O2H1_PGNDA
O2H1_PGNDB
O2H2_PGNDA
O2H2_PGNDB
SOL12_PGND

RLY5
INJ34_PGND
INJ1_PGND
INJ2_PGND

PDR_GND

21 LED1
LED1
22 LED2
LED2
GND1

C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20C21
O2
O2
38
13

87

50
37

64
70
91
88

84
257/264

GND

GND GADG2306170945PS
 Figure 118. Interface section application diagram
258/264

Application diagrams
VD D5 VDDIO
VB_STBY VDD5
C22 C23 3V3_EXT

99

92

27
VDDIO

VDDIO
VB_CAN

VDD_CAN
GND

L1
98 95 CANL
CAN_TX CANTX CANL
96 94 CANH
CAN_RX CANRX CANH
ACT45B-101
R19 R20 C24 C25
23
GND
75
GND
71
AD_TEST AD_TEST
C26 VBAT

GND
RSTN
R22 25
RSTN L9788 GND GND
74
RSTC RSTC
GND D1
R23
4
LIN_TX LINTX
5 6 LIN
LIN_RX LINRX LIN
DS12308 Rev 4

1
R24
R25 JP2 D2A JP3
E_F_DGA 1
FLW_IN_P

GND_CAN
C27
R26 R27 JP4 3 FLW_OUT

3
FLW_OUT FLW_OUT
FLW_IN_P 2 C28 C29
FLW_IN_N GND LIN Master/Slave
C30
GND C31 R28

100
E_F_DGB FLW_IN_N
C32 C33 C34 GND

GND
VTRK1
GND GND GND
R29
VDD5
E_F_DGH R30

C35 R31

GND R32

GND

GADG2306171146PS

L9788
 Figure 119. Multi regulator supply section application diagram

L9788
D3
D4 82
L2
78
VBAT VB_IN VB_IN_SW
C36 C53 C54 C37 80
BUCK_C_BST
79 L3
D5 CP
TVS 81
BUCK_SW
D1
GND GND GND
C39 C43 G1 76 C40
C42 C41Q10 Boost_G
D7 R33
TVS S1 R34

GND
69
GND VPRE
GND GND GNDGND
R35 77
VBAT_SENSE
L9788 VDD5_GATE
73 Q11

72 VDD5
VDD5_IN
C44 C45

KEY_IN 9
KEY_IN
R36
DS12308 Rev 4

WK_IN 10
WK_IN GND GND
R37
MRD 11 68 VTRK1
MRD VSENSE1
VB_STBY 7 67 VTRK2
VB_STBY VSENSE2
C46 C47 C48 8 66 VTRK3
VSENSE4_MON TAB_GND VSENSE3
C49 C51 C52 C50

TAB
GND GND GND
VTRK_EXT_MON GND GND GND

GADG2306171202PS

Application diagrams
259/264
Application diagrams L9788

B.1 Bill of material

Table 111. Bill of material
Symbol Parameter Min Typ Max Unit Note

C39 Battery filter capacitor - 4.7 - nF -

Reverse battery
D3 - - - - Choice: STTH4R02
protection diode
D5,D7 TVS diode - - - - Choice: TPSMB36A
battery decoupling
C42 - 100 nF
capacitor
battery decoupling
C41 - 100 µF
capacitor
L2 Boost inductance - - - - see Table 28
choice: STD20NF06L
Q10 Boost MOSFET - - - - see Table 27 and
Table 28
choice:
D4 Boost diode - - - - STPS10H100C see
Table 28
C36 Cout_boost 36 40 150 µF see Table 28
C53 Cout_boost_ALU 0 330 470 µF see Table 28
R33 Rg - 2.2 - Ω see Table 28
R34 Rg_pd - 150 - kΩ see Table 28
External charge pump
C37 80 100 120 nF see Table 39
capacitor
R35 Rsense 10 22 30 kΩ see Table 28
C43 filter capacitor - 100 - nF Optional
KEY_IN protection
R36 - 1 - kΩ -
resistor
WK_IN protection
R37 - 1 - kΩ -
resistor
C46, C47, C48,
filter capacitor - 100 - nF -
C49,C44, C54
C38 CBST - 47 - nF see Table 30
L3 Lvpre 15 22 29 µH see Table 30
Choice: STPS5L60-Y
D6 Dvbuck_CTRL - - - -
see Table 30
C40 Cvpre 15 40 150 µF see Table 30
choice: STD20NF06L
Q11 - - - - - see Table 34 and
Table 35
C45 CVDD5 5 20 60 µF see Table 35

260/264 DS12308 Rev 4

L9788 Application diagrams

Table 111. Bill of material (continued)

Symbol Parameter Min Typ Max Unit Note

C50,C51,C52 CVS1/2/3 0.38 0.47 20 µF see Table 32

R1,R2,R3,R4,R5,
IGBT gate resistor - 1 - kΩ -
R11
R6,R7,R8,R9,R10, IGBT Gate discharge
- 4.7 0 kΩ -
R12 resistor
C1,C2,C3,C4,C5,C6 filter capacitor - 1.5 - nF -
MSC differential line
R13,R14 - 100 - Ω -
adapting resistor
WDA pull-up external
R15 50 - 250 kΩ See Table 24
resistor
Q7, Q8A, Q8B, Q9A,
- - - - - choice: STL15DN4F
Q9B
C7,C8,C9,C10,C11,C1
2,C13,C14,C15,C16,C filter capacitor - 4.7 - nF -
17,C18,C19,C20,C21
R16, R17 - - 5.1 - kΩ See Table 46
C22,C23 decoupling capacitor - 100 - nF -
R22,R23 protection resistor - 1 - kΩ -
filter capacitor (VRS
C27, C32 - 100 - pF -
sensor configuration)
filter capacitor (VRS
C30 - 470 - pF -
sensor configuration)
filter resistor (VRS
R26,R27 - 33 - kΩ -
sensor configuration)
filter capacitor (VRS
C31 - 100 - nF -
sensor configuration)
Protection and reference
R25,R28 resistors (VRS sensor - 10 1% - kΩ see Section 11.2
configuration)
filter capacitor (Hall
C35 - 1 - nF -
sensor configuration)
pull-up resistor (Hall
R29 - 27 - kΩ -
sensor configuration)
Protection and reference
R30 resistor (Hall sensor - 27 - kΩ -
configuration)
Protection and reference
R31,R32 resistor (Hall sensor - 33 - kΩ -
configuration)
C33,C34 filter capacitor - 470 - pF place close to pin
L1 CAN Choke - - - - choice: ACT45B-101

DS12308 Rev 4 261/264

263
Application diagrams L9788

Table 111. Bill of material (continued)

Symbol Parameter Min Typ Max Unit Note

R19, R20 CAN termination resistor - 60 - Ω -

CAN termination
C26 - 4.7 - nF -
capacitor
C24,C25 - - 47 - pF -
D2A - - - - - 27V TVS
D1 Vser Diode - - - - Choice: BAS21
R24 Lin pull-up resistor - 1 - kΩ -
C28 - - - - - Choice: 220pF
Choice: 1 nF (K-Line),
C29 - - - - -
680 pF (LIN)

262/264 DS12308 Rev 4

L9788 Revision history

Revision history
Table 112. Document revision history
Date Revision Changes

30-Jan-2018 1 Initial release.

20-Jun-2018 2 Updated Figure 47: Safety switch off on page 121.
Updated:
– Table 11 (parameter IVB_STBY_ EOT_enable and IVB_STBY_EOT_enable;
03-Dec-2018 3
– “DO: Serial Output Data” on page 178;
– Section 18.3: Upstream communication on page 184.
Updated:
– Figure 90: LQFP100 (14x14x1.4 mm exp. pad down) marking information;
30-May-2022 4
– Table 109: LQFP100 (14x14x1.4 mm exp. pad down) package mechanical data.
Document changed from "Restricted" to "Public".

DS12308 Rev 4 263/264

263
 L9788

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264/264 DS12308 Rev 4