Ghulam Ishaq Khan Institute of Engineering Sciences and

Technology

Electronic Devices and Circuits

EE-231
CH:4 DC Biasing BJT

Dr. Waleed Tariq Sethi

Assistant Professor
Faculty of Electrical Engineering
GIK Institute of Engineering Sciences and Technology
Email : [email protected]

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
CHAPTER OBJECTIVES

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
Introduction
• It is wrong to assume that transistor can raise the level
of any AC input without the assistance of an external
(DC) energy source
• The amplified output AC power level is the result of energy
from the applied DC sources
• Hence the design of any electronic amplifier has two
components
• The DC portion & the AC portion
• Using the superposition theorem, the analysis for DC
conditions can be made separately from the AC
response
• Though components/parameters (resistors, capacitors etc)
chosen for the required DC levels will affect the AC response

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
• During the design process, a number of mathematical
relations will be used but the most frequent ones are

• In most instances, IB is the first quantity to be

determined
• Once IB is known, the remaining quantities can be found
using the relations stated above

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
Operating Point
• For any transistor the resulting DC current and
voltage establish an operating point on the
characteristic curves
• A region around this point will be used for
amplification purpose
• Since this point is fixed on the characteristic curves
for any given DC values, hence it is known as
quiescent point or Q-point

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
• For every transistor a biasing circuit is designed
• This biasing circuit is designed in such a way as to make the
device operational on a particular Q-point with in the active or
linear region
• For amplification purposes, it is necessary that while biasing
the device, the operational point is chosen in such a way that
the following regions are avoided
• Saturation region
• Cut-off region
• Maximum power constraint
• Another important biasing factor
is the temperature
• Increase in temperature increases
transistor’s current gain (β) and
leakage current ICEO
• This can change the operating
condition set previously by the
biasing network
• Hence the network design must
provide high degree of
temperature stability
Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
Best possible point
of operation. A
proper input signal if
amplified in this Point of operation
region will not drive too close to
the device into non- maximum power
linear regions. and voltage level
Largest possible
current and voltage
swing.

No bias → Device
is completely OFF

Q-point too close to non-linear

regions. An excessively large signal
might drive transistor in to cut-off or
saturation
Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
Types of Transistor Bias
Configuration
• Fixed Bias Configuration
• Also called base bias
• Emitter Bias Configuration
• Voltage Divider Bias Configuration
• Collector Feedback Configuration
• Emitter-follower Configuration
• Common-base Configuration
• Also some other miscellaneous configurations

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Fixed Bias Configuration
• Also known as base bias
• For DC analyses, network can be isolated from AC by
replacing capacitors with an open circuit
• Calculations will show that RB will affect both IB and IC

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Example 4.1
Determine the following for the fixed-bias configuration,
a. IBQ and ICQ
b. VCEQ
c. VB and VC
d. VBC

VB=VBE=0.7V
VC=VCE=4.23V
Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Fixed Bias & Transistor Saturation
• For a given design, saturation • Once ICSat is known, we have an
gives you the maximum value of idea of maximum possible value of
the current collector current for the chosen
• A change in design may drop or design and the level to stay below
raise the saturation level if we expect linear amplification

Approximation

Actual
Prepared by: Dr. Waleed Tariq Sethi-Approximate
Ghulam Ishaq Khan Institute-Spring 2025
 Example 4.2
Determine the saturation level for the network in example 4.1

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 Load Line Analysis - Fixed Bias
• Plot the network output characteristics
• Write the KVL equation for output
• Superimpose the curve defined by the equation on output
characteristics of the network
• Intersection of the two curves define actual operating
conditions or operating point for the network
• Load line basically represents response of a linear circuit to
which a non linear device in question is connected
• The operating point or the Q-point is the point where the
parameters of linear circuit match with parameters of the non-
linear device depending upon how they are connected
• In a fixed bias network, RC will define the slope of network
equation
• Smaller RC (i.e; load resistance in this case) → Steeper curve

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 slope Y-intercept

Fixed VCC and fixed RC

IB changes so IC changes

Fixed VCC and fixed IB Fixed RC and fixed IB

RC changes so IC changes VCC changes so IC changes

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 Example 4.3
• Given the load line, determine the required values of
VCC, RC and RB
Vcc- IcRc - Vce = 0

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 Emitter-Bias Configuration
• Emitter is not grounded directly but
through a resistor
• The inclusion of emitter resistor provides
greater stability to the DC bias against
temperature changes
• Even if there is a change in temperature
or transistor’s β , DC voltages and DC
currents remain close to where they
were set originally
• Procedure for analysis is the same as
that for fixed-bias configuration
• VCC can be separated for input and output
loops
• Calculations can be performed separately
for input and output loops
• The resistor RE always appears (β + 1)
times greater than RE to the input (to be
proved during analysis)
Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Base-Emitter Loop
From Kirchhoff’s voltage
law :
+ VCC - I E R E - VBE - I E R E = 0

Since IE = ( + 1)IB:

VCC - I B R B - ( + 1)I B R E = 0

Solving for IB:

VCC - VBE
IB =
R B + ( + 1)R E
Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Collector-Emitter Loop
From Kirchhoff’s voltage law :

+ I E R E + VCE + I CR C − VCC = 0

Since IE  IC:
VCE = VCC – I C (R C + R E )

Also:

VE = I E R E
VC = VCE + VE = VCC - I CR C
VB = VCC – I R R B = VBE + VE

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Stability of Emitter-Bias: Example 4.5, pg: 173

Fixed Bias Emitter Bias

• IC increases by 100% due to 100% • IC increases by 81% due to 100%

increase in β change in β
• IB remains the same • Unlike fixed-bias, in emitter-bias IB
• VCE decreases by 76% also decreases to reduce the
overall effect of β on IC
• VCE decreases by 35%
• Hence for thePrepared
sameby:change Tariqβ,
Dr. Waleed in Emitter-bias
Sethi- is Institute-Spring
Ghulam Ishaq Khan more stable 2025than Fixed-bias
 Example 4.4, Pg: 172
• Find IB, IC, VCE, VC, VE, VB, VBC

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 Example 4.4

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 Emitter-bias & Transistor
Saturation
• Analysis are performed in the same
manner as were performed for
Fixed-bias
• At saturation, VCE is approximated
to zero and a short is inserted
between collector and emitter
• The addition of emitter resistance
reduces the level of collector
current below the one obtained
with fixed-bias configuration using
the same collector resistor
Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Load Line Analysis: Emitter-Bias
• The load line analysis are almost the same as that of fixed-
bias
• Different levels of IBQ will obviously move the Q-point up
and down the load line

RE and RB can be adjusted to fix IBQ at any point of interest on characteristic curves
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 Example 4.6
Determine the saturation current for the network, (example 4.4)

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 Voltage-Divider Bias Configuration
• The most popular bias configuration for a BJT
• ICQ and VCEQ were dependant on β in previous
configurations
• β is temperature dependant so change in β would change the Q-
point
• Voltage-divider bias is a configuration that is less dependant
on β or in fact independent of β
• Lesser sensitivity to changes in β
• Once the circuit bias is designed and operational then for
any change in β, level of IBQ will change but the operating
point (i.e; Q-point) defined by ICQ and VCEQ will remain fixed
Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
Methods for Analysis
• There are two methods for analyzing a voltage-
divider bias circuit
• Exact Method
• Can be applied to any voltage-divider bias configuration
• Approximate Method
• Can be applied only if specific conditions are satisfied
• More direct analysis
• Lesser time and energy required for calculations
• Can be applied to majority but not all situations

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 Exact Analysis
• Thevenin equivalent
for the input circuit
is drawn

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 Example 4.8
Determine the dc bias voltage VCE and the current IC for the voltage-
divider configuration.

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Approximate Analysis
• Applicable under certain conditions
▪ We know that Ri = (1 + β)RE
▪ Ri >> R2
▪ IB ≈ 0
▪ Hence, I1 = I2 >> IB
• Thus R1 and R2 are series elements
• Ri is equivalent resistance between base
and ground for a transistor with emitter
resistance
• But the most important condition required
for applying the approximate model is
▪ βRE ≥ 10R2
• Calculations for voltages and currents
using approximate analysis will indicate
that β will not appear during calculations
▪ Hence, Q-point will be independent
of β Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Approximate Analysis
Where IB << I1 and I2 and I1  I2 :
R 2 VCC
VB =
R1 + R 2

Where RE > 10R2:

VE
IE =
RE
VE = VB − VBE

From Kirchhoff’s voltage law:

VCE = VCC - I CR C - I E R E

IE  IC
VCE = V CC -I C (R C + R E )

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 Example 4.9
Repeat the analysis example 4.8, using the approximate technique.

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Example 4.10
Transistor Saturation & Load Line
Analysis
• The output circuits of voltage-divider and emitter-
bias are identical
• So, the technique and formulas for finding the
saturation current ICsat and the load line analysis will also
be same

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Collector Feedback Configuration
• Stability of the Q-point against
changes in β can also be achieved by
introducing a feedback path from
collector to base

• The sensitivity to changes in β would

be less as compared to fixed bias
and emitter bias

• Due to the feedback path, the

collector resistor RC is also reflected
back in to input loop

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Base-Emitter Loop
From Kirchhoff’s voltage law:
VCC – ICR C – I B R B – VBE – I E R E = 0

Where IB << IC:

IC = I C + I B = I C

Knowing IC = IB and IE  IC, the

loop equation becomes:
VCC – I B R C − I B R B − VBE − I B R E = 0

Solving for IB:

VCC − VBE
IB =
R B + (R C + R E )

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 Base-Emitter Loop

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 Collector-Emitter Loop
Applying Kirchoff’s voltage law:
IE RE + VCE + ICRC – VCC = 0
Since IC  IC and IC = IB:
IC(RC + RE) + VCE – VCC =0

Solving for VCE:

VCE = VCC – IC(RC + RE)

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
• Having seen different circuits for BJT biasing
networks, a general format for IB and ICQ is

• Where
− V’ = VCC – VBE for
• Fixed-bias, emitter-bias and collector feedback bias
− R’ = 0 for fixed bias
− R’ = (β + 1)RE or βRE in emitter bias
− R’ = RE + RC in collector feedback bias
• As a general rule, if βR’ >>RB ;Q-point will be less
sensitive to changes in β
• R’ is typically larger for a collector feedback
configuration than for an emitter-bias configuration

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 Example 4.12
Determine the quiescent levels of ICQ and VEQ for the network.

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 Example 4.13
Repeat example 4.11 using s beta of 135 .

 = 135

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 Example 4.14
Determine the dc level of IB and VC for the network.

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Saturation Conditions & Load Line
• Once the approximation IC’ = IC is made then
• Equation for saturation current is the same as obtained for
voltage-divider bias and emitter-bias

• Using the same approximation for IC , the load line

obtained will be similar to the one obtained for voltage-
divider bias and emitter-bias

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Additional Configurations
• Emitter Follower Configuration
• Output across emitter leg as long as their a resistor
connected to emitter leg
• Collector is at AC ground
• Common Base Configuration
• Two power supplies are used
• One for driving input of BJT
• One for driving output of BJT

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Emitter Follower Configuration

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Common Base Configuration

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Miscellaneous Bias Configurations

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Difference between Analysis and
Design Problems
• Analysis Problems
• The analysis performed in relation to BJT biasing so far
was done when supply, resistors values etc were already
given
• The provided data was used to find unknown currents and
voltages
• Design Problems
• Currents and voltage levels are specified
• The elements (i.e; resistors) required to establish the desired
current and voltage levels must be determined

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
Design Problems Contd…
• Requirements
• Characteristics of the device
• Network equations
• Circuit analysis laws (KCL, KVL & Ohm’s law)
• Design problem challenges the thinking process of an
engineer to a higher degree than analysis problem
• At times assumptions are made to reach at a particular
solution
• Once the resistor values are calculated then the nearest
values according to industry standards are chosen
• Any variations due to NOT using the calculated values are
accepted as part of design
• The most frequent and basic relation to be used in design
problems is V
Runknown = R
IR
Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Example 4.19
Given the device characteristics in Fig., determine VCC, RB and RC for
the fixed-bias configuration.

Characteristics Prepared
withby:load-line; Fixed Bias circuit.
Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
Another technique for Solving Design
Problems
• At times it is difficult to compute both RC and RE in the
output loop due to a limited amount of given information
• e.g; the manufacturer might just provide a specific Q-point and
the supply voltage
• Such a scenario requires an engineering judgment such as
to estimate the level of VE compared to VCC
• Some books follow a rule of thumb where
• VB = 1/3 of VCC
• VCE and VCB = 1/3 of VCC
• ICRC = 1/3 of VCC
• And the remaining of VCC goes to VE
• In this chapter VE is mostly 1/4 to 1/10 of VCC
Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Design of a Bias Circuit with an
Emitter Feedback Resistor
The emitter resistor
cannot be
unreasonably large
because the voltage
across it limits the
range of swing of the
voltage from the
collector to emitter.

The supply voltage and operating point selected from the manufacturer’s
information on the transistor used on the amplifier.
Emitter-stabilized bias circuit for design consideration.
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 Example 4.22
Determine the resistor values, for the indicated operating point and
supply voltage.

Emitter-stabilized bias circuit for design consideration.

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Transistor Switching Networks
Transistors with only the DC source applied can be used as electronic
switches.
No DC source or biasing connected to the base (input). Only DC supply
connected at the output loop

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Transistor Switching Networks
Saturation current:
VCC
I Csat =
RC

To ensure saturation:
I
I B  Csat
 dc

Emitter-collector resistance
at saturation and cutoff:
VCEsat
R sat =
I Csat

VCC
R cutoff =
I CEO

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 Example 4.24
Determine RB and RC for the transistor inverter, if Icsat=10mA.

Inverter. Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 Switching Time
Transistor switching times:
t on = t r + t d
t off = t s + t f

td delay time
tr rise time
ts storage time
tf fall time

Where ton total time for the transistor to switch from “off” to “on”
Where toff total time for the transistor to switch from “on” to “off”

Defining the time intervals of a pulse waveform.

Prepared by: Dr. Waleed Tariq Sethi- Ghulam Ishaq Khan Institute-Spring 2025
 pnp Transistors

The analysis for pnp transistor biasing circuits is the same as

that for npn transistor circuits. The only difference is that the
currents are flowing in the opposite direction.

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 pnp Transistors

pnp transistor in an emitter-stabilized configuration.

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